Expt.No: 1 STUDY OF SIMULATION TOOLSDate :

AIM:

To study the Simulation tools.

THEORY:Creating a Test Bench for Simulation:

In this section, you will create a test bench waveform containing input stimulus you can use to simulate the counter module. This test bench waveform is a graphical view of a test bench. It is used with a simulator to verify that the counter design meets both behavioral and timing design requirements. You will use the Waveform Editor to create a test benchwaveform (TBW) file.

1. Select the counter HDL file in the Sources in Project window.

2. Create a new source by selecting Project _ New Source.

3. In the New Source window, select Test Bench Waveform as the source type, and type test bench in the File Name field.

4. Click Next.

5. The Source File dialog box shows that you are associating the test bench with the source file: counter. Click Next.

6. Click Finish. You need to set initial values for your test bench waveform in the Initialize Timing dialog box before the test bench waveform editing window opens.

7. Fill in the fields in the Initialize Timing dialog box using the information below: Clock Time High: 20 ns. Clock Time Low: 20 ns. Input Setup Time: 10 ns. Output Valid Delay: 10 ns. Initial Offset: 0 ns Global Signals: GSR (FPGA)

Leave the remaining fields with their default values.8. Click OK to open the waveform editor. The blue shaded areas are associated with each input signal and correspond to the Input Setup Time in the Initialize Timing dialog box. In this tutorial, the input transitions occur at the edge of the blue cells located under each rising edge of the CLOCK input.

Fig 2: Waveform Editor - Test Bench

Fig 3:Waveform Editor - Expected Results

9. In this design, the only stimulus that you will provide is on the DIRECTION port. Make the transitions as shown below for the DIRECTION port:

Click on the blue cell at approximately the 300 ns clock transition. The signal switches to high at this point.

Click on the blue cell at approximately the 900 ns clock transition. The signal switches back to low.

Click on the blue cell at approximately the 1400 ns clock transition. The signal switches to high again.

10. Select File _ Save to save the waveform. In the Sources in Project window, the TBW file is automatically added to your project.

11. Close the Waveform Editor window.

Adding Expected Results to the Test Bench Waveform:

In this step you will create a self-checking test bench with expected outputs that correspond to your inputs. The input setup and output delay numbers that were entered into the Initialize Timing dialog when you started the waveform editor are evaluated against actual results when the design is simulated. This can be useful in the Simulate Post- Place & Route HDL Model process, to verify that the design behaves as expected in the target device both in terms of functionality and timing.To create a self-checking test bench, you can edit output transitions manually, or you can run the Generate Expected Results process:1. Select the testbench.tbw file in the Sources in Project window.

2. Double-click the Generate Expected Simulation Results process. This process converts the TBW into HDL and then simulates it in a background process.

3. The Expected Results dialog box will open. Select Yes to post the results in the waveform editor.

4. Click the “+” to expand the COUNT_OUT bus and view the transitions that correspond to the Output Valid Delay time (yellow cells) in the Initialize Timing dialog box.

5. Select File _ Save to save the waveform.

6. Close the Waveform Editor. Now that you have a test bench, you are ready to simulate your design.

Simulating the Behavioral Model (ISE Simulator):

If you are using ISE Base or Foundation, you can simulate your design with the ISE Simulator. If you wish to simulate your design with a ModelSim simulator,

skip this section and proceed to the “Simulating the Behavioral Model (ModelSim)” section.

Fig 4: Simulator Processes for Test Bench

Fig 5: Behavioral Simulation in ISE Simulator

To run the integrated simulation processes in ISE:1. Select the test bench waveform in the Sources in Project window. You can see the Xilinx ISE Simulator processes in the Processes for Source window.

2. Double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation to the end of the test bench.

3. To see your simulation results, select the test bench tab and zoom in on the transitions. You can use the zoom icons in the waveform view, or right click and select a zoom command.The ISE window, including the waveform view.

4. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port.5. Close the waveform view window. You have completed simulation of your design using the ISE Simulator. Skip past the ModelSim section below and proceed to the “Creating and Editing Timing and AreaConstraints” section.

Simulating the Behavioral Model (ModelSim):

If you have a ModelSim simulator installed, you can simulate your design using the integrated ModelSim flow. You can run processes from within ISE which launches the installed ModelSim simulator.

To run the integrated simulation processes in ISE:

1. Select the test bench in the Sources in Project window. You can see ModelSim Simulator processes in the Processes for Source window in Fig 6.

Fig 6: Simulator Processes for Test Bench

Fig 7: Behavioral Simulation in ModelSim

2. Double-click the Simulate Behavioral Model process. The ModelSim simulator opens and runs your simulation to the end of the test bench.The ModelSim window, including the waveform, should look like Fig 7.

To see your simulation results, view the Wave window.

1. Right-click in the Wave window and select a zoom command.

2. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port.

3. Close the ModelSim window.

RESULT:

Expt.No: 2 STUDY OF SYNTHESIS TOOLS

Date :

AIM:

To study the Synthesis tools.

THEORY:

Now that you have created the source files, verified the design’s behavior with simulation, and added constraints, you are ready to synthesize and implement the design.

Implementing the Design:1. Select the counter source file in the Sources in Project window.

2. In the Processes for Source window, click the “+” sign next to Implement Design. The Translate, Map, and Place & Route processes are displayed. Expand those processes as well by clicking on the “+” sign. You can see that there are many sub-processes and options that can be run during design implementation.

3. Double-click the top level Implement Design process.ISE determines the current state of your design and runs the processes needed to pull your design through implementation. In this case, ISE runs the Translate, Map and PAR processes. Your design is now pulled through to a placed-and-routed state. This feature is called the “pull through model.”

4. After the processes have finished running, notice the status markers in the Processes for Source window. You should see green checkmarks next to several of the processes, indicating that they ran successfully. If there are any yellow exclamation points, check the warnings in the Console tab or the Warnings tab within the Transcript window. If a red X appears next to a process, you must locate and fix the error before you can continue.

Verification of Synthesis: Your synthesized design can be viewed as a schematic in the Register Transfer Level (RTL) Viewer. The schematic view shows gates and elements independent of the targeted Xilinx® device.

1. In the Processes for Source window, double-click View RTL Schematic found in the Synthesize - XST process group. The top level schematic representation of your synthesized design opens in the workspace

2. Right-click on the symbol and select Push Into the Selected Instance to view the schematic in detail. The Design tab appears in the Sources in Project window, enabling you to view the design hierarchy. In the schematic, you can see the design components you created in the HDL source, and you can “push into” symbols to view increasing levels of detail.

3. Close the schematic window.

Figure: RTL Viewer - Detailed View

RESULT:

EXP.NO: 3Date : BACK ANNOTATION FOR FPGAS .

AIM: To study the Place and Root and Back annotation for FPGAs.

THEORY:

After implementation is complete, you can verify your design before downloading it to a device.

Viewing Placement:

In this section, you will use the Floor planner to verify your pin outs and placement. Floor planner is also very useful for creating area groups for designs

1. Select the counter source file in the Sources in Project window.

2. Click the “+” sign to expand the Place & Route group of processes.

3. Double-click the View/Edit Placed Design (Floor planner) process. The Floor planner view opens.

4. Select View _ Zoom _ To Box and then use the mouse to draw a box around the counter instance, shown in green on the right side of the chip.

5. This Fig 1 shows where the entire design was placed. Click on any of the components listed in the Design Hierarchy window to see where each component is placed.

6. Zoom in to the right side of the chip even more, and place your mouse over the K13pad. You can see that your pinout constraint was applied - the DIRECTION pin is placed at K13.

7. Close the Floor planner without saving.

Viewing Resource Utilization in Reports:

Many ISE processes produce summary reports which enable you to check information about your design after each process is run. Detailed reports are available from the Processes for Source window. You can also view summary information and access most often-utilized reports in the Design Summary.1. Click on the Design Summary tab at the bottom of the window. If you closed the summary during this tutorial, you can reopen it by double-clicking the View Design Summary process.

Figure 3: Timing Analyzer - Timing Summary

Figure 4: FPGA Editor - Detailed View

2. In the Device Utilization Summary section, observe the number of Slice Flip Flops that were used during implementation. You should see 4 flip flops, since you implemented a 4-bit counter.3. To see other reports, scroll to the bottom of the Design Summary. You can click on a report from here to view it in the ISE Text Editor.

Timing Closure:

In this section, you will run timing analysis on your design to verify that your timing constraints were met. Timing closure is the process of working on your design to ensure that it meets your necessary timing requirements. ISE provides several tools to assist with timing closure.

1. In the Processes for Source window, under the Place & Route group of processes, expand the Generate Post-Place & Route Static Timing group by clicking the “+”sign.

2. Double-click the Analyze Post-Place & Route Static Timing process. The Timing Analyzer opens.

3. To analyze the design, select Analyze Against Timing Constraints. The Analyze with Timing Constraints dialog box opens.

4. Click OK. When analysis is complete, the timing report opens.

5. Select Timing summary from the Timing Report Description tree in the left window. This displays the summary section of the timing report, where you can see that no timing errors were reported.

6. Close the Timing Analyzer without saving.

Viewing the Placed and Routed Design:

In this section, you will use the FPGA Editor to view the design. You can view your design on the FPGA device, as well as edit the placement and routing with the FPGA Editor.

1. Double-click the View/Edit Routed Design (FPGA Editor) process found in the Place & Route group of processes. Your implemented design opens in the FPGA Editor.

2. Look in the List window to examine your design components.

3. Click on the COUNT_OUT K12 IOB in the List window to select the row. This is one of the outputs in your design.

4. With the COUNT_OUT K12 row selected, select View _ Zoom Selection. In the editor window, you can see the COUNT_OUT<0> IOB highlighted in red.5. Push into (double-click) the red-highlighted COUNT_OUT K12 IOB. You should see Fig 4.

6. Enlarge the window and zoom in so you can see more detail. This view shows the inside of an FPGA at the lowest viewable level. The blue line shows the route that is used through the IOB. The red lines show the routes that are available.

Figure 5: Simulator Processes for Test Bench

Figure 6: Timing Simulation in ISE Simulator

7. Verify that the signal goes to the pad as an output.

8. Close the FPGA Editor.

Timing Simulation (ISE Simulator):

You can verify that your design meets your timing requirements by running a timing simulation. You can use the same test bench waveform that was used earlier in the design flow for behavioral simulation. When running timing simulation, the ISE tools create a structural HDL file which includes timing information available after Place and Route is run. The simulator will run on a model that is created based on the design to be downloaded to the FPGA. If you are using ISE Base or Foundation, you can simulate your design with the ISE Simulator. To simulate your design with ModelSim, skip to the “Timing Simulation (ModelSim)” section.

To run the integrated simulation processes:

1. Select the test bench waveform in the Sources in Project window. You can see the ISE Simulator processes in the Processes for Source window.

2. Double-click the Simulate Post-Place & Route Model process. This process generates a timing-annotated net list from the implemented design and simulates it. The resulting simulation is displayed in the Waveform Viewer. These results look different than those you saw in the behavioral simulation earlier in this tutorial. These results show timing delays.3. To see your simulation results, zoom in on the transitions and view the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port.

4. Zoom in again to see the timing delay between a rising clock edge and an output transition.

5. Click the Measure Marker button and then click near the 300 ns mark. Drag the second marker to the point where the output becomes stable to see the time delay between the clock edge and the transition.

6. Close the waveform view window. You have completed timing simulation of your design using the ISE Simulator. Skip past the ModelSim section below, and proceed to the “Creating Configuration Data” section.

Timing Simulation (ModelSim):

If you have a ModelSim simulator installed, you can simulate your design using the integrated ModelSim flow. You can run processes from within ISE which launches the installed ModelSim simulator.

1. To run the integrated simulation processes, select the test bench in the Sources in Project window. You can see the ModelSim Simulator processes in the Processes for Source window.

Figure 7: Simulator Processes for Test Bench

Figure 8: Timing Simulation in ModelSim

2. Double-click the Simulate Post-Place & Route VHDL/Verilog Model process.

3. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port.

4. Zoom in on the rising clock edges to see that the output transitions occur slightly later due to the timing delay.

5. Close the ModelSim window.

RESULT:

PARALLEL SIGNED ADDERExpt No:13 Date:

AIM:

To design and simulate the parallel signed adder using verilog HDL .

APPARATUS REQUIRED:

Xilinx ISE 10.1.BLOCK DIAGRAM:

Pipelined design partition of parallel adder

PROGRAM:

// PARALLEL SIGNED ADDER.

module adder12s ( clk,n0,n1,n2,n3,n4,n5,n6,n7,sum) ;input clk ;input [11:0] n0 ;input [11:0] n1 ;input [11:0] n2 ;input [11:0] n3 ;input [11:0] n4 ;input [11:0] n5 ;input [11:0] n6 ;input [11:0] n7 ;output [14:0] sum ;wire [7:0] s00_lsb ;wire [7:0] s01_lsb ;wire [7:0] s02_lsb ;wire [7:0] s03_lsb ;wire [5:0] s00_msb ;wire [5:0] s01_msb ;wire [5:0] s02_msb ;wire [5:0] s03_msb ;wire [7:0] s10_lsb ;wire [7:0] s11_lsb ;wire [6:0] s10_msb ;wire [6:0] s11_msb ;wire [7:0] s20_lsb ;reg [11:7] n0_reg1 ;reg [11:7] n1_reg1 ;reg [11:7] n2_reg1 ;reg [11:7] n3_reg1 ;reg [11:7] n4_reg1 ;reg [11:7] n5_reg1 ;reg [11:7] n6_reg1 ;reg [11:7] n7_reg1 ;reg [7:0] s00_lsbreg1 ;

reg [7:0] s01_lsbreg1 ;reg [7:0] s02_lsbreg1 ;reg [7:0] s03_lsbreg1 ;reg [5:0] s00_msbreg2 ;reg [5:0] s01_msbreg2 ;reg [5:0] s02_msbreg2 ;reg [5:0] s03_msbreg2 ;reg [6:0] s00_lsbreg2 ;reg [6:0] s01_lsbreg2 ;reg [6:0] s02_lsbreg2 ;reg [6:0] s03_lsbreg2 ;reg [7:0] s10_lsbreg3 ;reg [7:0] s11_lsbreg3 ;reg [5:0] s00_msbreg3 ;reg [5:0] s01_msbreg3 ;reg [5:0] s02_msbreg3 ;reg [5:0] s03_msbreg3 ;reg [6:0] s10_lsbreg4 ;reg [6:0] s11_lsbreg4 ;reg [6:0] s10_msbreg4 ;reg [6:0] s11_msbreg4 ;reg [6:0] s10_msbreg5 ;reg [6:0] s11_msbreg5 ;reg s20_lsbreg5cy ;reg [6:0] s20_lsbreg5 ;// First Stage Additionassign s00_lsb[7:0] = n0[6:0]+n1[6:0] ;// Add lsb first - s00_lsb[7] is the carryassign s01_lsb[7:0] = n2[6:0]+n3[6:0] ;// n0-n7 lsb need not be registered since addition is already carried out here.assign s02_lsb[7:0] = n4[6:0]+n5[6:0] ;assign s03_lsb[7:0] = n6[6:0]+n7[6:0] ;always @ (posedge clk)// Pipeline 1: clk (1). Register msb to continue// addition of msb.beginn0_reg1[11:7] <= n0[11:7] ;// Preserve all inputs for msb addition during the clk(2).n1_reg1[11:7] <= n1[11:7] ;n2_reg1[11:7] <= n2[11:7] ;

n3_reg1[11:7] <= n3[11:7] ;n4_reg1[11:7] <= n4[11:7] ;n5_reg1[11:7] <= n5[11:7] ;n6_reg1[11:7] <= n6[11:7] ;n7_reg1[11:7] <= n7[11:7] ;s00_lsbreg1[7:0] <= s00_lsb[7:0] ;// Preserve all lsb sum. s00_lsbreg1[7] is the registered carry from lsb addition.s01_lsbreg1[7:0] <= s01_lsb[7:0] ;s02_lsbreg1[7:0] <= s02_lsb[7:0] ;s03_lsbreg1[7:0] <= s03_lsb[7:0] ;end// Sign extended & msb added with carry.assign s00_msb[5:0] = {n0_reg1[11], n0_reg1[11:7]}+{n1_reg1[11], n1_reg1[11:7]}+s00_lsbreg1[7];//s00_msb[6] is ignored.assign s01_msb[5:0] = {n2_reg1[11], n2_reg1[11:7]}+{n3_reg1[11], n3_reg1[11:7]}+s01_lsbreg1[7];//10.3 Signed Adder Design 387assign s02_msb[5:0] = {n4_reg1[11], n4_reg1[11:7]}+{n5_reg1[11], n5_reg1[11:7]}+s02_lsbreg1[7];assign s03_msb[5:0] = {n6_reg1[11], n6_reg1[11:7]}+{n7_reg1[11], n7_reg1[11:7]}+s03_lsbreg1[7];always @ (posedge clk)// Pipeline 2: clk (2). Register msb to continue addition of msb.begins00_msbreg2[5:0] <= s00_msb[5:0] ; // Preserve all msb sum.s01_msbreg2[5:0] <= s01_msb[5:0] ;s02_msbreg2[5:0] <= s02_msb[5:0] ;s03_msbreg2[5:0] <= s03_msb[5:0] ;s00_lsbreg2[6:0] <= s00_lsbreg1[6:0] ; // Preserve all lsb sum.s01_lsbreg2[6:0] <= s01_lsbreg1[6:0] ;s02_lsbreg2[6:0] <= s02_lsbreg1[6:0] ;s03_lsbreg2[6:0] <= s03_lsbreg1[6:0] ;end// Second Stage Additionassign s10_lsb[7:0] = s00_lsbreg2[6:0]+s01_lsbreg2[6:0] ;//Add lsb first : s10_lsb[7] is the carry.assign s11_lsb[7:0] = s02_lsbreg2[6:0] +s03_lsbreg2[6:0] ;//s00, s01 lsbs need not be registered//since addition is already carried out here.

always @ (posedge clk)// Pipeline 3: clk (3). Register msb to continue addition of msb.begins10_lsbreg3[7:0] <= s10_lsb[7:0] ; // Preserve all lsb sum.s11_lsbreg3[7:0] <= s11_lsb[7:0] ;s00_msbreg3[5:0] <= s00_msbreg2[5:0];// Preserve all msb sum.s01_msbreg3[5:0] <= s01_msbreg2[5:0] ;s02_msbreg3[5:0] <= s02_msbreg2[5:0] ;s03_msbreg3[5:0] <= s03_msbreg2[5:0] ;endassign s10_msb[6:0] = {s00_msbreg3[5],s00_msbreg3[5:0]}+{s01_msbreg3[5],s01_msbreg3[5:0]}+s10_lsbreg3[7] ;// Add MSB of second stage with sign extension and carry in from LSB.// s10_msb[7] is ignored.assign s11_msb[6:0] = {s02_msbreg3[5], s02_msbreg3[5:0]}+{s03_msbreg3[5], s03_msbreg3[5:0]}+s11_lsbreg3[7] ;always @ (posedge clk)//388 Arithmetic Circuit Designs// Pipeline 4: clk (4). Register msb to continue addition of msb.begins10_lsbreg4[6:0] <= s10_lsbreg3[6:0] ; // Preserve all lsb sum.s11_lsbreg4[6:0] <= s11_lsbreg3[6:0] ;s10_msbreg4[6:0] <= s10_msb[6:0] ; // Preserve all msb sum.s11_msbreg4[6:0] <= s11_msb[6:0] ;end// Third Stage Additionassign s20_lsb[7:0] = s10_lsbreg4[6:0]+ s11_lsbreg4[6:0] ;//Add lsb first : s20_lsb[7] is the carry.always @ (posedge clk)// Pipeline 5: clk (5). Register msb to continue addition of msb.begins10_msbreg5[6:0] <= s10_msbreg4[6:0]; //Preserve all msb sum.s11_msbreg5[6:0] <= s11_msbreg4[6:0] ;s20_lsbreg5cy <= s20_lsb[7]; // Preserve all lsb sum.s20_lsbreg5[6:0] <= s20_lsb[6:0];end// Add third stage MSB results and concatenate// with LSB result to get the final result.assign sum[14:0] = {({s10_msbreg5[6], s10_msbreg5[6:0]}+

{s11_msbreg5[6], s11_msbreg5[6:0]}+s20_lsbreg5cy), s20_lsbreg5[6:0]};endmodule

//TEST BENCH FOR PARALLEL ADDER`define clkperiodby2 10 // Frequency of operation is 50 MHz.

module adder12s_test(sum);output [14:0] sum;reg clk ;reg [11:0] n0 ;reg [11:0] n1 ;reg [11:0] n2 ;reg [11:0] n3 ;reg [11:0] n4 ;reg [11:0] n5 ;reg [11:0] n6 ;reg [11:0] n7 ;adder12s u1( .clk(clk),.n0(n0),.n1(n1),.n2(n2),.n3(n3),.n4(n4),.n5(n5),.n6(n6),.n7(n7),.sum(sum));initialbeginclk = 1'b0 ; // Initialize the clock.n0 = 12'h0 ; // Apply the first set of inputs.n1 = 12'h0 ;n2 = 12'h0 ;n3 = 12'h0 ;n4 = 12'h0 ;n5 = 12'h0 ;n6 = 12'h0 ;n7 = 12'h0 ;#17 n0 = 12'hfff ; // Apply the second set of inputs.n1 = 12'hfff ;n2 = 12'hfff ;n3 = 12'hfff ;n4 = 12'hfff ;n5 = 12'hfff ;n6 = 12'hfff ;//390 Arithmetic Circuit Designsn7 = 12'hfff ;

#20 n0 = 12'h7ff ; // Apply the third set of inputs.n1 = 12'h7ff ;n2 = 12'h7ff ;n3 = 12'h7ff ;n4 = 12'h7ff ;n5 = 12'h7ff ;n6 = 12'h7ff ;n7 = 12'h7ff ;#20 n0 = 12'h800 ; // Apply the fourth set of inputs.n1 = 12'h800 ;n2 = 12'h800 ;n3 = 12'h800 ;n4 = 12'h800 ;n5 = 12'h800 ;n6 = 12'h800 ;n7 = 12'h800 ;#20 n0 = 12'h001 ; // Apply the fifth set of inputs.n1 = 12'h001 ;n2 = 12'h001 ;n3 = 12'h001 ;n4 = 12'h001 ;n5 = 12'h001 ;n6 = 12'h001 ;n7 = 12'h001 ;#20 n0 = 12'h001 ; // Apply the sixth set of inputs.n1 = 12'hfff ;n2 = 12'h001 ;n3 = 12'hfff ;n4 = 12'h001 ;n5 = 12'hfff ;n6 = 12'h001 ;n7 = 12'hfff ;#20 n0 = 12'h7ff ; // Apply the seventh set of inputs.n1 = 12'h7ff ;n2 = 12'h7ff ;n3 = 12'h7ff ;n4 = 12'h801 ;n5 = 12'h801 ;n6 = 12'h801 ;n7 = 12'h801 ;

#20 n0 = 12'haaa ; // Apply the eighth set of inputs.n1 = 12'h555 ;n2 = 12'haaa ;n3 = 12'h555 ;n4 = 12'haaa ;//10.3 Signed Adder Design 391n5 = 12'h555 ;n6 = 12'haaa ;n7 = 12'h555 ;#20 n0 = 12'h0 ; // Apply one more set of inputs.n1 = 12'h0 ;n2 = 12'h0 ;n3 = 12'h0 ;n4 = 12'h0 ;n5 = 12'h0 ;n6 = 12'h0 ;n7 = 12'h0 ;#400 // Wait for some time before stopping.$stop ;endalways#`clkperiodby2 clk <= ~clk ; // Toggle the clock.endmodule

OUTPUT WAVEFORM

RESULT:

PIPELINED SERIAL ADDER

Expt No:14 Date:

AIM:

To design and simulate the pipelined serial adder using verilog HDL .

APPARATUS REQUIRED:

Xilinx ISE 10.1. BLOCK DIAGRAM:

PIN DETAILS:

S.NO PIN DETAILS1. n0-n7 Eight input data from n0 to n7, and the width is

12-bits.2. Sum[14:0] Accumulated result available in this register.3. Sum_valid This signal will be enable when the output is

valid.4. enable This input signal will enable the adder when

enable=1.5. clk Clock input signal.

PROGRAM:

// PIPELINED SERIAL ADDER.

module serial_adder12s ( clk,enable,n,sum,sum_valid,result) ; input clk ; input enable ; input [11:0] n ; output [14:0] sum ; output sum_valid ; output [14:0] result ; // Prolong the result till it is overwritten by a new result. wire [14:0] sum_next ; // Declare nets in the design. wire [2:0] cnt_next ; wire sum_val ; reg [14:0] sum; reg [2:0] cnt ; reg sum_valid ; reg [14:0] result ; assign sum_next [14:0] = enable ? ({{3{n[11]}}, n[11:0]} + sum[14:0]) : 0 ;

// Sign extend & accumulate. assign cnt_next [2:0] = enable ? (cnt + 1) : 0 ;

// Pre-advance the counter. assign sum_val = (cnt == 7) ? 1 : 0 ; // Pre-determine the validity of the sum. always @ (posedge clk) // Pipeline ? Register the sum. begin sum [14:0] <= sum_next [14:0] ; // Register the sum. cnt [2:0] <= cnt_next [2:0] ; // Advance the count. sum_valid <= sum_val ; // Register the signal. end // Prolong the result till it is overwritten by the new result. always @ (posedge clk) result[14:0] <= sum_valid ? sum[14:0] : result[14:0] ; // Register the sum.endmodule

// TEST BENCH FOR PIPELINED SERIAL ADDER:

`define clkperiodby2 10

`include "serial_adder12s.v"module serial_adder12s_test ( );//sum,sum_valid,result);wire [14:0] sum;wire sum_valid ;wire [14:0] result;reg clk ;reg enable ;reg [11:0] n ;serial_adder12s u1( .clk(clk),.enable(enable),.n(n),.sum(sum),.sum_valid(sum_valid),.result(result));initialbeginclk = 0 ;// Apply first set of inputs sequentially every 20 ns.n = 12'h0 ; // n0 @ 0 ns.enable = 0 ;#20 enable = 1 ;#17 n = 12'hfff ; // n1 @ 37 ns.#20 n = 12'h7ff ; // n2 @ 57 ns, etc.#20 n = 12'h800 ;#20 n = 12'h001 ;#20 n = 12'h001 ;#20 n = 12'h7ff ;#20 n = 12'haaa ; // n7 @ 157 ns.#20 n = 12'h0 ;enable = 0 ;// Disable before applying the next set of inputs// so that the accumulated ?sum? is cleared.//378 Arithmetic Circuit Designs#20 enable = 1 ; // Apply the next set of inputs.n = 100 ; // n0#20 n = 200 ;#20 n = 300 ;#20 n = 400 ;#20 n = 500 ;

#20 n = 100 ;#20 n = 200 ;#20 n = 247 ; // n7#20 enable = 0 ;#100 $stop ;endalways#`clkperiodby2 clk <= ~clk ; // Run the clock at 50 MHz.endmodule

OUTPUT WAVEFORM:

RESULT:

TRAFFIC LIGHT CONTROLLERExpt No:15 Date:

AIM:

To design and synthesis the traffic light controller using verilog HDL .

APPARATUS REQUIRED:

Xilinx ISE 10.1. PROGRAM:

module traffic(clk,en,south,east,north,west,chip4_en);input clk,en;output [6:0]south;output [6:0]north;output [6:0]east;output [6:0]west;output chip4_en;reg [6:0]south;reg [6:0]north;reg [6:0]east;reg [6:0]west;reg chip4_en;reg term_count;reg start_count;reg[27:0]count;reg[3:0]nstate;parameter [3:0]idle=4'b0000,step1_amber=4'b0001,step1=4'b0010,step2_amber=4'b0011,step2=4'b0100,step3_amber=4'b0101,step3=4'b0110,step4_amber=4'b0111,step4=4'b1000;

always @(posedge clk or posedge en)beginif(en)begincount=0;term_count=1'b0;endelsebeginterm_count=1'b0;if(start_count)begincount=count+1;if(count==25000000)beginterm_count=1'b1;count=0;endendendendalways@(posedge clk)beginif(en)beginsouth=7'b1000000;north=7'b1000000;east=7'b1000000;west=7'b1000000;nstate=idle;endelsechip4_en=0;case(nstate)idle:beginsouth=7'b1000011;east=7'b1000011;north=7'b1000011;west=7'b1000011;

nstate=idle;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step1_amber;endendstep1_amber:beginsouth=7'b0100000;north=7'b1000000;east=7'b1000000;west=7'b1000000;nstate=step1_amber;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step1;endendstep1:beginsouth=7'b0011100;north=7'b1000000;east=7'b1000000;west=7'b1000000;nstate=step1;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step2_amber;endendstep2_amber:beginsouth=7'b1000000;north=7'b1000000;

east=7'b1000000;west=7'b0100000;nstate=step2_amber;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step2;endendstep2:beginsouth=7'b1000000;north=7'b1000000;east=7'b1000000;west=7'b0011100;nstate=step2;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step3_amber;endendstep3_amber:beginsouth=7'b1000000;north=7'b1000000;east=7'b0100000;west=7'b1000000;nstate=step3_amber;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step3;endendstep3:begin

south=7'b1000000;north=7'b1000000;east=7'b0011100;west=7'b1000000;nstate=step3;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step4_amber;endendstep4_amber:beginsouth=7'b1000000;north=7'b0100000;east=7'b1000000;west=7'b1000000;nstate=step4_amber;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step4;endendstep4:beginsouth=7'b1000000;north=7'b0011100;east=7'b1000000;west=7'b1000000;nstate=step4;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=idle;endend

endcaseendendmodulemodule traffic(clk,en,south,east,north,west,chip4_en);input clk,en;output [6:0]south;output [6:0]north;output [6:0]east;output [6:0]west;output chip4_en;reg [6:0]south;reg [6:0]north;reg [6:0]east;reg [6:0]west;reg chip4_en;reg term_count;reg start_count;reg[27:0]count;reg[3:0]nstate;parameter [3:0]idle=4'b0000,step1_amber=4'b0001,step1=4'b0010,step2_amber=4'b0011,step2=4'b0100,step3_amber=4'b0101,step3=4'b0110,step4_amber=4'b0111,step4=4'b1000;always @(posedge clk or posedge en)beginif(en)begincount=0;term_count=1'b0;endelsebeginterm_count=1'b0;if(start_count)begincount=count+1;

if(count==25000000)beginterm_count=1'b1;count=0;endendendendalways@(posedge clk)beginif(en)beginsouth=7'b1000000;north=7'b1000000;east=7'b1000000;west=7'b1000000;nstate=idle;endelsechip4_en=0;case(nstate)idle:beginsouth=7'b1000011;east=7'b1000011;north=7'b1000011;west=7'b1000011;nstate=idle;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step1_amber;endendstep1_amber:beginsouth=7'b0100000;north=7'b1000000;east=7'b1000000;

west=7'b1000000;nstate=step1_amber;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step1;endendstep1:beginsouth=7'b0011100;north=7'b1000000;east=7'b1000000;west=7'b1000000;nstate=step1;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step2_amber;endendstep2_amber:beginsouth=7'b1000000;north=7'b1000000;east=7'b1000000;west=7'b0100000;nstate=step2_amber;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step2;endendstep2:beginsouth=7'b1000000;

north=7'b1000000;east=7'b1000000;west=7'b0011100;nstate=step2;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step3_amber;endendstep3_amber:beginsouth=7'b1000000;north=7'b1000000;east=7'b0100000;west=7'b1000000;nstate=step3_amber;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step3;endendstep3:beginsouth=7'b1000000;north=7'b1000000;east=7'b0011100;west=7'b1000000;nstate=step3;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step4_amber;endendstep4_amber:

beginsouth=7'b1000000;north=7'b0100000;east=7'b1000000;west=7'b1000000;nstate=step4_amber;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=step4;endendstep4:beginsouth=7'b1000000;north=7'b0011100;east=7'b1000000;west=7'b1000000;nstate=step4;start_count=1'b1;if(term_count)beginstart_count=1'b0;nstate=idle;endendendcaseendendmodule

PIN ASSIGNMENT DETAILS:

WEST SOUTH EAST NORTHRED M3 N7 E4 F3AMBER R5 L5 G5 M10LEFT L4 R6 F4 B1STRAIGHT C2 N3 H4 P9RIGHT G3 T8 H3 M7PEDESTRAIN C1 M4 E3 K4PEDESTRAIN N8 J3 G4 T5Enable K13Chip_en J4Clk T9

RESULT: