Research ArticleFirst Steps in Creating Online Testable ReversibleSequential Circuits

Mozammel H A Khan1 and Jacqueline E Rice 2

1Department of Computer Science and Engineering East West University Aftabnagar Dhaka 1212 Bangladesh2Department of Mathematics and Computer Science University of Lethbridge Lethbridge AB Canada T1K 3M4

Correspondence should be addressed to Jacqueline E Rice jriceulethca

Received 2 May 2017 Accepted 6 December 2017 Published 14 January 2018

Academic Editor Marcelo Lubaszewski

Copyright copy 2018 Mozammel H A Khan and Jacqueline E Rice This is an open access article distributed under the CreativeCommons Attribution License which permits unrestricted use distribution and reproduction in any medium provided theoriginal work is properly cited

Synthesis of reversible sequential circuits is a very new research area It has been shown that such circuits can be implementedusing quantum dot cellular automata Other work has used traditional designs for sequential circuits and replaced the flip-flopsand the gates with their reversible counterparts Our earlier work uses a direct feedback method without any flip-flops improvingupon the replacement technique in both quantum cost and ancilla inputs We present here a further improved version of the directfeedbackmethod Design examples show that the proposedmethod produces better results than our earliermethod in terms of bothquantum cost and ancilla inputs We also propose the first technique for online testing of single line faults in sequential reversiblecircuits

1 Introduction

Moorersquos law [1] predicted a continuous rise in the numberof transistors per chip due to the continuous reduction infeature size The popular thought is that Moorersquos law willno longer hold true in about a decade when the feature sizewill approach the atomic level DeBenedictis [2] showed thatin CMOS technology feature size is no longer the primarychallenge rather energy dissipation is the new limiting factorCurrent CMOS circuits implement Boolean logic networkswhere the main contributor to heat generation is the energyin the 0 and 1 signals stored on wires Each time a signalchanges from one state to another and back again1198621198812 joulesof energy are turned into heat where 119862 is the capacitancebetween the wire and the ground and 119881 is the powersupply voltage The most common number cited is 1198621198812 ge100119896119879 where 119896 is Boltzmannrsquos constant and 119879 is the ambienttemperature in kelvin [2] DeBenedictis [2] also stated thatadiabatic and reversible logic essentially recycle 1198621198812 joulesof signal energy many times before dissipating as heatConsequently the energy drawn from the power supply couldbe reduced by as much as 100 times However signal energyrecycling cannot take place in traditional Boolean networks

Therefore reversible logic may be the next promise for CMOStechnology

In a theoretical study Landauer [3] stated that irreversiblelogic operations dissipate 1198961198791198971198992 of heat energy when abit of information is lost where again 119896 is Boltzmannrsquosconstant and 119879 is the operating temperature in kelvin Inanother theoretical study Bennett [4] showed that froma thermodynamic point of view if a circuit is both logi-cally and physically reversible then 1198961198791198971198992 heat will not bedissipated Experiments have shown that dissipation of noheat is not achievable however it has been experimentallydemonstrated that reversible logic dissipates less heat than thethermodynamic limit of 1198961198791198971198992 in physically irreversible low-power CMOS logic [5] and physically reversible supercon-ductor flux logic (SFL) [6]Thus reversible logic is a favorablechoice for low-power emerging computing technologies

Reversible logic has become realizable in many emergingcomputing technologies such as superconductor flux logic(SFL) technology [6 7] optical technology [8 9] quantumdot cellular automata technology [10 11] andnanotechnology[12] In addition quantum circuits are inherently reversible[13] This is another reason why reversible logic has become

HindawiVLSI DesignVolume 2018 Article ID 6153274 13 pageshttpsdoiorg10115520186153274

2 VLSI Design

A P = A

(a)

A AP =B A oplus BQ =

(b)

A P = ABC

Q = BR = AB oplus C

(c)

A AP =BC

Q =R =

AB oplus ACAB oplus AC

(d)

Figure 1 Commonly used reversible gates (a) NOT gate (b) CNOT or Feynman gate (c) Toffoli gate and (d) controlled swap or Fredkingate

a promising choice for low-power emerging computingtechnologies

Reversible logic synthesis attempts have mostly focusedon reversible combinational logic synthesis Some of themost important but nonexhaustive work in this area is [14ndash23] However very few works have investigated reversiblesequential logic synthesisThemajor problembehind this lackof work is the prevailing thought that feedback is not possiblein reversible logic and therefore reversible sequential circuitsare not possible However in 1980 Toffoli [24] argued thatif the feedback is provided through a delay element thenthe feedback information will be available as the input tothe reversible combinational circuit in the next clock cycleand thus a reversible sequential circuit is possible MoreoverThapliyal et al [25] showed that reversible sequential circuitscan be implemented using quantum dot cellular automata(QCA) technology by providing appropriate feedback timingby managing the clock of the QCA wire providing thefeedback

This paper presents a further improvement of our earlierwork in designing a sequential circuit using direct feedbackinstead of flip-flops [26] In addition to our knowledge noother work has offered any technique for online testing ofsequential circuits Thus we also propose the first method oftesting for single line faults in sequential circuits

The rest of the paper is organized as follows In Section 2we discuss background for our proposed design method andrelated topicsWediscuss relatedwork ondesign of sequentialcircuits and online testingmethods for combinational circuitsin Section 3 In Section 4 we present our proposed methodof designing sequential circuits We show design examples inSection 5 In Section 6 we introduce our proposedmethod ofonline testing for single line faults in sequential circuits Wealso present results for several benchmark circuits Finally inSection 8 we conclude the paper

2 Background

21 Reversible Logic A reversible function is a bijectivemapping 119865 0 1119899 997891rarr 0 1119899 where 119899 is the number ofinput variables A reversible gate (or a circuit) implementsa reversible function that is it maps the input combinationto the output combination in a bijective manner Thus areversible gate (or a circuit) has the same number of inputsand outputs In addition every input combination producesa unique output combination in a reversible circuit andtherefore for every output combination the correspondinginput combination can be uniquely determined

A reversible circuit is constructed using reversible gatesThe commonly used reversible gates are shown in Figure 1

Figure 1(a) shows the symbol of a NOT gate It complementsthe input at the output that is 119875 = 1198601015840 Figure 1(b) showsthe symbol of a controlled-NOT (CNOT) or Feynman gateThe input 119860 is called the control input and its value is passedunchanged to the output that is 119875 = 119860 The input 119861 is calledthe target input The target output has the value 119876 = 119860 oplus119861 Figure 1(c) shows the symbol of a three-input Toffoli gate(sometimes referred to as a controlled-controlled-NOT gateor CCNOT gate) The inputs 119860 and 119861 are called the controlinputs and their values are passed unchanged to the outputsthat is119875 = 119860 and119876 = 119861The input119862 is called the target inputand the target output has the value 119877 = 119860119861 oplus 119862 Toffoli gatesmay have more than three inputs in which case they may bereferred to as multiple-controlled Toffoli gates In an 119899-inputToffoli gate the first (119899minus1) inputs (say 1199091 1199092 119909119899minus1) are thecontrol inputs and the last input (say 119909119899) is the target inputThe value of the target output is 11990911199092 sdot sdot sdot 119909119899minus1oplus119909119899 Figure 1(d)shows the symbol of a controlled swap gate or Fredkin gateInput 119860 is the control input and inputs 119861 and 119862 are targetsWhen the control input value is 119860 = 0 then the target inputs119861 and 119862 are passed unchanged to the outputs that is 119876 = 119861and 119877 = 119862 When the control input value is 119860 = 1 then thetarget inputs are swapped at the outputs that is 119876 = 119862 and119877 = 119861The outputs119876 and119877 can be expressed as119876 = 1198601015840119861oplus119860119862and119877 = 119860119861oplus1198601015840119862When119860 = 0 then119876 = 01015840 sdot119861oplus0sdot119862 = 119861 and119877 = 0 sdot 119861oplus01015840 sdot 119862 = 119862 When119860 = 1 then119876 = 11015840 sdot 119861 oplus 1 sdot119862 = 119862and 119877 = 1 sdot 119861 oplus 11015840 sdot 119862 = 119861

Quantum cost and the number of ancilla inputs are widelyused as metrics for comparing reversible circuits Quantumcost refers to the number of primitive quantum gates requiredto realize the circuit while ancilla inputs are the constant-initialized working inputs in addition to the function inputsthat are required for the functionality of the circuit

NOT andCNOTgates are technology realizable primitivegates and their quantum costs are assumed to be one Toffoliand controlled swap gates are macro-level gates and must berealized through a combination of primitive quantum gatesThe three-input Toffoli gate and the controlled swap gate canbe realized using five primitive quantum gates [27 28] andthus their quantum cost is five each

Realization of multiple-controlled Toffoli gates fromprimitive quantum gates is presented in [29] where quantumcosts for up to 16-input Toffoli gates are reported Thequantum costs for 4-input 5-input and 6-input Toffoli gatesare 14 20 and 32 respectively

In [30] extended Toffoli gates (ETG) are proposedwhich have two target outputs ETGs are very useful inonline testing of reversible combinational circuits In Fig-ure 2(a) the extended Feynman gate (EFG) and its logiclevel implementation are shown The quantum cost of the

VLSI Design 3

x xy yxoplusz zxoplus

x xy yxoplusz zxoplus

(a)

x xw w

y ywxoplusz zwxoplus

x xw w

y ywxoplusz zwxoplus

(b)

Figure 2 The symbol and logic level implementations for (a) the extended Feynman gate and (b) a 2-control extended Toffoli gate

A

B

C

D

0

A

B

C

D

F = A oplus BD oplus ACD oplus BCD

Figure 3 Reversible circuit implementing (1)

EFG is 2 In Figure 2(b) a 2-control ETG and its logic levelimplementation are shownThe quantum cost of an ETG is 2plus the quantum cost of the corresponding Toffoli gate Thequantum cost of the ETG in Figure 2(b) is 5 + 2 = 7

22 Reversible Logic Synthesis Using ESOP Expressions Anexclusive-OR sum of products (ESOP) expression is similarto a conventional sum of products (SOP) expression exceptthat product terms are combined with exclusive-OR (EXOR)operators rather than OR operators [31] A common tech-nique in reversible logic synthesis is to express the logicfunction as an ESOP expression and then realize the ESOPexpression as a cascade of NOT CNOT and Toffoli gates [32]An example ESOP expression is given in (1) and its reversiblerealization as a cascade of NOT CNOT and Toffoli gates isshown in Figure 3

119865 (119860 119861 119862119863) = 119860 oplus 119861119863 oplus 119860119862119863 oplus 119861119862119863 (1)

23 Sequential Circuits The classical model of a sequentialcircuit is shown in Figure 4 A sequential circuit has amemory whose content during the present clock cycle iscalled the present state The combinational circuit producesthe output as a function of the present state and the inputThe combinational circuit also produces the next state as afunction of the present state and the input this computednext state becomes the present state during the next clockcycle The behavior of a sequential circuit is described usinga state transition diagram In describing a sequential circuitthe present state is represented by 119876 and the next state isrepresented by 119876+ An example sequential circuit is shownin the state transition diagram in Figure 4 It has 1-bit input(119909) 1-bit output (119911) and 2-bit state (11987611198760) The reset state is00

24 Testing of Reversible Circuits Testing is very importantto ensure quality availability and reliability of a circuitThereare two approaches to circuit testing offline testing andonlinetesting [33] In offline testing a circuit is tested when it is not

in normal operation In online testing however the circuitmust be able to continue normal operations while testing iscarried out For online testing additional circuitry is generallyadded to the original circuit to determine whether the circuitis faulty or not There are three fault models line faults (orbit faults) [33] missing control faults which is one instanceof crosspoint faults [34] andmissing gate faults [35] In a linefault the logic value of a line is flipped and produces faultyoutput In a missing control fault the control point of a gateeither is not working or disappears from the gate resulting inan incorrect value for the target output In amissing gate faultthe entire gate does not work or the gate disappears from thecircuit causing faulty output

3 Related Work

In this section we discuss related work on reversible sequen-tial circuit design and on online testing of reversible combi-national circuits

31 Related Work on Reversible Sequential Circuit DesignThere are many attempts at designing reversible latches flip-flops and sequential circuits Some important but nonex-haustive work on reversible sequential logic design includes[25 26 36ndash42] References [36ndash39] present reversible designsfor latches and flip-flops using reversible gates and sug-gest that sequential circuits be synthesized by replacingthe latches flip-flops and gates of the combinational partof the traditional irreversible designs with their reversiblecounterparts Following this replacement approach the workin [40] presents a design for a four-bit falling-edge-triggereduniversal register and the work in [41] presents a designfor a four-bit level-triggered up counter with asynchronousparallel load The work in [25] again uses the replacementtechnique and demonstrates that reversible circuits can beimplemented using QCA technology with offline testing ofthe QCA-based sequential circuitThe work in [42] offers thefirst attempt to synthesize a sequential circuit using directfeedback of the state output and without using any flip-flopsReference [42] also presents a design for a level-triggeredup counter using positive polarity Reed-Muller expressionsfor representing the next states The up counter design ismore efficient than the replacement design in [41] in termsof both quantum cost and garbage outputs (outputs that arenot used for the intended circuit realization) The next stepto this work is presented in [26] which details the directdesign of arbitrary sequential circuits using pseudo-Reed-Muller expressions for representing the next statesThis workalso introduces modifications making the circuit falling-edgetriggered and asynchronous loadable The updown counterin [26] is better than that in [41] in terms of both quantum

4 VLSI Design

Combinational logic

Memory

Input Output

Nex

t sta

te

Pres

ent s

tate

Clock(a)

00

10

0111

1110

00

110110

00

01

Reset

(b)

Figure 4 (a) Model of a sequential circuit (b) State transition diagram of an example sequential circuit

cost and garbage outputs and the universal register in [26]improves upon the design in [40] again for both quantumcostand garbage output

A further improvement of the work in [26] is presented in[43] In [43] a new technique for representing the next statesusing exclusive-OR sum-of-product (ESOP) expressions ispresented Using this technique designs for a four-bit falling-edge triggered updown counter with asynchronous loadingand a four-bit falling-edge triggered universal register arepresented Both designs in [43] offer improvements overthose from [26] in terms of both quantum cost and ancillainput This work is an extended version of [43]

32 Related Work on Testing of Reversible CombinationalCircuits Several works offer techniques for online testingof reversible combinational circuits Some propose newtestable gates which are then used to construct online testablereversible circuits In [17] three new reversible gates areproposed two of which are used to design an online testableblock and the other is used to create a checker circuit Thechecker circuit compares the two parity bits produced by theonline testable blocks in order to test a single bit fault In [23]an improved approach to single bit fault testing is proposedthat does not require a checker circuit

The most generalized approaches offer online testing ofreversible circuits synthesized using NOT CNOT and Toffoligates In [44] all of the Toffoli gates are replaced by extendedToffoli gates and two sets of CNOT gates and one additionalparity line are added to the original circuit to achieve onlinetestability for single line faults In [45] a DFT- (design fortestability-) based offline approach is proposed for detectingsingle missing gate faults In [46] an online fault detectionapproach is proposed for detecting single missing gate faultsIn [47] each of the Toffoli gates is accompanied by a duplicateToffoli gate of the same size with the same control lines butthe target is placed on an additional parity line to make theToffoli gate a testable Toffoli block Two sets of CNOT gatesare also used for which the targets are the parity line Thisapproach detects all three types of faults

To the best of our knowledge no work has been reportedin the literature on offline or online testing of reversiblesequential circuits

4 Synthesis of Sequential Reversible Circuits

In this section we present our proposedmethod for synthesisof sequential reversible circuits

41 Representing the Next State Let 119876 and 119876+ be the presentstate and the next state of a sequential circuit respectively119876+can be expressed as a function of 119876 and 119876+ as follows

119876+ = 119876 oplus 119876 oplus 119876+ = 119876 oplus 119876lowast (2)

where

119876lowast = 119876 oplus 119876+ (3)

We call 119876lowast the modified next state In our proposedtechnique themodifiednext state is determinedusing (3) andis expressed as a minimized ESOP expression of a functionof the inputs and the present state The next state is thenexpressed using (2)

42 Synthesis Model Our model for the reversible synthesisof sequential circuits is shown in Figure 5 First the modifiednext state 119876lowast is generated as a function of the inputs andpresent state in the Modified Next State Logic section Thenext state is generated using (2) in the Next State Logicsection The generated next state is loaded to the stateoutput as the present state at the falling-edge of the clock inthe Falling-Edge Trigger section The asynchronous reset orload is carried out in the Asynchronous Load section Thefeedback of the present state is generated in the Feedbacksection and the present state is fed back to the Modified NextState Logic section Finally in the Output Logic section theoutput is generated as a function of the input and the presentstate The following examples explain the use of this model

5 Design Examples

In this section we use three examples to illustrate the designmodel discussed in Section 42

51 Example 1 Sequential Circuit from Figure 4(b) The truthtable representing the next states (1198761+1198760+) the modifiednext states (1198761lowast1198760lowast) and the output (119911) of the sequentialcircuit in Figure 4(b) is shown in Table 1 The modified nextstates (1198761lowast1198760lowast) and the output (119911) are minimized as ESOPexpressions as follows

1198761lowast = 11987601015840 oplus 11990911987611198760 (4)

1198760lowast = 1 oplus 119909101584011987611015840 oplus 119876110158401198760 (5)

119911 = 1198760 oplus 1199091015840 (6)

VLSI Design 5

Modifiednextstatelogic

InputsNextstatelogicQ

Falling-edge

triggering

C

QReset or

asynchronousloading

Q

0D

RL

Feedback

C

0

Q

Q

Q

Outputlogic

0D

Q

RL

CInputs

01

Q

Inputs Inputs

Outputs

01Qlowast Q+ Q+

Q+Q+

Figure 5 Model of reversible synthesis of sequential circuit

R R

C

x

1

1

Q1

Q0

0

0

Q0

Q1 Q1

Q0

Modified next state logicNext state

logicFalling-edge

triggerAsynchronous

reset

0

0

Feedback

Q1

Q0

Outputlogic

C

z

Q0lowast

Q1lowast

Q0+

Q1+

Figure 6 Reversible realization of the sequential circuit described by Figure 4(b)

Table 1 Truth table representing the next states the modified nextstates and the output of the sequential circuit from Figure 4(b)

11990911987611198760 1198761+1198760+ 1198761lowast1198760lowast 119911

000 10 10 1001 00 01 0010 01 11 1011 10 01 0100 11 11 0101 01 00 1110 01 11 0111 00 11 1

Equations (4) (5) and (6) are then used to implement thestatemachine fromFigure 4(b) resulting in the circuit shownin Figure 6 Each section of this circuit is explained below

(1) Modified Next State Logic The modified next states 1198761lowastand1198760lowast (see (4) and (5)) are realized as functions of the input119909 and the fed-back present states 1198761 and 1198760 as a cascadeof NOT CNOT and Toffoli gates The quantum cost of thissection is 28 and 2 ancilla inputs are required

(2) Next State LogicThe next states are realized as1198761+ = 1198761oplus1198761lowast and 1198760+ = 1198760 oplus 1198760lowast using the generated modified nextstates 1198761lowast and 1198760lowast and fed-back present states 1198761 and 1198760This requires two CNOT gates and thus the quantum costof this section is exactly equal to the number of bits in thestate of the sequential circuit since for each bit a CNOT gateis required and the quantum cost of the CNOT gate is 1 Noancilla inputs are required

(3) Falling-Edge Trigger The falling-edge triggering isachieved using two controlled swap gates controlled by theclock 119862 When the clock 119862 = 1 and reset 119877 = 0 the fed-backstates are passed to the state outputs maintaining the stateoutputs unchanged When the clock is set to 119862 = 0 and 119877 = 0is maintained then the generated next states are transmittedto the state outputs Just after the next states arrive at the stateoutput and the feedback of the present states arrives at theFalling-Edge Trigger section the clock must be set to 119862 = 1in order tomaintain the new present state at the outputThusthe changes of the present states occur at the falling-edge ofthe clock 119862 and the duration of the period of 119862 = 0 has to bevery carefully determined to avoidmalfunction of the circuitThe quantum cost of this section is 5 times the number of bitsrequired for the state of the sequential circuit since for eachbit a controlled swap gate is required and the quantum cost of

6 VLSI Design

the controlled swap gate is 5 Thus the quantum cost of thissection is 10 and no ancilla inputs are required

(4) Reset The reset is achieved using two controlled swapgates controlled by the reset input 119877 In the sequentialcircuit represented by Figure 4 the reset state is 00 Duringsynchronous operation the clock must be set to 119862 = 1 andthe reset must be cleared to 119877 = 0 to maintain the presentstate unchanged For the falling-edge triggering action theclock and the reset must both be cleared to 119862119877 = 00 Thereset action takes place asynchronously when the clock andthe reset are both set to 119862119877 = 11 In this case the constantinputs 00 are transmitted to the state outputs At this pointthe reset must be set to 119877 = 0 in order to maintain the stateoutputs unchanged Again the duration of the reset value119877 = 1 must be carefully determined to avoid malfunctionof the sequential circuit The quantum cost of this section isalso 5 times the number of bits in the state of the sequentialcircuit since for each bit a controlled swap gate is requiredand the quantum cost of the controlled swap gate is 5 Thissection requires ancilla inputs exactly equal to the number ofbits in the state Thus the quantum cost of this section is 10and 2 ancilla inputs are required

(5) Feedback The feedback of the present state is generatedusing two CNOT gates used as copying gates and is achievedby setting the target input to be 0 The quantum cost of thissection is exactly equal to the number of the bits in the stateof the sequential circuit since one CNOT gate is required foreach bit of the state and the quantum cost of the CNOT gateis 1 This section requires ancilla inputs exactly equal to thenumber of bits in the state of the sequential circuit since foreach bit of the state one constant-initialized input is requiredThe quantum cost of this section is 2 and 2 ancilla inputs arerequired

(6) Output Logic The output 119911 is realized as a function of theinput 119909 and the present state 1198760 using (6)

The total quantum cost of the circuit in Figure 6 is 53and 6 ancilla inputs are required These values are comparedwith those of the replacement design approach in [26] andthe direct design in [26] in Table 2 The improvement overprevious designs is calculated using the formula

Improvement = Previous minus PresentPrevious

times 100 (7)

From Table 2 we see that our new present design techniquesaves significantly on quantum cost and ancilla inputs ascompared to both previous replacement design techniqueand the direct design technique presented in [26]

52 Example 2 4-Bit UpDown Counter In this sectionwe illustrate the application of our technique to the designof a four-bit falling-edge trigged updown counter withasynchronous load The truth table representing the nextstates and the modified next states of the counter is shownin Table 3Themodified next states of the four-bit up counterfrom Table 3 are minimized as ESOP expressions as follows

1198763lowast = 119876211987611198760 (8)

Table 2 Comparison of reversible realization of the sequentialcircuit in Figure 6 with replacement design method and directdesign method in [26]

Quantum cost Ancilla inputReplacement design [26] 96 18Direct design [26] 88 9Present design 53 6 improvement overreplacement design [26] 4479 6667

improvement overdirect design [26] 3977 3333

Table 3 Truth table representing the next states and the modifiednext states of a four-bit up counter [43]

Present state Next state Modified next state1198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

0000 0001 00010001 0010 00110010 0011 00010011 0100 01110100 0101 00010101 0110 00110110 0111 00010111 1000 11111000 1001 00011001 1010 00111010 1011 00011011 1100 01111100 1101 00011101 1110 00111110 1111 00011111 0000 1111

1198762lowast = 11987611198760 (9)

1198761lowast = 1198760 (10)

1198760lowast = 1 (11)

Similarly the modified next states of the four-bit downcounter are minimized as ESOP expressions as follows

1198763lowast = 119876210158401198761101584011987601015840 (12)

1198762lowast = 1198761101584011987601015840 (13)

1198761lowast = 11987601015840 (14)

1198760lowast = 1 (15)

The complete counter is implemented using the ESOP expres-sions (8) to (15) and the resulting reversible circuit is shownin Figure 7 where 119862 is the clock input the input 119871 performsthe asynchronous load with 119871 = 0 for normal operation and119871 = 1 for asynchronous load and the input119872 determines thecount direction with119872 = 0 for up and119872 = 1 for down The

VLSI Design 7

Q0

Q1

Q2

Q3

0

0

0

0

1

0

C C

0

0

Q3

Q2

Q1

Q0

Q0lowast

Q1lowast

Q2lowast

Q3lowast Q3

+Q2

+Q1

+Q0

M

Q2

Q1

Q0

Q3

M

L LModified next state logic

Nextstatelogic

Falling-edgetrigger Asynchronous load Feedback

D0

D1

D2

D3

+

Figure 7 Reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load [43]

design is similar to that of the previous example (Example 1)The operation of the circuit is discussed below

(1) C = 1 and L = 1 Asynchronous Load The data inputs 11986331198632 1198631 and 1198630 are loaded to the present state outputs 11987631198762 1198761 and 1198760 (respectively) through the controlled swapgates that make up the Asynchronous Load section of thecircuit After loading the input data we set 119871 = 0 to maintainthe present state output

(2) M = 0 Modified Next State Generation for Up CountThe six 119872-controlled CNOT gates of the Modified NextState Logic section will not modify the logic values of theirtargets and the fed-back state values 1198763 1198762 1198761 and 1198760remain unchanged These fed-back state values are used inthe Modified Next State Logic section to generate modifiednext states 1198763lowast 1198762lowast 1198761lowast and 1198760lowast (see (8) to (11))

(3) M = 1 Modified Next State Generation for Down CountThe first three CNOT gates controlled by 119872 complementthe fed-back present states 1198763 1198762 1198761 and 1198760 Thesecomplemented values are used in the Modified Next StateLogic section to generatemodified next states1198763lowast1198762lowast1198761lowastand 1198760lowast (see (12) to (15)) The last three CNOT gates ofthe Modified Next State Logic section restore the fed-backpresent states for use in the Next State Logic section of thecircuit

The circuit in Figure 7 has a quantum cost of 74 andrequires 8 ancilla inputs The complexity of our design is

Table 4 Comparison of reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load with thatin [26] (including data previously presented in [43])

Quantum cost Ancilla inputDesign of [26] 94 8Present design 74 8 improvement overdesign of [26] 2128 0

compared with that in [26] as shown in Table 4 From thetable we see that the present design saves quantum cost withno increase of ancilla inputs

53 Example 3 4-Bit Universal Register In this section weillustrate the synthesis process for a four-bit falling-edgetriggered universal register The truth table representing thenext states and the modified next states is shown in Table 5where 119863119877 is the serial data input The modified next states1198763lowast1198762lowast1198761lowast and1198760lowast are minimized as ESOP expressionsas follows

1198763lowast = 119863119877 oplus 1198763 (16)

1198762lowast = 1198763 oplus 1198762 (17)

1198761lowast = 1198762 oplus 1198761 (18)

1198760lowast = 1198761 oplus 1198760 (19)

8 VLSI Design

Table 5 Truth table representing the next states and the modifiednext states of a four-bit serial-in serial-out right-shift register [43]

Present state Next state Modified next state1198631198771198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

00000 0000 000000001 0000 000100010 0001 001100011 0001 001000100 0010 011000101 0010 011100110 0011 010100111 0011 010001000 0100 110001001 0100 110101010 0101 111101011 0101 111001100 0110 101001101 0110 101101110 0111 100101111 0111 100010000 1000 100010001 1000 100110010 1001 101110011 1001 101010100 1010 111010101 1010 111110110 1011 110110111 1011 110011000 1100 010011001 1100 010111010 1101 011111011 1101 011011100 1110 001011101 1110 001111110 1111 000111111 1111 0000

Using (2) the next states corresponding to (16) to (19) can bedetermined as follows

1198763+ = 119863119877 oplus 1198763 oplus 1198763 = 119863119877 (20)

1198762+ = 1198763 oplus 1198762 oplus 1198762 = 1198763 (21)

1198761+ = 1198762 oplus 1198761 oplus 1198761 = 1198762 (22)

1198760+ = 1198761 oplus 1198760 oplus 1198760 = 1198761 (23)

Similarly the next states of a four-bit serial-in serial-out left-shift register can be determined as follows where 119863119871 is theserial data input

1198763+ = 1198762 (24)

1198762+ = 1198761 (25)

1198761+ = 1198760 (26)

1198760+ = 119863119871 (27)

Equations (20) to (27) are implemented with reversible gatesto build the circuit shown in Figure 8 Multiplexing is neededfor implementing right-shift and left-shift between 119863119877 and1198762 for 1198763+ between 1198763 and 1198761 for 1198762+ between 1198762and 1198760 for 1198761+ and between 1198761 and 119863119871 for 1198760+ This isimplemented using four controlled swap gates controlled bythe shift direction control input 119872 in the Next State Logicsection of the circuit Implementations of the other sectionsare similar to those in Figure 7 The different modes ofoperations are explained below

(1) C = 1 and L = 0 Serial-In Serial-Out Register If119872 = 0expressions (20) to (23) are implemented by the Next StateLogic section and data is shifted right If119872 = 1 expressions(24) to (27) are implemented and data is shifted left When119862 is changed to 0 the next states are passed to the presentstate outputs through the Asynchronous Load section of thecircuit

(2) Serial-In Parallel-Out Register The operation is similar tostep (1) and the present state outputs are taken in parallel

(3) C = 1 and L = 1 Parallel-In Parallel-Out Register Theparallel input values 1198633 1198632 1198631 and 1198630 are loaded to thepresent state outputs through theAsynchronous Load sectionby setting 119871 = 1 and then changing to 119871 = 0 Outputs aretaken in parallel

(4) Parallel-In Serial-Out Register The asynchronous loadoperation is similar to step (3) After setting 119871 = 0 if 119862 ischanged to 0 the states will be shifted to either right or leftbased on the value of119872

The quantum cost of the circuit in Figure 8 is 74 and14 ancilla inputs are required The circuit complexity iscompared with that of previous work in Table 6 From thetable we see that the present design saves both quantum costand ancilla inputs as compared to the replacement design in[40] It is to be noted that in [40] the number of ancilla inputsis not mentioned We count only the 0-initialized workinginputs as ancilla inputs and do not include a large number ofcontrol inputs as ancilla inputs The present design also saveson quantum cost as compared to the direct design in [26] butrequires slightly more ancilla inputs

6 Online Testable Design ofSequential Circuits

In this section we introduce our proposed technique foronline testing of single line faults in sequential circuit Wefocus only on single line faults because some of the missingcontrol fault and missing gate fault situations can be treatedas single line faults For example if a missing control faultinverts the original target output of the gate then that faultcan be treated as a single line fault at the target output of thegate Similarly if a gate produces an inverted output at the

VLSI Design 9

Q0

Q1

Q2

Q3

0

0

0

0

0

0

C C

0

0

Next state logic triggerFalling-edge

Feedback

Q2

Q1

Q0

+Q3

+Q2

+Q1

+Q0

M M

L LAsynchronous load

0

DR

0

0

Q3

DL

0

0

0

D0

D1

D2

D3

Figure 8 Reversible realization of the four-bit falling-edge triggered universal register [43]

Table 6 Comparison of reversible realization of the four-bit falling-edge triggered universal register with that of the replacement designin [40] and the direct design in [26]

Quantum cost Ancilla input

Replacement design [40] 220 18

Direct design [26] 112 12

Present design 74 14 improvement overreplacement design [40]

6636 2222

improvement overdirect design [26]

3393 minus1667

target then the missing gate will not produce that inversionand this condition can be treated as a single line fault atthat position Thus online detection of single line faults alsodetects some missing control and missing gate faults

61 Online Testing of Single Line Fault in Toffoli Circuits AToffoli circuit is a cascade of NOT CNOT and Toffoli gatesIn [44] a method for online detection of single line fault inToffoli circuits is presented The method in [44] is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) All CNOT and Toffoli gates of the given circuit arereplaced by their corresponding extended versions(EFGs and ETGs respectively) The second target ofall gates is the parity line 119871

(4) The NOT gates in the given circuit are retained If thenumber of NOT gates in the given circuit is odd thenan extra NOT gate is added at the end of the parityline 119871

10 VLSI Design

L = 0 O

I1I2I3

O1

O2

O3

Figure 9 Online testing of a single line fault in a Fredkin circuit

(5) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(6) If the circuit is fault free then the parity output will be0 otherwise it will be 1

62 Online Testing of Single Line Faults in Fredkin CircuitsA Fredkin circuit is a cascade consisting of only Fredkin(controlled swap) gates To our knowledge there is noexisting work on offline or online testing of Fredkin circuitsWe propose here a technique for online testing of single linefaults in Fredkin circuits The procedure is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(4) If the circuit is fault free then the parity output will be0 otherwise it will be 1

A simple example of the above technique is shown in Figure 9In a controlled swap gate the target inputs are either swappedor not swapped depending on the control value Thus theoutputs of a controlled swap gate are a permutation ofthe inputs Similarly the outputs of a Fredkin circuit are apermutation of the inputs In Figure 9 the parity output iscomputed as

119874 = (1198681 oplus 1198682 oplus 1198683) oplus (1198681 oplus 1198682 oplus 1198683) (28)

If there is no single line fault in the circuit then the parityoutput119874 of (28) will be 0 since each pair (input output) willbe canceled If any single line fault occurs anywhere in thecircuit then any of 119868119899 where 119899 isin 1 2 3will be inverted at theoutput Thus the parity output 119874 will be 1 since 119868119899 oplus 119868

1015840

119899= 1

If a single line fault occurs at any point in the parity line theparity output 119874 will also be 1 since if any subexpression in(28) is inverted then 119874 will be 1

63 Online Testing of Single Line Faults in Sequential CircuitsIn our proposedmethod for online testing of single line faultsin sequential circuits we use the technique in [44] for testing

the Toffoli circuits in the (i) Modified Next State Logic andNext State Logic sections together and test the (ii) Feedbacksection and (iii) Output Logic section separately We thenuse our proposed technique for online testing of single linefaults in Fredkin circuits in the Falling-Edge Trigger andResetAsynchronous Load sections together

The online testable version of the reversible sequentialcircuit in Figure 6 is shown in Figure 10 The design of thetestable circuit is described below

(1) The Modified Next State Logic and Next State Logicsections together are a Toffoli circuit We make thiscircuit testable by adding 0-initialized parity input119871119872119873 This portion of the circuit has five active inputs119909 two 1-initialized inputs 1198761 and 1198760 Five CNOTgates are added at the beginning of this portion andanother five CNOT gates are added at the end of thisportion OneCNOT gate and three Toffoli gates in theoriginal circuit are replaced by their correspondingextended versions There are three NOT gates inthe original circuit so an extra NOT gate is addedalong the parity line If any single line fault occursin this section then the parity output 119874119872119873 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 20

(2) The Falling-Edge Trigger and Asynchronous Resetsections together are a Fredkin circuit We make thiscircuit testable by adding 0-initialized parity input119871119879119871This portion of the circuit has eight active inputs119877 119862 1198761+ 1198761 1198760+ 1198760 and two 0-initialized inputsEight CNOT gates are added at the beginning of thisportion and another eight CNOT gates are added atthe end of this portion If any single line fault occursin this section then the parity output 119874119879119871 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 16

(3) The Feedback section of the circuit is a Toffoli circuitWe make this circuit testable by adding 0-initializedparity input 119871119865 This portion of the circuit has fouractive inputs 1198761 1198760 and two 0-initialized inputsThis portion of the circuit is made testable using thetechnique described in Section 61 If any single linefault occurs in this section then the parity output 119874119865will be 1 otherwise it will be 0The overhead quantumcost of this section is 10

(4) The Output Logic section of the circuit is a Toffolicircuit We make this circuit testable by adding 0-initialized parity input 119871119874 This portion of the circuithas two active inputs 119909 and 1198760 This portion of thecircuit is made testable using the technique describedin Section 61 If any single line fault occurs in thissection then the parity output 119874119874 will be 1 otherwiseit will be 0The overhead quantum cost of this sectionis 5

(5) Multiple line faults in different sections can bedetected simultaneously Therefore from the parityoutputs fault sections can be located

VLSI Design 11

Table 7 Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks both before and after addinggates for testability

Filename Inputs Outputs States Total before testability Total after testabilityGC QC Number of lines GC QC Number of lines increase in QC

bbara 4 2 10 46 1096 14 116 1242 18 1330bbsse 7 7 16 99 1361 22 185 1629 26 1970bbtas 2 2 6 21 203 10 73 285 14 4040beecount 3 4 7 53 577 13 111 729 17 2630cse 7 7 16 137 2922 22 223 3266 26 1180dk14 3 5 7 104 973 14 164 1229 18 2630dk512 3 5 4 58 491 12 104 645 16 3140donfile 2 1 24 67 877 13 145 1069 17 2190ex1 9 19 20 355 3979 38 483 4797 42 2060ex2 2 2 19 97 1924 14 177 2178 18 1320ex3 2 2 10 51 715 12 117 867 16 2130ex4 6 9 14 74 618 23 162 838 27 3560ex5 2 2 9 43 631 12 109 767 16 2160ex7 2 2 10 48 680 12 114 826 16 2150keyb 7 2 19 110 4946 19 200 5236 23 590lion9 2 1 9 34 505 11 98 621 15 2300lion 2 1 4 15 79 7 51 137 11 7340planet1 7 19 48 646 4763 38 784 6169 42 2950planet 7 19 48 646 4763 38 784 6169 42 2950s1a 8 6 20 97 3668 24 197 3942 28 750s1 8 6 20 197 3864 24 297 4338 28 1230s8 4 1 5 36 1036 11 90 1150 15 1100sand 11 9 32 288 4941 30 400 5609 34 1350shiftreg 1 1 8 17 29 8 65 99 12 24140sse 7 7 16 98 1378 22 184 1644 26 1930styr 9 10 30 338 6553 29 448 7319 33 1170tav 4 4 4 23 403 12 69 487 16 2080tbk 6 3 32 110 3621 19 200 3911 23 800train11 2 1 11 47 742 11 111 884 15 1910train4 2 1 4 18 103 7 54 167 11 6210

The total overhead quantum cost of the circuit in Figure 10 is20 + 16 + 10 + 5 = 51 The quantum cost of the original circuitin Figure 6 is 53Therefore the quantum cost overhead of thetestable circuit is only 9623

7 Experimental Results

The process for designing the sequential reversible circuitand adding the gates for testability was applied to severalsequential benchmarks from theMCNC suite of benchmarks[48] As shown in Table 7 the additional circuitry requiredfor making the sequential reversible circuit testable adds anaverage of 30 overhead in terms of quantum cost Thehighest percentage overhead occurs for the smallest circuitsthis is a result of needing to copy the input and output linesseveral times In larger circuits the percentage overhead issignificantly lower

8 Conclusion

In this work an improved synthesis approach for sequentialreversible circuits is presented Three design examples aredemonstrated including an arbitrary sequential circuit with2-bit states 1-bit input and 1-bit output (Figure 4) a four-bitfalling-edge triggered updown counter with asynchronousload and a four-bit falling-edge triggered universal registerare shown We compare the quantum cost and the ancillainputs of the three designs with both the replacement designtechnique and the direct design technique reported in [26]The new design of the sequential circuit in Figure 4 saves4479 and 3977 in quantum cost and 6667 and 3333in ancilla inputs as compared to the replacement design anddirect design in [26] respectively The new counter designsaves 2128 in quantumcostwith the samenumber of ancillainputs as compared to the design in [26] The new registerdesign saves 6636 in quantum cost and 2222 in ancilla

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

VLSI Design 3

x xy yxoplusz zxoplus

x xy yxoplusz zxoplus

(a)

x xw w

y ywxoplusz zwxoplus

x xw w

y ywxoplusz zwxoplus

(b)

Figure 2 The symbol and logic level implementations for (a) the extended Feynman gate and (b) a 2-control extended Toffoli gate

A

B

C

D

0

A

B

C

D

F = A oplus BD oplus ACD oplus BCD

Figure 3 Reversible circuit implementing (1)

EFG is 2 In Figure 2(b) a 2-control ETG and its logic levelimplementation are shownThe quantum cost of an ETG is 2plus the quantum cost of the corresponding Toffoli gate Thequantum cost of the ETG in Figure 2(b) is 5 + 2 = 7

22 Reversible Logic Synthesis Using ESOP Expressions Anexclusive-OR sum of products (ESOP) expression is similarto a conventional sum of products (SOP) expression exceptthat product terms are combined with exclusive-OR (EXOR)operators rather than OR operators [31] A common tech-nique in reversible logic synthesis is to express the logicfunction as an ESOP expression and then realize the ESOPexpression as a cascade of NOT CNOT and Toffoli gates [32]An example ESOP expression is given in (1) and its reversiblerealization as a cascade of NOT CNOT and Toffoli gates isshown in Figure 3

119865 (119860 119861 119862119863) = 119860 oplus 119861119863 oplus 119860119862119863 oplus 119861119862119863 (1)

23 Sequential Circuits The classical model of a sequentialcircuit is shown in Figure 4 A sequential circuit has amemory whose content during the present clock cycle iscalled the present state The combinational circuit producesthe output as a function of the present state and the inputThe combinational circuit also produces the next state as afunction of the present state and the input this computednext state becomes the present state during the next clockcycle The behavior of a sequential circuit is described usinga state transition diagram In describing a sequential circuitthe present state is represented by 119876 and the next state isrepresented by 119876+ An example sequential circuit is shownin the state transition diagram in Figure 4 It has 1-bit input(119909) 1-bit output (119911) and 2-bit state (11987611198760) The reset state is00

24 Testing of Reversible Circuits Testing is very importantto ensure quality availability and reliability of a circuitThereare two approaches to circuit testing offline testing andonlinetesting [33] In offline testing a circuit is tested when it is not

in normal operation In online testing however the circuitmust be able to continue normal operations while testing iscarried out For online testing additional circuitry is generallyadded to the original circuit to determine whether the circuitis faulty or not There are three fault models line faults (orbit faults) [33] missing control faults which is one instanceof crosspoint faults [34] andmissing gate faults [35] In a linefault the logic value of a line is flipped and produces faultyoutput In a missing control fault the control point of a gateeither is not working or disappears from the gate resulting inan incorrect value for the target output In amissing gate faultthe entire gate does not work or the gate disappears from thecircuit causing faulty output

3 Related Work

In this section we discuss related work on reversible sequen-tial circuit design and on online testing of reversible combi-national circuits

31 Related Work on Reversible Sequential Circuit DesignThere are many attempts at designing reversible latches flip-flops and sequential circuits Some important but nonex-haustive work on reversible sequential logic design includes[25 26 36ndash42] References [36ndash39] present reversible designsfor latches and flip-flops using reversible gates and sug-gest that sequential circuits be synthesized by replacingthe latches flip-flops and gates of the combinational partof the traditional irreversible designs with their reversiblecounterparts Following this replacement approach the workin [40] presents a design for a four-bit falling-edge-triggereduniversal register and the work in [41] presents a designfor a four-bit level-triggered up counter with asynchronousparallel load The work in [25] again uses the replacementtechnique and demonstrates that reversible circuits can beimplemented using QCA technology with offline testing ofthe QCA-based sequential circuitThe work in [42] offers thefirst attempt to synthesize a sequential circuit using directfeedback of the state output and without using any flip-flopsReference [42] also presents a design for a level-triggeredup counter using positive polarity Reed-Muller expressionsfor representing the next states The up counter design ismore efficient than the replacement design in [41] in termsof both quantum cost and garbage outputs (outputs that arenot used for the intended circuit realization) The next stepto this work is presented in [26] which details the directdesign of arbitrary sequential circuits using pseudo-Reed-Muller expressions for representing the next statesThis workalso introduces modifications making the circuit falling-edgetriggered and asynchronous loadable The updown counterin [26] is better than that in [41] in terms of both quantum

4 VLSI Design

Combinational logic

Memory

Input Output

Nex

t sta

te

Pres

ent s

tate

Clock(a)

00

10

0111

1110

00

110110

00

01

Reset

(b)

Figure 4 (a) Model of a sequential circuit (b) State transition diagram of an example sequential circuit

cost and garbage outputs and the universal register in [26]improves upon the design in [40] again for both quantumcostand garbage output

A further improvement of the work in [26] is presented in[43] In [43] a new technique for representing the next statesusing exclusive-OR sum-of-product (ESOP) expressions ispresented Using this technique designs for a four-bit falling-edge triggered updown counter with asynchronous loadingand a four-bit falling-edge triggered universal register arepresented Both designs in [43] offer improvements overthose from [26] in terms of both quantum cost and ancillainput This work is an extended version of [43]

32 Related Work on Testing of Reversible CombinationalCircuits Several works offer techniques for online testingof reversible combinational circuits Some propose newtestable gates which are then used to construct online testablereversible circuits In [17] three new reversible gates areproposed two of which are used to design an online testableblock and the other is used to create a checker circuit Thechecker circuit compares the two parity bits produced by theonline testable blocks in order to test a single bit fault In [23]an improved approach to single bit fault testing is proposedthat does not require a checker circuit

The most generalized approaches offer online testing ofreversible circuits synthesized using NOT CNOT and Toffoligates In [44] all of the Toffoli gates are replaced by extendedToffoli gates and two sets of CNOT gates and one additionalparity line are added to the original circuit to achieve onlinetestability for single line faults In [45] a DFT- (design fortestability-) based offline approach is proposed for detectingsingle missing gate faults In [46] an online fault detectionapproach is proposed for detecting single missing gate faultsIn [47] each of the Toffoli gates is accompanied by a duplicateToffoli gate of the same size with the same control lines butthe target is placed on an additional parity line to make theToffoli gate a testable Toffoli block Two sets of CNOT gatesare also used for which the targets are the parity line Thisapproach detects all three types of faults

To the best of our knowledge no work has been reportedin the literature on offline or online testing of reversiblesequential circuits

4 Synthesis of Sequential Reversible Circuits

In this section we present our proposedmethod for synthesisof sequential reversible circuits

41 Representing the Next State Let 119876 and 119876+ be the presentstate and the next state of a sequential circuit respectively119876+can be expressed as a function of 119876 and 119876+ as follows

119876+ = 119876 oplus 119876 oplus 119876+ = 119876 oplus 119876lowast (2)

where

119876lowast = 119876 oplus 119876+ (3)

We call 119876lowast the modified next state In our proposedtechnique themodifiednext state is determinedusing (3) andis expressed as a minimized ESOP expression of a functionof the inputs and the present state The next state is thenexpressed using (2)

42 Synthesis Model Our model for the reversible synthesisof sequential circuits is shown in Figure 5 First the modifiednext state 119876lowast is generated as a function of the inputs andpresent state in the Modified Next State Logic section Thenext state is generated using (2) in the Next State Logicsection The generated next state is loaded to the stateoutput as the present state at the falling-edge of the clock inthe Falling-Edge Trigger section The asynchronous reset orload is carried out in the Asynchronous Load section Thefeedback of the present state is generated in the Feedbacksection and the present state is fed back to the Modified NextState Logic section Finally in the Output Logic section theoutput is generated as a function of the input and the presentstate The following examples explain the use of this model

5 Design Examples

In this section we use three examples to illustrate the designmodel discussed in Section 42

51 Example 1 Sequential Circuit from Figure 4(b) The truthtable representing the next states (1198761+1198760+) the modifiednext states (1198761lowast1198760lowast) and the output (119911) of the sequentialcircuit in Figure 4(b) is shown in Table 1 The modified nextstates (1198761lowast1198760lowast) and the output (119911) are minimized as ESOPexpressions as follows

1198761lowast = 11987601015840 oplus 11990911987611198760 (4)

1198760lowast = 1 oplus 119909101584011987611015840 oplus 119876110158401198760 (5)

119911 = 1198760 oplus 1199091015840 (6)

VLSI Design 5

Modifiednextstatelogic

InputsNextstatelogicQ

Falling-edge

triggering

C

QReset or

asynchronousloading

Q

0D

RL

Feedback

C

0

Q

Q

Q

Outputlogic

0D

Q

RL

CInputs

01

Q

Inputs Inputs

Outputs

01Qlowast Q+ Q+

Q+Q+

Figure 5 Model of reversible synthesis of sequential circuit

R R

C

x

1

1

Q1

Q0

0

0

Q0

Q1 Q1

Q0

Modified next state logicNext state

logicFalling-edge

triggerAsynchronous

reset

0

0

Feedback

Q1

Q0

Outputlogic

C

z

Q0lowast

Q1lowast

Q0+

Q1+

Figure 6 Reversible realization of the sequential circuit described by Figure 4(b)

Table 1 Truth table representing the next states the modified nextstates and the output of the sequential circuit from Figure 4(b)

11990911987611198760 1198761+1198760+ 1198761lowast1198760lowast 119911

000 10 10 1001 00 01 0010 01 11 1011 10 01 0100 11 11 0101 01 00 1110 01 11 0111 00 11 1

Equations (4) (5) and (6) are then used to implement thestatemachine fromFigure 4(b) resulting in the circuit shownin Figure 6 Each section of this circuit is explained below

(1) Modified Next State Logic The modified next states 1198761lowastand1198760lowast (see (4) and (5)) are realized as functions of the input119909 and the fed-back present states 1198761 and 1198760 as a cascadeof NOT CNOT and Toffoli gates The quantum cost of thissection is 28 and 2 ancilla inputs are required

(2) Next State LogicThe next states are realized as1198761+ = 1198761oplus1198761lowast and 1198760+ = 1198760 oplus 1198760lowast using the generated modified nextstates 1198761lowast and 1198760lowast and fed-back present states 1198761 and 1198760This requires two CNOT gates and thus the quantum costof this section is exactly equal to the number of bits in thestate of the sequential circuit since for each bit a CNOT gateis required and the quantum cost of the CNOT gate is 1 Noancilla inputs are required

(3) Falling-Edge Trigger The falling-edge triggering isachieved using two controlled swap gates controlled by theclock 119862 When the clock 119862 = 1 and reset 119877 = 0 the fed-backstates are passed to the state outputs maintaining the stateoutputs unchanged When the clock is set to 119862 = 0 and 119877 = 0is maintained then the generated next states are transmittedto the state outputs Just after the next states arrive at the stateoutput and the feedback of the present states arrives at theFalling-Edge Trigger section the clock must be set to 119862 = 1in order tomaintain the new present state at the outputThusthe changes of the present states occur at the falling-edge ofthe clock 119862 and the duration of the period of 119862 = 0 has to bevery carefully determined to avoidmalfunction of the circuitThe quantum cost of this section is 5 times the number of bitsrequired for the state of the sequential circuit since for eachbit a controlled swap gate is required and the quantum cost of

6 VLSI Design

the controlled swap gate is 5 Thus the quantum cost of thissection is 10 and no ancilla inputs are required

(4) Reset The reset is achieved using two controlled swapgates controlled by the reset input 119877 In the sequentialcircuit represented by Figure 4 the reset state is 00 Duringsynchronous operation the clock must be set to 119862 = 1 andthe reset must be cleared to 119877 = 0 to maintain the presentstate unchanged For the falling-edge triggering action theclock and the reset must both be cleared to 119862119877 = 00 Thereset action takes place asynchronously when the clock andthe reset are both set to 119862119877 = 11 In this case the constantinputs 00 are transmitted to the state outputs At this pointthe reset must be set to 119877 = 0 in order to maintain the stateoutputs unchanged Again the duration of the reset value119877 = 1 must be carefully determined to avoid malfunctionof the sequential circuit The quantum cost of this section isalso 5 times the number of bits in the state of the sequentialcircuit since for each bit a controlled swap gate is requiredand the quantum cost of the controlled swap gate is 5 Thissection requires ancilla inputs exactly equal to the number ofbits in the state Thus the quantum cost of this section is 10and 2 ancilla inputs are required

(5) Feedback The feedback of the present state is generatedusing two CNOT gates used as copying gates and is achievedby setting the target input to be 0 The quantum cost of thissection is exactly equal to the number of the bits in the stateof the sequential circuit since one CNOT gate is required foreach bit of the state and the quantum cost of the CNOT gateis 1 This section requires ancilla inputs exactly equal to thenumber of bits in the state of the sequential circuit since foreach bit of the state one constant-initialized input is requiredThe quantum cost of this section is 2 and 2 ancilla inputs arerequired

(6) Output Logic The output 119911 is realized as a function of theinput 119909 and the present state 1198760 using (6)

The total quantum cost of the circuit in Figure 6 is 53and 6 ancilla inputs are required These values are comparedwith those of the replacement design approach in [26] andthe direct design in [26] in Table 2 The improvement overprevious designs is calculated using the formula

Improvement = Previous minus PresentPrevious

times 100 (7)

From Table 2 we see that our new present design techniquesaves significantly on quantum cost and ancilla inputs ascompared to both previous replacement design techniqueand the direct design technique presented in [26]

52 Example 2 4-Bit UpDown Counter In this sectionwe illustrate the application of our technique to the designof a four-bit falling-edge trigged updown counter withasynchronous load The truth table representing the nextstates and the modified next states of the counter is shownin Table 3Themodified next states of the four-bit up counterfrom Table 3 are minimized as ESOP expressions as follows

1198763lowast = 119876211987611198760 (8)

Table 2 Comparison of reversible realization of the sequentialcircuit in Figure 6 with replacement design method and directdesign method in [26]

Quantum cost Ancilla inputReplacement design [26] 96 18Direct design [26] 88 9Present design 53 6 improvement overreplacement design [26] 4479 6667

improvement overdirect design [26] 3977 3333

Table 3 Truth table representing the next states and the modifiednext states of a four-bit up counter [43]

Present state Next state Modified next state1198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

0000 0001 00010001 0010 00110010 0011 00010011 0100 01110100 0101 00010101 0110 00110110 0111 00010111 1000 11111000 1001 00011001 1010 00111010 1011 00011011 1100 01111100 1101 00011101 1110 00111110 1111 00011111 0000 1111

1198762lowast = 11987611198760 (9)

1198761lowast = 1198760 (10)

1198760lowast = 1 (11)

Similarly the modified next states of the four-bit downcounter are minimized as ESOP expressions as follows

1198763lowast = 119876210158401198761101584011987601015840 (12)

1198762lowast = 1198761101584011987601015840 (13)

1198761lowast = 11987601015840 (14)

1198760lowast = 1 (15)

The complete counter is implemented using the ESOP expres-sions (8) to (15) and the resulting reversible circuit is shownin Figure 7 where 119862 is the clock input the input 119871 performsthe asynchronous load with 119871 = 0 for normal operation and119871 = 1 for asynchronous load and the input119872 determines thecount direction with119872 = 0 for up and119872 = 1 for down The

VLSI Design 7

Q0

Q1

Q2

Q3

0

0

0

0

1

0

C C

0

0

Q3

Q2

Q1

Q0

Q0lowast

Q1lowast

Q2lowast

Q3lowast Q3

+Q2

+Q1

+Q0

M

Q2

Q1

Q0

Q3

M

L LModified next state logic

Nextstatelogic

Falling-edgetrigger Asynchronous load Feedback

D0

D1

D2

D3

+

Figure 7 Reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load [43]

design is similar to that of the previous example (Example 1)The operation of the circuit is discussed below

(1) C = 1 and L = 1 Asynchronous Load The data inputs 11986331198632 1198631 and 1198630 are loaded to the present state outputs 11987631198762 1198761 and 1198760 (respectively) through the controlled swapgates that make up the Asynchronous Load section of thecircuit After loading the input data we set 119871 = 0 to maintainthe present state output

(2) M = 0 Modified Next State Generation for Up CountThe six 119872-controlled CNOT gates of the Modified NextState Logic section will not modify the logic values of theirtargets and the fed-back state values 1198763 1198762 1198761 and 1198760remain unchanged These fed-back state values are used inthe Modified Next State Logic section to generate modifiednext states 1198763lowast 1198762lowast 1198761lowast and 1198760lowast (see (8) to (11))

(3) M = 1 Modified Next State Generation for Down CountThe first three CNOT gates controlled by 119872 complementthe fed-back present states 1198763 1198762 1198761 and 1198760 Thesecomplemented values are used in the Modified Next StateLogic section to generatemodified next states1198763lowast1198762lowast1198761lowastand 1198760lowast (see (12) to (15)) The last three CNOT gates ofthe Modified Next State Logic section restore the fed-backpresent states for use in the Next State Logic section of thecircuit

The circuit in Figure 7 has a quantum cost of 74 andrequires 8 ancilla inputs The complexity of our design is

Table 4 Comparison of reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load with thatin [26] (including data previously presented in [43])

Quantum cost Ancilla inputDesign of [26] 94 8Present design 74 8 improvement overdesign of [26] 2128 0

compared with that in [26] as shown in Table 4 From thetable we see that the present design saves quantum cost withno increase of ancilla inputs

53 Example 3 4-Bit Universal Register In this section weillustrate the synthesis process for a four-bit falling-edgetriggered universal register The truth table representing thenext states and the modified next states is shown in Table 5where 119863119877 is the serial data input The modified next states1198763lowast1198762lowast1198761lowast and1198760lowast are minimized as ESOP expressionsas follows

1198763lowast = 119863119877 oplus 1198763 (16)

1198762lowast = 1198763 oplus 1198762 (17)

1198761lowast = 1198762 oplus 1198761 (18)

1198760lowast = 1198761 oplus 1198760 (19)

8 VLSI Design

Table 5 Truth table representing the next states and the modifiednext states of a four-bit serial-in serial-out right-shift register [43]

Present state Next state Modified next state1198631198771198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

00000 0000 000000001 0000 000100010 0001 001100011 0001 001000100 0010 011000101 0010 011100110 0011 010100111 0011 010001000 0100 110001001 0100 110101010 0101 111101011 0101 111001100 0110 101001101 0110 101101110 0111 100101111 0111 100010000 1000 100010001 1000 100110010 1001 101110011 1001 101010100 1010 111010101 1010 111110110 1011 110110111 1011 110011000 1100 010011001 1100 010111010 1101 011111011 1101 011011100 1110 001011101 1110 001111110 1111 000111111 1111 0000

Using (2) the next states corresponding to (16) to (19) can bedetermined as follows

1198763+ = 119863119877 oplus 1198763 oplus 1198763 = 119863119877 (20)

1198762+ = 1198763 oplus 1198762 oplus 1198762 = 1198763 (21)

1198761+ = 1198762 oplus 1198761 oplus 1198761 = 1198762 (22)

1198760+ = 1198761 oplus 1198760 oplus 1198760 = 1198761 (23)

Similarly the next states of a four-bit serial-in serial-out left-shift register can be determined as follows where 119863119871 is theserial data input

1198763+ = 1198762 (24)

1198762+ = 1198761 (25)

1198761+ = 1198760 (26)

1198760+ = 119863119871 (27)

Equations (20) to (27) are implemented with reversible gatesto build the circuit shown in Figure 8 Multiplexing is neededfor implementing right-shift and left-shift between 119863119877 and1198762 for 1198763+ between 1198763 and 1198761 for 1198762+ between 1198762and 1198760 for 1198761+ and between 1198761 and 119863119871 for 1198760+ This isimplemented using four controlled swap gates controlled bythe shift direction control input 119872 in the Next State Logicsection of the circuit Implementations of the other sectionsare similar to those in Figure 7 The different modes ofoperations are explained below

(1) C = 1 and L = 0 Serial-In Serial-Out Register If119872 = 0expressions (20) to (23) are implemented by the Next StateLogic section and data is shifted right If119872 = 1 expressions(24) to (27) are implemented and data is shifted left When119862 is changed to 0 the next states are passed to the presentstate outputs through the Asynchronous Load section of thecircuit

(2) Serial-In Parallel-Out Register The operation is similar tostep (1) and the present state outputs are taken in parallel

(3) C = 1 and L = 1 Parallel-In Parallel-Out Register Theparallel input values 1198633 1198632 1198631 and 1198630 are loaded to thepresent state outputs through theAsynchronous Load sectionby setting 119871 = 1 and then changing to 119871 = 0 Outputs aretaken in parallel

(4) Parallel-In Serial-Out Register The asynchronous loadoperation is similar to step (3) After setting 119871 = 0 if 119862 ischanged to 0 the states will be shifted to either right or leftbased on the value of119872

The quantum cost of the circuit in Figure 8 is 74 and14 ancilla inputs are required The circuit complexity iscompared with that of previous work in Table 6 From thetable we see that the present design saves both quantum costand ancilla inputs as compared to the replacement design in[40] It is to be noted that in [40] the number of ancilla inputsis not mentioned We count only the 0-initialized workinginputs as ancilla inputs and do not include a large number ofcontrol inputs as ancilla inputs The present design also saveson quantum cost as compared to the direct design in [26] butrequires slightly more ancilla inputs

6 Online Testable Design ofSequential Circuits

In this section we introduce our proposed technique foronline testing of single line faults in sequential circuit Wefocus only on single line faults because some of the missingcontrol fault and missing gate fault situations can be treatedas single line faults For example if a missing control faultinverts the original target output of the gate then that faultcan be treated as a single line fault at the target output of thegate Similarly if a gate produces an inverted output at the

VLSI Design 9

Q0

Q1

Q2

Q3

0

0

0

0

0

0

C C

0

0

Next state logic triggerFalling-edge

Feedback

Q2

Q1

Q0

+Q3

+Q2

+Q1

+Q0

M M

L LAsynchronous load

0

DR

0

0

Q3

DL

0

0

0

D0

D1

D2

D3

Figure 8 Reversible realization of the four-bit falling-edge triggered universal register [43]

Table 6 Comparison of reversible realization of the four-bit falling-edge triggered universal register with that of the replacement designin [40] and the direct design in [26]

Quantum cost Ancilla input

Replacement design [40] 220 18

Direct design [26] 112 12

Present design 74 14 improvement overreplacement design [40]

6636 2222

improvement overdirect design [26]

3393 minus1667

target then the missing gate will not produce that inversionand this condition can be treated as a single line fault atthat position Thus online detection of single line faults alsodetects some missing control and missing gate faults

61 Online Testing of Single Line Fault in Toffoli Circuits AToffoli circuit is a cascade of NOT CNOT and Toffoli gatesIn [44] a method for online detection of single line fault inToffoli circuits is presented The method in [44] is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) All CNOT and Toffoli gates of the given circuit arereplaced by their corresponding extended versions(EFGs and ETGs respectively) The second target ofall gates is the parity line 119871

(4) The NOT gates in the given circuit are retained If thenumber of NOT gates in the given circuit is odd thenan extra NOT gate is added at the end of the parityline 119871

10 VLSI Design

L = 0 O

I1I2I3

O1

O2

O3

Figure 9 Online testing of a single line fault in a Fredkin circuit

(5) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(6) If the circuit is fault free then the parity output will be0 otherwise it will be 1

62 Online Testing of Single Line Faults in Fredkin CircuitsA Fredkin circuit is a cascade consisting of only Fredkin(controlled swap) gates To our knowledge there is noexisting work on offline or online testing of Fredkin circuitsWe propose here a technique for online testing of single linefaults in Fredkin circuits The procedure is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(4) If the circuit is fault free then the parity output will be0 otherwise it will be 1

A simple example of the above technique is shown in Figure 9In a controlled swap gate the target inputs are either swappedor not swapped depending on the control value Thus theoutputs of a controlled swap gate are a permutation ofthe inputs Similarly the outputs of a Fredkin circuit are apermutation of the inputs In Figure 9 the parity output iscomputed as

119874 = (1198681 oplus 1198682 oplus 1198683) oplus (1198681 oplus 1198682 oplus 1198683) (28)

If there is no single line fault in the circuit then the parityoutput119874 of (28) will be 0 since each pair (input output) willbe canceled If any single line fault occurs anywhere in thecircuit then any of 119868119899 where 119899 isin 1 2 3will be inverted at theoutput Thus the parity output 119874 will be 1 since 119868119899 oplus 119868

1015840

119899= 1

If a single line fault occurs at any point in the parity line theparity output 119874 will also be 1 since if any subexpression in(28) is inverted then 119874 will be 1

63 Online Testing of Single Line Faults in Sequential CircuitsIn our proposedmethod for online testing of single line faultsin sequential circuits we use the technique in [44] for testing

the Toffoli circuits in the (i) Modified Next State Logic andNext State Logic sections together and test the (ii) Feedbacksection and (iii) Output Logic section separately We thenuse our proposed technique for online testing of single linefaults in Fredkin circuits in the Falling-Edge Trigger andResetAsynchronous Load sections together

The online testable version of the reversible sequentialcircuit in Figure 6 is shown in Figure 10 The design of thetestable circuit is described below

(1) The Modified Next State Logic and Next State Logicsections together are a Toffoli circuit We make thiscircuit testable by adding 0-initialized parity input119871119872119873 This portion of the circuit has five active inputs119909 two 1-initialized inputs 1198761 and 1198760 Five CNOTgates are added at the beginning of this portion andanother five CNOT gates are added at the end of thisportion OneCNOT gate and three Toffoli gates in theoriginal circuit are replaced by their correspondingextended versions There are three NOT gates inthe original circuit so an extra NOT gate is addedalong the parity line If any single line fault occursin this section then the parity output 119874119872119873 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 20

(2) The Falling-Edge Trigger and Asynchronous Resetsections together are a Fredkin circuit We make thiscircuit testable by adding 0-initialized parity input119871119879119871This portion of the circuit has eight active inputs119877 119862 1198761+ 1198761 1198760+ 1198760 and two 0-initialized inputsEight CNOT gates are added at the beginning of thisportion and another eight CNOT gates are added atthe end of this portion If any single line fault occursin this section then the parity output 119874119879119871 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 16

(3) The Feedback section of the circuit is a Toffoli circuitWe make this circuit testable by adding 0-initializedparity input 119871119865 This portion of the circuit has fouractive inputs 1198761 1198760 and two 0-initialized inputsThis portion of the circuit is made testable using thetechnique described in Section 61 If any single linefault occurs in this section then the parity output 119874119865will be 1 otherwise it will be 0The overhead quantumcost of this section is 10

(4) The Output Logic section of the circuit is a Toffolicircuit We make this circuit testable by adding 0-initialized parity input 119871119874 This portion of the circuithas two active inputs 119909 and 1198760 This portion of thecircuit is made testable using the technique describedin Section 61 If any single line fault occurs in thissection then the parity output 119874119874 will be 1 otherwiseit will be 0The overhead quantum cost of this sectionis 5

(5) Multiple line faults in different sections can bedetected simultaneously Therefore from the parityoutputs fault sections can be located

VLSI Design 11

Table 7 Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks both before and after addinggates for testability

Filename Inputs Outputs States Total before testability Total after testabilityGC QC Number of lines GC QC Number of lines increase in QC

bbara 4 2 10 46 1096 14 116 1242 18 1330bbsse 7 7 16 99 1361 22 185 1629 26 1970bbtas 2 2 6 21 203 10 73 285 14 4040beecount 3 4 7 53 577 13 111 729 17 2630cse 7 7 16 137 2922 22 223 3266 26 1180dk14 3 5 7 104 973 14 164 1229 18 2630dk512 3 5 4 58 491 12 104 645 16 3140donfile 2 1 24 67 877 13 145 1069 17 2190ex1 9 19 20 355 3979 38 483 4797 42 2060ex2 2 2 19 97 1924 14 177 2178 18 1320ex3 2 2 10 51 715 12 117 867 16 2130ex4 6 9 14 74 618 23 162 838 27 3560ex5 2 2 9 43 631 12 109 767 16 2160ex7 2 2 10 48 680 12 114 826 16 2150keyb 7 2 19 110 4946 19 200 5236 23 590lion9 2 1 9 34 505 11 98 621 15 2300lion 2 1 4 15 79 7 51 137 11 7340planet1 7 19 48 646 4763 38 784 6169 42 2950planet 7 19 48 646 4763 38 784 6169 42 2950s1a 8 6 20 97 3668 24 197 3942 28 750s1 8 6 20 197 3864 24 297 4338 28 1230s8 4 1 5 36 1036 11 90 1150 15 1100sand 11 9 32 288 4941 30 400 5609 34 1350shiftreg 1 1 8 17 29 8 65 99 12 24140sse 7 7 16 98 1378 22 184 1644 26 1930styr 9 10 30 338 6553 29 448 7319 33 1170tav 4 4 4 23 403 12 69 487 16 2080tbk 6 3 32 110 3621 19 200 3911 23 800train11 2 1 11 47 742 11 111 884 15 1910train4 2 1 4 18 103 7 54 167 11 6210

The total overhead quantum cost of the circuit in Figure 10 is20 + 16 + 10 + 5 = 51 The quantum cost of the original circuitin Figure 6 is 53Therefore the quantum cost overhead of thetestable circuit is only 9623

7 Experimental Results

The process for designing the sequential reversible circuitand adding the gates for testability was applied to severalsequential benchmarks from theMCNC suite of benchmarks[48] As shown in Table 7 the additional circuitry requiredfor making the sequential reversible circuit testable adds anaverage of 30 overhead in terms of quantum cost Thehighest percentage overhead occurs for the smallest circuitsthis is a result of needing to copy the input and output linesseveral times In larger circuits the percentage overhead issignificantly lower

8 Conclusion

In this work an improved synthesis approach for sequentialreversible circuits is presented Three design examples aredemonstrated including an arbitrary sequential circuit with2-bit states 1-bit input and 1-bit output (Figure 4) a four-bitfalling-edge triggered updown counter with asynchronousload and a four-bit falling-edge triggered universal registerare shown We compare the quantum cost and the ancillainputs of the three designs with both the replacement designtechnique and the direct design technique reported in [26]The new design of the sequential circuit in Figure 4 saves4479 and 3977 in quantum cost and 6667 and 3333in ancilla inputs as compared to the replacement design anddirect design in [26] respectively The new counter designsaves 2128 in quantumcostwith the samenumber of ancillainputs as compared to the design in [26] The new registerdesign saves 6636 in quantum cost and 2222 in ancilla

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

4 VLSI Design

Combinational logic

Memory

Input Output

Nex

t sta

te

Pres

ent s

tate

Clock(a)

00

10

0111

1110

00

110110

00

01

Reset

(b)

Figure 4 (a) Model of a sequential circuit (b) State transition diagram of an example sequential circuit

cost and garbage outputs and the universal register in [26]improves upon the design in [40] again for both quantumcostand garbage output

A further improvement of the work in [26] is presented in[43] In [43] a new technique for representing the next statesusing exclusive-OR sum-of-product (ESOP) expressions ispresented Using this technique designs for a four-bit falling-edge triggered updown counter with asynchronous loadingand a four-bit falling-edge triggered universal register arepresented Both designs in [43] offer improvements overthose from [26] in terms of both quantum cost and ancillainput This work is an extended version of [43]

32 Related Work on Testing of Reversible CombinationalCircuits Several works offer techniques for online testingof reversible combinational circuits Some propose newtestable gates which are then used to construct online testablereversible circuits In [17] three new reversible gates areproposed two of which are used to design an online testableblock and the other is used to create a checker circuit Thechecker circuit compares the two parity bits produced by theonline testable blocks in order to test a single bit fault In [23]an improved approach to single bit fault testing is proposedthat does not require a checker circuit

The most generalized approaches offer online testing ofreversible circuits synthesized using NOT CNOT and Toffoligates In [44] all of the Toffoli gates are replaced by extendedToffoli gates and two sets of CNOT gates and one additionalparity line are added to the original circuit to achieve onlinetestability for single line faults In [45] a DFT- (design fortestability-) based offline approach is proposed for detectingsingle missing gate faults In [46] an online fault detectionapproach is proposed for detecting single missing gate faultsIn [47] each of the Toffoli gates is accompanied by a duplicateToffoli gate of the same size with the same control lines butthe target is placed on an additional parity line to make theToffoli gate a testable Toffoli block Two sets of CNOT gatesare also used for which the targets are the parity line Thisapproach detects all three types of faults

To the best of our knowledge no work has been reportedin the literature on offline or online testing of reversiblesequential circuits

4 Synthesis of Sequential Reversible Circuits

In this section we present our proposedmethod for synthesisof sequential reversible circuits

41 Representing the Next State Let 119876 and 119876+ be the presentstate and the next state of a sequential circuit respectively119876+can be expressed as a function of 119876 and 119876+ as follows

119876+ = 119876 oplus 119876 oplus 119876+ = 119876 oplus 119876lowast (2)

where

119876lowast = 119876 oplus 119876+ (3)

We call 119876lowast the modified next state In our proposedtechnique themodifiednext state is determinedusing (3) andis expressed as a minimized ESOP expression of a functionof the inputs and the present state The next state is thenexpressed using (2)

42 Synthesis Model Our model for the reversible synthesisof sequential circuits is shown in Figure 5 First the modifiednext state 119876lowast is generated as a function of the inputs andpresent state in the Modified Next State Logic section Thenext state is generated using (2) in the Next State Logicsection The generated next state is loaded to the stateoutput as the present state at the falling-edge of the clock inthe Falling-Edge Trigger section The asynchronous reset orload is carried out in the Asynchronous Load section Thefeedback of the present state is generated in the Feedbacksection and the present state is fed back to the Modified NextState Logic section Finally in the Output Logic section theoutput is generated as a function of the input and the presentstate The following examples explain the use of this model

5 Design Examples

In this section we use three examples to illustrate the designmodel discussed in Section 42

51 Example 1 Sequential Circuit from Figure 4(b) The truthtable representing the next states (1198761+1198760+) the modifiednext states (1198761lowast1198760lowast) and the output (119911) of the sequentialcircuit in Figure 4(b) is shown in Table 1 The modified nextstates (1198761lowast1198760lowast) and the output (119911) are minimized as ESOPexpressions as follows

1198761lowast = 11987601015840 oplus 11990911987611198760 (4)

1198760lowast = 1 oplus 119909101584011987611015840 oplus 119876110158401198760 (5)

119911 = 1198760 oplus 1199091015840 (6)

VLSI Design 5

Modifiednextstatelogic

InputsNextstatelogicQ

Falling-edge

triggering

C

QReset or

asynchronousloading

Q

0D

RL

Feedback

C

0

Q

Q

Q

Outputlogic

0D

Q

RL

CInputs

01

Q

Inputs Inputs

Outputs

01Qlowast Q+ Q+

Q+Q+

Figure 5 Model of reversible synthesis of sequential circuit

R R

C

x

1

1

Q1

Q0

0

0

Q0

Q1 Q1

Q0

Modified next state logicNext state

logicFalling-edge

triggerAsynchronous

reset

0

0

Feedback

Q1

Q0

Outputlogic

C

z

Q0lowast

Q1lowast

Q0+

Q1+

Figure 6 Reversible realization of the sequential circuit described by Figure 4(b)

Table 1 Truth table representing the next states the modified nextstates and the output of the sequential circuit from Figure 4(b)

11990911987611198760 1198761+1198760+ 1198761lowast1198760lowast 119911

000 10 10 1001 00 01 0010 01 11 1011 10 01 0100 11 11 0101 01 00 1110 01 11 0111 00 11 1

Equations (4) (5) and (6) are then used to implement thestatemachine fromFigure 4(b) resulting in the circuit shownin Figure 6 Each section of this circuit is explained below

(1) Modified Next State Logic The modified next states 1198761lowastand1198760lowast (see (4) and (5)) are realized as functions of the input119909 and the fed-back present states 1198761 and 1198760 as a cascadeof NOT CNOT and Toffoli gates The quantum cost of thissection is 28 and 2 ancilla inputs are required

(2) Next State LogicThe next states are realized as1198761+ = 1198761oplus1198761lowast and 1198760+ = 1198760 oplus 1198760lowast using the generated modified nextstates 1198761lowast and 1198760lowast and fed-back present states 1198761 and 1198760This requires two CNOT gates and thus the quantum costof this section is exactly equal to the number of bits in thestate of the sequential circuit since for each bit a CNOT gateis required and the quantum cost of the CNOT gate is 1 Noancilla inputs are required

(3) Falling-Edge Trigger The falling-edge triggering isachieved using two controlled swap gates controlled by theclock 119862 When the clock 119862 = 1 and reset 119877 = 0 the fed-backstates are passed to the state outputs maintaining the stateoutputs unchanged When the clock is set to 119862 = 0 and 119877 = 0is maintained then the generated next states are transmittedto the state outputs Just after the next states arrive at the stateoutput and the feedback of the present states arrives at theFalling-Edge Trigger section the clock must be set to 119862 = 1in order tomaintain the new present state at the outputThusthe changes of the present states occur at the falling-edge ofthe clock 119862 and the duration of the period of 119862 = 0 has to bevery carefully determined to avoidmalfunction of the circuitThe quantum cost of this section is 5 times the number of bitsrequired for the state of the sequential circuit since for eachbit a controlled swap gate is required and the quantum cost of

6 VLSI Design

the controlled swap gate is 5 Thus the quantum cost of thissection is 10 and no ancilla inputs are required

(4) Reset The reset is achieved using two controlled swapgates controlled by the reset input 119877 In the sequentialcircuit represented by Figure 4 the reset state is 00 Duringsynchronous operation the clock must be set to 119862 = 1 andthe reset must be cleared to 119877 = 0 to maintain the presentstate unchanged For the falling-edge triggering action theclock and the reset must both be cleared to 119862119877 = 00 Thereset action takes place asynchronously when the clock andthe reset are both set to 119862119877 = 11 In this case the constantinputs 00 are transmitted to the state outputs At this pointthe reset must be set to 119877 = 0 in order to maintain the stateoutputs unchanged Again the duration of the reset value119877 = 1 must be carefully determined to avoid malfunctionof the sequential circuit The quantum cost of this section isalso 5 times the number of bits in the state of the sequentialcircuit since for each bit a controlled swap gate is requiredand the quantum cost of the controlled swap gate is 5 Thissection requires ancilla inputs exactly equal to the number ofbits in the state Thus the quantum cost of this section is 10and 2 ancilla inputs are required

(5) Feedback The feedback of the present state is generatedusing two CNOT gates used as copying gates and is achievedby setting the target input to be 0 The quantum cost of thissection is exactly equal to the number of the bits in the stateof the sequential circuit since one CNOT gate is required foreach bit of the state and the quantum cost of the CNOT gateis 1 This section requires ancilla inputs exactly equal to thenumber of bits in the state of the sequential circuit since foreach bit of the state one constant-initialized input is requiredThe quantum cost of this section is 2 and 2 ancilla inputs arerequired

(6) Output Logic The output 119911 is realized as a function of theinput 119909 and the present state 1198760 using (6)

The total quantum cost of the circuit in Figure 6 is 53and 6 ancilla inputs are required These values are comparedwith those of the replacement design approach in [26] andthe direct design in [26] in Table 2 The improvement overprevious designs is calculated using the formula

Improvement = Previous minus PresentPrevious

times 100 (7)

From Table 2 we see that our new present design techniquesaves significantly on quantum cost and ancilla inputs ascompared to both previous replacement design techniqueand the direct design technique presented in [26]

52 Example 2 4-Bit UpDown Counter In this sectionwe illustrate the application of our technique to the designof a four-bit falling-edge trigged updown counter withasynchronous load The truth table representing the nextstates and the modified next states of the counter is shownin Table 3Themodified next states of the four-bit up counterfrom Table 3 are minimized as ESOP expressions as follows

1198763lowast = 119876211987611198760 (8)

Table 2 Comparison of reversible realization of the sequentialcircuit in Figure 6 with replacement design method and directdesign method in [26]

Quantum cost Ancilla inputReplacement design [26] 96 18Direct design [26] 88 9Present design 53 6 improvement overreplacement design [26] 4479 6667

improvement overdirect design [26] 3977 3333

Table 3 Truth table representing the next states and the modifiednext states of a four-bit up counter [43]

Present state Next state Modified next state1198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

0000 0001 00010001 0010 00110010 0011 00010011 0100 01110100 0101 00010101 0110 00110110 0111 00010111 1000 11111000 1001 00011001 1010 00111010 1011 00011011 1100 01111100 1101 00011101 1110 00111110 1111 00011111 0000 1111

1198762lowast = 11987611198760 (9)

1198761lowast = 1198760 (10)

1198760lowast = 1 (11)

Similarly the modified next states of the four-bit downcounter are minimized as ESOP expressions as follows

1198763lowast = 119876210158401198761101584011987601015840 (12)

1198762lowast = 1198761101584011987601015840 (13)

1198761lowast = 11987601015840 (14)

1198760lowast = 1 (15)

The complete counter is implemented using the ESOP expres-sions (8) to (15) and the resulting reversible circuit is shownin Figure 7 where 119862 is the clock input the input 119871 performsthe asynchronous load with 119871 = 0 for normal operation and119871 = 1 for asynchronous load and the input119872 determines thecount direction with119872 = 0 for up and119872 = 1 for down The

VLSI Design 7

Q0

Q1

Q2

Q3

0

0

0

0

1

0

C C

0

0

Q3

Q2

Q1

Q0

Q0lowast

Q1lowast

Q2lowast

Q3lowast Q3

+Q2

+Q1

+Q0

M

Q2

Q1

Q0

Q3

M

L LModified next state logic

Nextstatelogic

Falling-edgetrigger Asynchronous load Feedback

D0

D1

D2

D3

+

Figure 7 Reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load [43]

design is similar to that of the previous example (Example 1)The operation of the circuit is discussed below

(1) C = 1 and L = 1 Asynchronous Load The data inputs 11986331198632 1198631 and 1198630 are loaded to the present state outputs 11987631198762 1198761 and 1198760 (respectively) through the controlled swapgates that make up the Asynchronous Load section of thecircuit After loading the input data we set 119871 = 0 to maintainthe present state output

(2) M = 0 Modified Next State Generation for Up CountThe six 119872-controlled CNOT gates of the Modified NextState Logic section will not modify the logic values of theirtargets and the fed-back state values 1198763 1198762 1198761 and 1198760remain unchanged These fed-back state values are used inthe Modified Next State Logic section to generate modifiednext states 1198763lowast 1198762lowast 1198761lowast and 1198760lowast (see (8) to (11))

(3) M = 1 Modified Next State Generation for Down CountThe first three CNOT gates controlled by 119872 complementthe fed-back present states 1198763 1198762 1198761 and 1198760 Thesecomplemented values are used in the Modified Next StateLogic section to generatemodified next states1198763lowast1198762lowast1198761lowastand 1198760lowast (see (12) to (15)) The last three CNOT gates ofthe Modified Next State Logic section restore the fed-backpresent states for use in the Next State Logic section of thecircuit

The circuit in Figure 7 has a quantum cost of 74 andrequires 8 ancilla inputs The complexity of our design is

Table 4 Comparison of reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load with thatin [26] (including data previously presented in [43])

Quantum cost Ancilla inputDesign of [26] 94 8Present design 74 8 improvement overdesign of [26] 2128 0

compared with that in [26] as shown in Table 4 From thetable we see that the present design saves quantum cost withno increase of ancilla inputs

53 Example 3 4-Bit Universal Register In this section weillustrate the synthesis process for a four-bit falling-edgetriggered universal register The truth table representing thenext states and the modified next states is shown in Table 5where 119863119877 is the serial data input The modified next states1198763lowast1198762lowast1198761lowast and1198760lowast are minimized as ESOP expressionsas follows

1198763lowast = 119863119877 oplus 1198763 (16)

1198762lowast = 1198763 oplus 1198762 (17)

1198761lowast = 1198762 oplus 1198761 (18)

1198760lowast = 1198761 oplus 1198760 (19)

8 VLSI Design

Table 5 Truth table representing the next states and the modifiednext states of a four-bit serial-in serial-out right-shift register [43]

Present state Next state Modified next state1198631198771198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

00000 0000 000000001 0000 000100010 0001 001100011 0001 001000100 0010 011000101 0010 011100110 0011 010100111 0011 010001000 0100 110001001 0100 110101010 0101 111101011 0101 111001100 0110 101001101 0110 101101110 0111 100101111 0111 100010000 1000 100010001 1000 100110010 1001 101110011 1001 101010100 1010 111010101 1010 111110110 1011 110110111 1011 110011000 1100 010011001 1100 010111010 1101 011111011 1101 011011100 1110 001011101 1110 001111110 1111 000111111 1111 0000

Using (2) the next states corresponding to (16) to (19) can bedetermined as follows

1198763+ = 119863119877 oplus 1198763 oplus 1198763 = 119863119877 (20)

1198762+ = 1198763 oplus 1198762 oplus 1198762 = 1198763 (21)

1198761+ = 1198762 oplus 1198761 oplus 1198761 = 1198762 (22)

1198760+ = 1198761 oplus 1198760 oplus 1198760 = 1198761 (23)

Similarly the next states of a four-bit serial-in serial-out left-shift register can be determined as follows where 119863119871 is theserial data input

1198763+ = 1198762 (24)

1198762+ = 1198761 (25)

1198761+ = 1198760 (26)

1198760+ = 119863119871 (27)

Equations (20) to (27) are implemented with reversible gatesto build the circuit shown in Figure 8 Multiplexing is neededfor implementing right-shift and left-shift between 119863119877 and1198762 for 1198763+ between 1198763 and 1198761 for 1198762+ between 1198762and 1198760 for 1198761+ and between 1198761 and 119863119871 for 1198760+ This isimplemented using four controlled swap gates controlled bythe shift direction control input 119872 in the Next State Logicsection of the circuit Implementations of the other sectionsare similar to those in Figure 7 The different modes ofoperations are explained below

(1) C = 1 and L = 0 Serial-In Serial-Out Register If119872 = 0expressions (20) to (23) are implemented by the Next StateLogic section and data is shifted right If119872 = 1 expressions(24) to (27) are implemented and data is shifted left When119862 is changed to 0 the next states are passed to the presentstate outputs through the Asynchronous Load section of thecircuit

(2) Serial-In Parallel-Out Register The operation is similar tostep (1) and the present state outputs are taken in parallel

(3) C = 1 and L = 1 Parallel-In Parallel-Out Register Theparallel input values 1198633 1198632 1198631 and 1198630 are loaded to thepresent state outputs through theAsynchronous Load sectionby setting 119871 = 1 and then changing to 119871 = 0 Outputs aretaken in parallel

(4) Parallel-In Serial-Out Register The asynchronous loadoperation is similar to step (3) After setting 119871 = 0 if 119862 ischanged to 0 the states will be shifted to either right or leftbased on the value of119872

The quantum cost of the circuit in Figure 8 is 74 and14 ancilla inputs are required The circuit complexity iscompared with that of previous work in Table 6 From thetable we see that the present design saves both quantum costand ancilla inputs as compared to the replacement design in[40] It is to be noted that in [40] the number of ancilla inputsis not mentioned We count only the 0-initialized workinginputs as ancilla inputs and do not include a large number ofcontrol inputs as ancilla inputs The present design also saveson quantum cost as compared to the direct design in [26] butrequires slightly more ancilla inputs

6 Online Testable Design ofSequential Circuits

In this section we introduce our proposed technique foronline testing of single line faults in sequential circuit Wefocus only on single line faults because some of the missingcontrol fault and missing gate fault situations can be treatedas single line faults For example if a missing control faultinverts the original target output of the gate then that faultcan be treated as a single line fault at the target output of thegate Similarly if a gate produces an inverted output at the

VLSI Design 9

Q0

Q1

Q2

Q3

0

0

0

0

0

0

C C

0

0

Next state logic triggerFalling-edge

Feedback

Q2

Q1

Q0

+Q3

+Q2

+Q1

+Q0

M M

L LAsynchronous load

0

DR

0

0

Q3

DL

0

0

0

D0

D1

D2

D3

Figure 8 Reversible realization of the four-bit falling-edge triggered universal register [43]

Table 6 Comparison of reversible realization of the four-bit falling-edge triggered universal register with that of the replacement designin [40] and the direct design in [26]

Quantum cost Ancilla input

Replacement design [40] 220 18

Direct design [26] 112 12

Present design 74 14 improvement overreplacement design [40]

6636 2222

improvement overdirect design [26]

3393 minus1667

target then the missing gate will not produce that inversionand this condition can be treated as a single line fault atthat position Thus online detection of single line faults alsodetects some missing control and missing gate faults

61 Online Testing of Single Line Fault in Toffoli Circuits AToffoli circuit is a cascade of NOT CNOT and Toffoli gatesIn [44] a method for online detection of single line fault inToffoli circuits is presented The method in [44] is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) All CNOT and Toffoli gates of the given circuit arereplaced by their corresponding extended versions(EFGs and ETGs respectively) The second target ofall gates is the parity line 119871

(4) The NOT gates in the given circuit are retained If thenumber of NOT gates in the given circuit is odd thenan extra NOT gate is added at the end of the parityline 119871

10 VLSI Design

L = 0 O

I1I2I3

O1

O2

O3

Figure 9 Online testing of a single line fault in a Fredkin circuit

(5) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(6) If the circuit is fault free then the parity output will be0 otherwise it will be 1

62 Online Testing of Single Line Faults in Fredkin CircuitsA Fredkin circuit is a cascade consisting of only Fredkin(controlled swap) gates To our knowledge there is noexisting work on offline or online testing of Fredkin circuitsWe propose here a technique for online testing of single linefaults in Fredkin circuits The procedure is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(4) If the circuit is fault free then the parity output will be0 otherwise it will be 1

A simple example of the above technique is shown in Figure 9In a controlled swap gate the target inputs are either swappedor not swapped depending on the control value Thus theoutputs of a controlled swap gate are a permutation ofthe inputs Similarly the outputs of a Fredkin circuit are apermutation of the inputs In Figure 9 the parity output iscomputed as

119874 = (1198681 oplus 1198682 oplus 1198683) oplus (1198681 oplus 1198682 oplus 1198683) (28)

If there is no single line fault in the circuit then the parityoutput119874 of (28) will be 0 since each pair (input output) willbe canceled If any single line fault occurs anywhere in thecircuit then any of 119868119899 where 119899 isin 1 2 3will be inverted at theoutput Thus the parity output 119874 will be 1 since 119868119899 oplus 119868

1015840

119899= 1

If a single line fault occurs at any point in the parity line theparity output 119874 will also be 1 since if any subexpression in(28) is inverted then 119874 will be 1

63 Online Testing of Single Line Faults in Sequential CircuitsIn our proposedmethod for online testing of single line faultsin sequential circuits we use the technique in [44] for testing

the Toffoli circuits in the (i) Modified Next State Logic andNext State Logic sections together and test the (ii) Feedbacksection and (iii) Output Logic section separately We thenuse our proposed technique for online testing of single linefaults in Fredkin circuits in the Falling-Edge Trigger andResetAsynchronous Load sections together

The online testable version of the reversible sequentialcircuit in Figure 6 is shown in Figure 10 The design of thetestable circuit is described below

(1) The Modified Next State Logic and Next State Logicsections together are a Toffoli circuit We make thiscircuit testable by adding 0-initialized parity input119871119872119873 This portion of the circuit has five active inputs119909 two 1-initialized inputs 1198761 and 1198760 Five CNOTgates are added at the beginning of this portion andanother five CNOT gates are added at the end of thisportion OneCNOT gate and three Toffoli gates in theoriginal circuit are replaced by their correspondingextended versions There are three NOT gates inthe original circuit so an extra NOT gate is addedalong the parity line If any single line fault occursin this section then the parity output 119874119872119873 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 20

(2) The Falling-Edge Trigger and Asynchronous Resetsections together are a Fredkin circuit We make thiscircuit testable by adding 0-initialized parity input119871119879119871This portion of the circuit has eight active inputs119877 119862 1198761+ 1198761 1198760+ 1198760 and two 0-initialized inputsEight CNOT gates are added at the beginning of thisportion and another eight CNOT gates are added atthe end of this portion If any single line fault occursin this section then the parity output 119874119879119871 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 16

(3) The Feedback section of the circuit is a Toffoli circuitWe make this circuit testable by adding 0-initializedparity input 119871119865 This portion of the circuit has fouractive inputs 1198761 1198760 and two 0-initialized inputsThis portion of the circuit is made testable using thetechnique described in Section 61 If any single linefault occurs in this section then the parity output 119874119865will be 1 otherwise it will be 0The overhead quantumcost of this section is 10

(4) The Output Logic section of the circuit is a Toffolicircuit We make this circuit testable by adding 0-initialized parity input 119871119874 This portion of the circuithas two active inputs 119909 and 1198760 This portion of thecircuit is made testable using the technique describedin Section 61 If any single line fault occurs in thissection then the parity output 119874119874 will be 1 otherwiseit will be 0The overhead quantum cost of this sectionis 5

(5) Multiple line faults in different sections can bedetected simultaneously Therefore from the parityoutputs fault sections can be located

VLSI Design 11

Table 7 Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks both before and after addinggates for testability

Filename Inputs Outputs States Total before testability Total after testabilityGC QC Number of lines GC QC Number of lines increase in QC

bbara 4 2 10 46 1096 14 116 1242 18 1330bbsse 7 7 16 99 1361 22 185 1629 26 1970bbtas 2 2 6 21 203 10 73 285 14 4040beecount 3 4 7 53 577 13 111 729 17 2630cse 7 7 16 137 2922 22 223 3266 26 1180dk14 3 5 7 104 973 14 164 1229 18 2630dk512 3 5 4 58 491 12 104 645 16 3140donfile 2 1 24 67 877 13 145 1069 17 2190ex1 9 19 20 355 3979 38 483 4797 42 2060ex2 2 2 19 97 1924 14 177 2178 18 1320ex3 2 2 10 51 715 12 117 867 16 2130ex4 6 9 14 74 618 23 162 838 27 3560ex5 2 2 9 43 631 12 109 767 16 2160ex7 2 2 10 48 680 12 114 826 16 2150keyb 7 2 19 110 4946 19 200 5236 23 590lion9 2 1 9 34 505 11 98 621 15 2300lion 2 1 4 15 79 7 51 137 11 7340planet1 7 19 48 646 4763 38 784 6169 42 2950planet 7 19 48 646 4763 38 784 6169 42 2950s1a 8 6 20 97 3668 24 197 3942 28 750s1 8 6 20 197 3864 24 297 4338 28 1230s8 4 1 5 36 1036 11 90 1150 15 1100sand 11 9 32 288 4941 30 400 5609 34 1350shiftreg 1 1 8 17 29 8 65 99 12 24140sse 7 7 16 98 1378 22 184 1644 26 1930styr 9 10 30 338 6553 29 448 7319 33 1170tav 4 4 4 23 403 12 69 487 16 2080tbk 6 3 32 110 3621 19 200 3911 23 800train11 2 1 11 47 742 11 111 884 15 1910train4 2 1 4 18 103 7 54 167 11 6210

The total overhead quantum cost of the circuit in Figure 10 is20 + 16 + 10 + 5 = 51 The quantum cost of the original circuitin Figure 6 is 53Therefore the quantum cost overhead of thetestable circuit is only 9623

7 Experimental Results

The process for designing the sequential reversible circuitand adding the gates for testability was applied to severalsequential benchmarks from theMCNC suite of benchmarks[48] As shown in Table 7 the additional circuitry requiredfor making the sequential reversible circuit testable adds anaverage of 30 overhead in terms of quantum cost Thehighest percentage overhead occurs for the smallest circuitsthis is a result of needing to copy the input and output linesseveral times In larger circuits the percentage overhead issignificantly lower

8 Conclusion

In this work an improved synthesis approach for sequentialreversible circuits is presented Three design examples aredemonstrated including an arbitrary sequential circuit with2-bit states 1-bit input and 1-bit output (Figure 4) a four-bitfalling-edge triggered updown counter with asynchronousload and a four-bit falling-edge triggered universal registerare shown We compare the quantum cost and the ancillainputs of the three designs with both the replacement designtechnique and the direct design technique reported in [26]The new design of the sequential circuit in Figure 4 saves4479 and 3977 in quantum cost and 6667 and 3333in ancilla inputs as compared to the replacement design anddirect design in [26] respectively The new counter designsaves 2128 in quantumcostwith the samenumber of ancillainputs as compared to the design in [26] The new registerdesign saves 6636 in quantum cost and 2222 in ancilla

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

VLSI Design 5

Modifiednextstatelogic

InputsNextstatelogicQ

Falling-edge

triggering

C

QReset or

asynchronousloading

Q

0D

RL

Feedback

C

0

Q

Q

Q

Outputlogic

0D

Q

RL

CInputs

01

Q

Inputs Inputs

Outputs

01Qlowast Q+ Q+

Q+Q+

Figure 5 Model of reversible synthesis of sequential circuit

R R

C

x

1

1

Q1

Q0

0

0

Q0

Q1 Q1

Q0

Modified next state logicNext state

logicFalling-edge

triggerAsynchronous

reset

0

0

Feedback

Q1

Q0

Outputlogic

C

z

Q0lowast

Q1lowast

Q0+

Q1+

Figure 6 Reversible realization of the sequential circuit described by Figure 4(b)

Table 1 Truth table representing the next states the modified nextstates and the output of the sequential circuit from Figure 4(b)

11990911987611198760 1198761+1198760+ 1198761lowast1198760lowast 119911

000 10 10 1001 00 01 0010 01 11 1011 10 01 0100 11 11 0101 01 00 1110 01 11 0111 00 11 1

Equations (4) (5) and (6) are then used to implement thestatemachine fromFigure 4(b) resulting in the circuit shownin Figure 6 Each section of this circuit is explained below

(1) Modified Next State Logic The modified next states 1198761lowastand1198760lowast (see (4) and (5)) are realized as functions of the input119909 and the fed-back present states 1198761 and 1198760 as a cascadeof NOT CNOT and Toffoli gates The quantum cost of thissection is 28 and 2 ancilla inputs are required

(2) Next State LogicThe next states are realized as1198761+ = 1198761oplus1198761lowast and 1198760+ = 1198760 oplus 1198760lowast using the generated modified nextstates 1198761lowast and 1198760lowast and fed-back present states 1198761 and 1198760This requires two CNOT gates and thus the quantum costof this section is exactly equal to the number of bits in thestate of the sequential circuit since for each bit a CNOT gateis required and the quantum cost of the CNOT gate is 1 Noancilla inputs are required

(3) Falling-Edge Trigger The falling-edge triggering isachieved using two controlled swap gates controlled by theclock 119862 When the clock 119862 = 1 and reset 119877 = 0 the fed-backstates are passed to the state outputs maintaining the stateoutputs unchanged When the clock is set to 119862 = 0 and 119877 = 0is maintained then the generated next states are transmittedto the state outputs Just after the next states arrive at the stateoutput and the feedback of the present states arrives at theFalling-Edge Trigger section the clock must be set to 119862 = 1in order tomaintain the new present state at the outputThusthe changes of the present states occur at the falling-edge ofthe clock 119862 and the duration of the period of 119862 = 0 has to bevery carefully determined to avoidmalfunction of the circuitThe quantum cost of this section is 5 times the number of bitsrequired for the state of the sequential circuit since for eachbit a controlled swap gate is required and the quantum cost of

6 VLSI Design

the controlled swap gate is 5 Thus the quantum cost of thissection is 10 and no ancilla inputs are required

(4) Reset The reset is achieved using two controlled swapgates controlled by the reset input 119877 In the sequentialcircuit represented by Figure 4 the reset state is 00 Duringsynchronous operation the clock must be set to 119862 = 1 andthe reset must be cleared to 119877 = 0 to maintain the presentstate unchanged For the falling-edge triggering action theclock and the reset must both be cleared to 119862119877 = 00 Thereset action takes place asynchronously when the clock andthe reset are both set to 119862119877 = 11 In this case the constantinputs 00 are transmitted to the state outputs At this pointthe reset must be set to 119877 = 0 in order to maintain the stateoutputs unchanged Again the duration of the reset value119877 = 1 must be carefully determined to avoid malfunctionof the sequential circuit The quantum cost of this section isalso 5 times the number of bits in the state of the sequentialcircuit since for each bit a controlled swap gate is requiredand the quantum cost of the controlled swap gate is 5 Thissection requires ancilla inputs exactly equal to the number ofbits in the state Thus the quantum cost of this section is 10and 2 ancilla inputs are required

(5) Feedback The feedback of the present state is generatedusing two CNOT gates used as copying gates and is achievedby setting the target input to be 0 The quantum cost of thissection is exactly equal to the number of the bits in the stateof the sequential circuit since one CNOT gate is required foreach bit of the state and the quantum cost of the CNOT gateis 1 This section requires ancilla inputs exactly equal to thenumber of bits in the state of the sequential circuit since foreach bit of the state one constant-initialized input is requiredThe quantum cost of this section is 2 and 2 ancilla inputs arerequired

(6) Output Logic The output 119911 is realized as a function of theinput 119909 and the present state 1198760 using (6)

The total quantum cost of the circuit in Figure 6 is 53and 6 ancilla inputs are required These values are comparedwith those of the replacement design approach in [26] andthe direct design in [26] in Table 2 The improvement overprevious designs is calculated using the formula

Improvement = Previous minus PresentPrevious

times 100 (7)

From Table 2 we see that our new present design techniquesaves significantly on quantum cost and ancilla inputs ascompared to both previous replacement design techniqueand the direct design technique presented in [26]

52 Example 2 4-Bit UpDown Counter In this sectionwe illustrate the application of our technique to the designof a four-bit falling-edge trigged updown counter withasynchronous load The truth table representing the nextstates and the modified next states of the counter is shownin Table 3Themodified next states of the four-bit up counterfrom Table 3 are minimized as ESOP expressions as follows

1198763lowast = 119876211987611198760 (8)

Table 2 Comparison of reversible realization of the sequentialcircuit in Figure 6 with replacement design method and directdesign method in [26]

Quantum cost Ancilla inputReplacement design [26] 96 18Direct design [26] 88 9Present design 53 6 improvement overreplacement design [26] 4479 6667

improvement overdirect design [26] 3977 3333

Table 3 Truth table representing the next states and the modifiednext states of a four-bit up counter [43]

Present state Next state Modified next state1198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

0000 0001 00010001 0010 00110010 0011 00010011 0100 01110100 0101 00010101 0110 00110110 0111 00010111 1000 11111000 1001 00011001 1010 00111010 1011 00011011 1100 01111100 1101 00011101 1110 00111110 1111 00011111 0000 1111

1198762lowast = 11987611198760 (9)

1198761lowast = 1198760 (10)

1198760lowast = 1 (11)

Similarly the modified next states of the four-bit downcounter are minimized as ESOP expressions as follows

1198763lowast = 119876210158401198761101584011987601015840 (12)

1198762lowast = 1198761101584011987601015840 (13)

1198761lowast = 11987601015840 (14)

1198760lowast = 1 (15)

The complete counter is implemented using the ESOP expres-sions (8) to (15) and the resulting reversible circuit is shownin Figure 7 where 119862 is the clock input the input 119871 performsthe asynchronous load with 119871 = 0 for normal operation and119871 = 1 for asynchronous load and the input119872 determines thecount direction with119872 = 0 for up and119872 = 1 for down The

VLSI Design 7

Q0

Q1

Q2

Q3

0

0

0

0

1

0

C C

0

0

Q3

Q2

Q1

Q0

Q0lowast

Q1lowast

Q2lowast

Q3lowast Q3

+Q2

+Q1

+Q0

M

Q2

Q1

Q0

Q3

M

L LModified next state logic

Nextstatelogic

Falling-edgetrigger Asynchronous load Feedback

D0

D1

D2

D3

+

Figure 7 Reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load [43]

design is similar to that of the previous example (Example 1)The operation of the circuit is discussed below

(1) C = 1 and L = 1 Asynchronous Load The data inputs 11986331198632 1198631 and 1198630 are loaded to the present state outputs 11987631198762 1198761 and 1198760 (respectively) through the controlled swapgates that make up the Asynchronous Load section of thecircuit After loading the input data we set 119871 = 0 to maintainthe present state output

(2) M = 0 Modified Next State Generation for Up CountThe six 119872-controlled CNOT gates of the Modified NextState Logic section will not modify the logic values of theirtargets and the fed-back state values 1198763 1198762 1198761 and 1198760remain unchanged These fed-back state values are used inthe Modified Next State Logic section to generate modifiednext states 1198763lowast 1198762lowast 1198761lowast and 1198760lowast (see (8) to (11))

(3) M = 1 Modified Next State Generation for Down CountThe first three CNOT gates controlled by 119872 complementthe fed-back present states 1198763 1198762 1198761 and 1198760 Thesecomplemented values are used in the Modified Next StateLogic section to generatemodified next states1198763lowast1198762lowast1198761lowastand 1198760lowast (see (12) to (15)) The last three CNOT gates ofthe Modified Next State Logic section restore the fed-backpresent states for use in the Next State Logic section of thecircuit

The circuit in Figure 7 has a quantum cost of 74 andrequires 8 ancilla inputs The complexity of our design is

Table 4 Comparison of reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load with thatin [26] (including data previously presented in [43])

Quantum cost Ancilla inputDesign of [26] 94 8Present design 74 8 improvement overdesign of [26] 2128 0

compared with that in [26] as shown in Table 4 From thetable we see that the present design saves quantum cost withno increase of ancilla inputs

53 Example 3 4-Bit Universal Register In this section weillustrate the synthesis process for a four-bit falling-edgetriggered universal register The truth table representing thenext states and the modified next states is shown in Table 5where 119863119877 is the serial data input The modified next states1198763lowast1198762lowast1198761lowast and1198760lowast are minimized as ESOP expressionsas follows

1198763lowast = 119863119877 oplus 1198763 (16)

1198762lowast = 1198763 oplus 1198762 (17)

1198761lowast = 1198762 oplus 1198761 (18)

1198760lowast = 1198761 oplus 1198760 (19)

8 VLSI Design

Table 5 Truth table representing the next states and the modifiednext states of a four-bit serial-in serial-out right-shift register [43]

Present state Next state Modified next state1198631198771198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

00000 0000 000000001 0000 000100010 0001 001100011 0001 001000100 0010 011000101 0010 011100110 0011 010100111 0011 010001000 0100 110001001 0100 110101010 0101 111101011 0101 111001100 0110 101001101 0110 101101110 0111 100101111 0111 100010000 1000 100010001 1000 100110010 1001 101110011 1001 101010100 1010 111010101 1010 111110110 1011 110110111 1011 110011000 1100 010011001 1100 010111010 1101 011111011 1101 011011100 1110 001011101 1110 001111110 1111 000111111 1111 0000

Using (2) the next states corresponding to (16) to (19) can bedetermined as follows

1198763+ = 119863119877 oplus 1198763 oplus 1198763 = 119863119877 (20)

1198762+ = 1198763 oplus 1198762 oplus 1198762 = 1198763 (21)

1198761+ = 1198762 oplus 1198761 oplus 1198761 = 1198762 (22)

1198760+ = 1198761 oplus 1198760 oplus 1198760 = 1198761 (23)

Similarly the next states of a four-bit serial-in serial-out left-shift register can be determined as follows where 119863119871 is theserial data input

1198763+ = 1198762 (24)

1198762+ = 1198761 (25)

1198761+ = 1198760 (26)

1198760+ = 119863119871 (27)

Equations (20) to (27) are implemented with reversible gatesto build the circuit shown in Figure 8 Multiplexing is neededfor implementing right-shift and left-shift between 119863119877 and1198762 for 1198763+ between 1198763 and 1198761 for 1198762+ between 1198762and 1198760 for 1198761+ and between 1198761 and 119863119871 for 1198760+ This isimplemented using four controlled swap gates controlled bythe shift direction control input 119872 in the Next State Logicsection of the circuit Implementations of the other sectionsare similar to those in Figure 7 The different modes ofoperations are explained below

(1) C = 1 and L = 0 Serial-In Serial-Out Register If119872 = 0expressions (20) to (23) are implemented by the Next StateLogic section and data is shifted right If119872 = 1 expressions(24) to (27) are implemented and data is shifted left When119862 is changed to 0 the next states are passed to the presentstate outputs through the Asynchronous Load section of thecircuit

(2) Serial-In Parallel-Out Register The operation is similar tostep (1) and the present state outputs are taken in parallel

(3) C = 1 and L = 1 Parallel-In Parallel-Out Register Theparallel input values 1198633 1198632 1198631 and 1198630 are loaded to thepresent state outputs through theAsynchronous Load sectionby setting 119871 = 1 and then changing to 119871 = 0 Outputs aretaken in parallel

(4) Parallel-In Serial-Out Register The asynchronous loadoperation is similar to step (3) After setting 119871 = 0 if 119862 ischanged to 0 the states will be shifted to either right or leftbased on the value of119872

The quantum cost of the circuit in Figure 8 is 74 and14 ancilla inputs are required The circuit complexity iscompared with that of previous work in Table 6 From thetable we see that the present design saves both quantum costand ancilla inputs as compared to the replacement design in[40] It is to be noted that in [40] the number of ancilla inputsis not mentioned We count only the 0-initialized workinginputs as ancilla inputs and do not include a large number ofcontrol inputs as ancilla inputs The present design also saveson quantum cost as compared to the direct design in [26] butrequires slightly more ancilla inputs

6 Online Testable Design ofSequential Circuits

In this section we introduce our proposed technique foronline testing of single line faults in sequential circuit Wefocus only on single line faults because some of the missingcontrol fault and missing gate fault situations can be treatedas single line faults For example if a missing control faultinverts the original target output of the gate then that faultcan be treated as a single line fault at the target output of thegate Similarly if a gate produces an inverted output at the

VLSI Design 9

Q0

Q1

Q2

Q3

0

0

0

0

0

0

C C

0

0

Next state logic triggerFalling-edge

Feedback

Q2

Q1

Q0

+Q3

+Q2

+Q1

+Q0

M M

L LAsynchronous load

0

DR

0

0

Q3

DL

0

0

0

D0

D1

D2

D3

Figure 8 Reversible realization of the four-bit falling-edge triggered universal register [43]

Table 6 Comparison of reversible realization of the four-bit falling-edge triggered universal register with that of the replacement designin [40] and the direct design in [26]

Quantum cost Ancilla input

Replacement design [40] 220 18

Direct design [26] 112 12

Present design 74 14 improvement overreplacement design [40]

6636 2222

improvement overdirect design [26]

3393 minus1667

target then the missing gate will not produce that inversionand this condition can be treated as a single line fault atthat position Thus online detection of single line faults alsodetects some missing control and missing gate faults

61 Online Testing of Single Line Fault in Toffoli Circuits AToffoli circuit is a cascade of NOT CNOT and Toffoli gatesIn [44] a method for online detection of single line fault inToffoli circuits is presented The method in [44] is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) All CNOT and Toffoli gates of the given circuit arereplaced by their corresponding extended versions(EFGs and ETGs respectively) The second target ofall gates is the parity line 119871

(4) The NOT gates in the given circuit are retained If thenumber of NOT gates in the given circuit is odd thenan extra NOT gate is added at the end of the parityline 119871

10 VLSI Design

L = 0 O

I1I2I3

O1

O2

O3

Figure 9 Online testing of a single line fault in a Fredkin circuit

(5) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(6) If the circuit is fault free then the parity output will be0 otherwise it will be 1

62 Online Testing of Single Line Faults in Fredkin CircuitsA Fredkin circuit is a cascade consisting of only Fredkin(controlled swap) gates To our knowledge there is noexisting work on offline or online testing of Fredkin circuitsWe propose here a technique for online testing of single linefaults in Fredkin circuits The procedure is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(4) If the circuit is fault free then the parity output will be0 otherwise it will be 1

A simple example of the above technique is shown in Figure 9In a controlled swap gate the target inputs are either swappedor not swapped depending on the control value Thus theoutputs of a controlled swap gate are a permutation ofthe inputs Similarly the outputs of a Fredkin circuit are apermutation of the inputs In Figure 9 the parity output iscomputed as

119874 = (1198681 oplus 1198682 oplus 1198683) oplus (1198681 oplus 1198682 oplus 1198683) (28)

If there is no single line fault in the circuit then the parityoutput119874 of (28) will be 0 since each pair (input output) willbe canceled If any single line fault occurs anywhere in thecircuit then any of 119868119899 where 119899 isin 1 2 3will be inverted at theoutput Thus the parity output 119874 will be 1 since 119868119899 oplus 119868

1015840

119899= 1

If a single line fault occurs at any point in the parity line theparity output 119874 will also be 1 since if any subexpression in(28) is inverted then 119874 will be 1

63 Online Testing of Single Line Faults in Sequential CircuitsIn our proposedmethod for online testing of single line faultsin sequential circuits we use the technique in [44] for testing

the Toffoli circuits in the (i) Modified Next State Logic andNext State Logic sections together and test the (ii) Feedbacksection and (iii) Output Logic section separately We thenuse our proposed technique for online testing of single linefaults in Fredkin circuits in the Falling-Edge Trigger andResetAsynchronous Load sections together

The online testable version of the reversible sequentialcircuit in Figure 6 is shown in Figure 10 The design of thetestable circuit is described below

(1) The Modified Next State Logic and Next State Logicsections together are a Toffoli circuit We make thiscircuit testable by adding 0-initialized parity input119871119872119873 This portion of the circuit has five active inputs119909 two 1-initialized inputs 1198761 and 1198760 Five CNOTgates are added at the beginning of this portion andanother five CNOT gates are added at the end of thisportion OneCNOT gate and three Toffoli gates in theoriginal circuit are replaced by their correspondingextended versions There are three NOT gates inthe original circuit so an extra NOT gate is addedalong the parity line If any single line fault occursin this section then the parity output 119874119872119873 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 20

(2) The Falling-Edge Trigger and Asynchronous Resetsections together are a Fredkin circuit We make thiscircuit testable by adding 0-initialized parity input119871119879119871This portion of the circuit has eight active inputs119877 119862 1198761+ 1198761 1198760+ 1198760 and two 0-initialized inputsEight CNOT gates are added at the beginning of thisportion and another eight CNOT gates are added atthe end of this portion If any single line fault occursin this section then the parity output 119874119879119871 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 16

(3) The Feedback section of the circuit is a Toffoli circuitWe make this circuit testable by adding 0-initializedparity input 119871119865 This portion of the circuit has fouractive inputs 1198761 1198760 and two 0-initialized inputsThis portion of the circuit is made testable using thetechnique described in Section 61 If any single linefault occurs in this section then the parity output 119874119865will be 1 otherwise it will be 0The overhead quantumcost of this section is 10

(4) The Output Logic section of the circuit is a Toffolicircuit We make this circuit testable by adding 0-initialized parity input 119871119874 This portion of the circuithas two active inputs 119909 and 1198760 This portion of thecircuit is made testable using the technique describedin Section 61 If any single line fault occurs in thissection then the parity output 119874119874 will be 1 otherwiseit will be 0The overhead quantum cost of this sectionis 5

(5) Multiple line faults in different sections can bedetected simultaneously Therefore from the parityoutputs fault sections can be located

VLSI Design 11

Table 7 Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks both before and after addinggates for testability

Filename Inputs Outputs States Total before testability Total after testabilityGC QC Number of lines GC QC Number of lines increase in QC

bbara 4 2 10 46 1096 14 116 1242 18 1330bbsse 7 7 16 99 1361 22 185 1629 26 1970bbtas 2 2 6 21 203 10 73 285 14 4040beecount 3 4 7 53 577 13 111 729 17 2630cse 7 7 16 137 2922 22 223 3266 26 1180dk14 3 5 7 104 973 14 164 1229 18 2630dk512 3 5 4 58 491 12 104 645 16 3140donfile 2 1 24 67 877 13 145 1069 17 2190ex1 9 19 20 355 3979 38 483 4797 42 2060ex2 2 2 19 97 1924 14 177 2178 18 1320ex3 2 2 10 51 715 12 117 867 16 2130ex4 6 9 14 74 618 23 162 838 27 3560ex5 2 2 9 43 631 12 109 767 16 2160ex7 2 2 10 48 680 12 114 826 16 2150keyb 7 2 19 110 4946 19 200 5236 23 590lion9 2 1 9 34 505 11 98 621 15 2300lion 2 1 4 15 79 7 51 137 11 7340planet1 7 19 48 646 4763 38 784 6169 42 2950planet 7 19 48 646 4763 38 784 6169 42 2950s1a 8 6 20 97 3668 24 197 3942 28 750s1 8 6 20 197 3864 24 297 4338 28 1230s8 4 1 5 36 1036 11 90 1150 15 1100sand 11 9 32 288 4941 30 400 5609 34 1350shiftreg 1 1 8 17 29 8 65 99 12 24140sse 7 7 16 98 1378 22 184 1644 26 1930styr 9 10 30 338 6553 29 448 7319 33 1170tav 4 4 4 23 403 12 69 487 16 2080tbk 6 3 32 110 3621 19 200 3911 23 800train11 2 1 11 47 742 11 111 884 15 1910train4 2 1 4 18 103 7 54 167 11 6210

The total overhead quantum cost of the circuit in Figure 10 is20 + 16 + 10 + 5 = 51 The quantum cost of the original circuitin Figure 6 is 53Therefore the quantum cost overhead of thetestable circuit is only 9623

7 Experimental Results

The process for designing the sequential reversible circuitand adding the gates for testability was applied to severalsequential benchmarks from theMCNC suite of benchmarks[48] As shown in Table 7 the additional circuitry requiredfor making the sequential reversible circuit testable adds anaverage of 30 overhead in terms of quantum cost Thehighest percentage overhead occurs for the smallest circuitsthis is a result of needing to copy the input and output linesseveral times In larger circuits the percentage overhead issignificantly lower

8 Conclusion

In this work an improved synthesis approach for sequentialreversible circuits is presented Three design examples aredemonstrated including an arbitrary sequential circuit with2-bit states 1-bit input and 1-bit output (Figure 4) a four-bitfalling-edge triggered updown counter with asynchronousload and a four-bit falling-edge triggered universal registerare shown We compare the quantum cost and the ancillainputs of the three designs with both the replacement designtechnique and the direct design technique reported in [26]The new design of the sequential circuit in Figure 4 saves4479 and 3977 in quantum cost and 6667 and 3333in ancilla inputs as compared to the replacement design anddirect design in [26] respectively The new counter designsaves 2128 in quantumcostwith the samenumber of ancillainputs as compared to the design in [26] The new registerdesign saves 6636 in quantum cost and 2222 in ancilla

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

6 VLSI Design

the controlled swap gate is 5 Thus the quantum cost of thissection is 10 and no ancilla inputs are required

(4) Reset The reset is achieved using two controlled swapgates controlled by the reset input 119877 In the sequentialcircuit represented by Figure 4 the reset state is 00 Duringsynchronous operation the clock must be set to 119862 = 1 andthe reset must be cleared to 119877 = 0 to maintain the presentstate unchanged For the falling-edge triggering action theclock and the reset must both be cleared to 119862119877 = 00 Thereset action takes place asynchronously when the clock andthe reset are both set to 119862119877 = 11 In this case the constantinputs 00 are transmitted to the state outputs At this pointthe reset must be set to 119877 = 0 in order to maintain the stateoutputs unchanged Again the duration of the reset value119877 = 1 must be carefully determined to avoid malfunctionof the sequential circuit The quantum cost of this section isalso 5 times the number of bits in the state of the sequentialcircuit since for each bit a controlled swap gate is requiredand the quantum cost of the controlled swap gate is 5 Thissection requires ancilla inputs exactly equal to the number ofbits in the state Thus the quantum cost of this section is 10and 2 ancilla inputs are required

(5) Feedback The feedback of the present state is generatedusing two CNOT gates used as copying gates and is achievedby setting the target input to be 0 The quantum cost of thissection is exactly equal to the number of the bits in the stateof the sequential circuit since one CNOT gate is required foreach bit of the state and the quantum cost of the CNOT gateis 1 This section requires ancilla inputs exactly equal to thenumber of bits in the state of the sequential circuit since foreach bit of the state one constant-initialized input is requiredThe quantum cost of this section is 2 and 2 ancilla inputs arerequired

(6) Output Logic The output 119911 is realized as a function of theinput 119909 and the present state 1198760 using (6)

The total quantum cost of the circuit in Figure 6 is 53and 6 ancilla inputs are required These values are comparedwith those of the replacement design approach in [26] andthe direct design in [26] in Table 2 The improvement overprevious designs is calculated using the formula

Improvement = Previous minus PresentPrevious

times 100 (7)

From Table 2 we see that our new present design techniquesaves significantly on quantum cost and ancilla inputs ascompared to both previous replacement design techniqueand the direct design technique presented in [26]

52 Example 2 4-Bit UpDown Counter In this sectionwe illustrate the application of our technique to the designof a four-bit falling-edge trigged updown counter withasynchronous load The truth table representing the nextstates and the modified next states of the counter is shownin Table 3Themodified next states of the four-bit up counterfrom Table 3 are minimized as ESOP expressions as follows

1198763lowast = 119876211987611198760 (8)

Table 2 Comparison of reversible realization of the sequentialcircuit in Figure 6 with replacement design method and directdesign method in [26]

Quantum cost Ancilla inputReplacement design [26] 96 18Direct design [26] 88 9Present design 53 6 improvement overreplacement design [26] 4479 6667

improvement overdirect design [26] 3977 3333

Table 3 Truth table representing the next states and the modifiednext states of a four-bit up counter [43]

Present state Next state Modified next state1198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

0000 0001 00010001 0010 00110010 0011 00010011 0100 01110100 0101 00010101 0110 00110110 0111 00010111 1000 11111000 1001 00011001 1010 00111010 1011 00011011 1100 01111100 1101 00011101 1110 00111110 1111 00011111 0000 1111

1198762lowast = 11987611198760 (9)

1198761lowast = 1198760 (10)

1198760lowast = 1 (11)

Similarly the modified next states of the four-bit downcounter are minimized as ESOP expressions as follows

1198763lowast = 119876210158401198761101584011987601015840 (12)

1198762lowast = 1198761101584011987601015840 (13)

1198761lowast = 11987601015840 (14)

1198760lowast = 1 (15)

The complete counter is implemented using the ESOP expres-sions (8) to (15) and the resulting reversible circuit is shownin Figure 7 where 119862 is the clock input the input 119871 performsthe asynchronous load with 119871 = 0 for normal operation and119871 = 1 for asynchronous load and the input119872 determines thecount direction with119872 = 0 for up and119872 = 1 for down The

VLSI Design 7

Q0

Q1

Q2

Q3

0

0

0

0

1

0

C C

0

0

Q3

Q2

Q1

Q0

Q0lowast

Q1lowast

Q2lowast

Q3lowast Q3

+Q2

+Q1

+Q0

M

Q2

Q1

Q0

Q3

M

L LModified next state logic

Nextstatelogic

Falling-edgetrigger Asynchronous load Feedback

D0

D1

D2

D3

+

Figure 7 Reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load [43]

design is similar to that of the previous example (Example 1)The operation of the circuit is discussed below

(1) C = 1 and L = 1 Asynchronous Load The data inputs 11986331198632 1198631 and 1198630 are loaded to the present state outputs 11987631198762 1198761 and 1198760 (respectively) through the controlled swapgates that make up the Asynchronous Load section of thecircuit After loading the input data we set 119871 = 0 to maintainthe present state output

(2) M = 0 Modified Next State Generation for Up CountThe six 119872-controlled CNOT gates of the Modified NextState Logic section will not modify the logic values of theirtargets and the fed-back state values 1198763 1198762 1198761 and 1198760remain unchanged These fed-back state values are used inthe Modified Next State Logic section to generate modifiednext states 1198763lowast 1198762lowast 1198761lowast and 1198760lowast (see (8) to (11))

(3) M = 1 Modified Next State Generation for Down CountThe first three CNOT gates controlled by 119872 complementthe fed-back present states 1198763 1198762 1198761 and 1198760 Thesecomplemented values are used in the Modified Next StateLogic section to generatemodified next states1198763lowast1198762lowast1198761lowastand 1198760lowast (see (12) to (15)) The last three CNOT gates ofthe Modified Next State Logic section restore the fed-backpresent states for use in the Next State Logic section of thecircuit

The circuit in Figure 7 has a quantum cost of 74 andrequires 8 ancilla inputs The complexity of our design is

Table 4 Comparison of reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load with thatin [26] (including data previously presented in [43])

Quantum cost Ancilla inputDesign of [26] 94 8Present design 74 8 improvement overdesign of [26] 2128 0

compared with that in [26] as shown in Table 4 From thetable we see that the present design saves quantum cost withno increase of ancilla inputs

53 Example 3 4-Bit Universal Register In this section weillustrate the synthesis process for a four-bit falling-edgetriggered universal register The truth table representing thenext states and the modified next states is shown in Table 5where 119863119877 is the serial data input The modified next states1198763lowast1198762lowast1198761lowast and1198760lowast are minimized as ESOP expressionsas follows

1198763lowast = 119863119877 oplus 1198763 (16)

1198762lowast = 1198763 oplus 1198762 (17)

1198761lowast = 1198762 oplus 1198761 (18)

1198760lowast = 1198761 oplus 1198760 (19)

8 VLSI Design

Table 5 Truth table representing the next states and the modifiednext states of a four-bit serial-in serial-out right-shift register [43]

Present state Next state Modified next state1198631198771198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

00000 0000 000000001 0000 000100010 0001 001100011 0001 001000100 0010 011000101 0010 011100110 0011 010100111 0011 010001000 0100 110001001 0100 110101010 0101 111101011 0101 111001100 0110 101001101 0110 101101110 0111 100101111 0111 100010000 1000 100010001 1000 100110010 1001 101110011 1001 101010100 1010 111010101 1010 111110110 1011 110110111 1011 110011000 1100 010011001 1100 010111010 1101 011111011 1101 011011100 1110 001011101 1110 001111110 1111 000111111 1111 0000

Using (2) the next states corresponding to (16) to (19) can bedetermined as follows

1198763+ = 119863119877 oplus 1198763 oplus 1198763 = 119863119877 (20)

1198762+ = 1198763 oplus 1198762 oplus 1198762 = 1198763 (21)

1198761+ = 1198762 oplus 1198761 oplus 1198761 = 1198762 (22)

1198760+ = 1198761 oplus 1198760 oplus 1198760 = 1198761 (23)

Similarly the next states of a four-bit serial-in serial-out left-shift register can be determined as follows where 119863119871 is theserial data input

1198763+ = 1198762 (24)

1198762+ = 1198761 (25)

1198761+ = 1198760 (26)

1198760+ = 119863119871 (27)

Equations (20) to (27) are implemented with reversible gatesto build the circuit shown in Figure 8 Multiplexing is neededfor implementing right-shift and left-shift between 119863119877 and1198762 for 1198763+ between 1198763 and 1198761 for 1198762+ between 1198762and 1198760 for 1198761+ and between 1198761 and 119863119871 for 1198760+ This isimplemented using four controlled swap gates controlled bythe shift direction control input 119872 in the Next State Logicsection of the circuit Implementations of the other sectionsare similar to those in Figure 7 The different modes ofoperations are explained below

(1) C = 1 and L = 0 Serial-In Serial-Out Register If119872 = 0expressions (20) to (23) are implemented by the Next StateLogic section and data is shifted right If119872 = 1 expressions(24) to (27) are implemented and data is shifted left When119862 is changed to 0 the next states are passed to the presentstate outputs through the Asynchronous Load section of thecircuit

(2) Serial-In Parallel-Out Register The operation is similar tostep (1) and the present state outputs are taken in parallel

(3) C = 1 and L = 1 Parallel-In Parallel-Out Register Theparallel input values 1198633 1198632 1198631 and 1198630 are loaded to thepresent state outputs through theAsynchronous Load sectionby setting 119871 = 1 and then changing to 119871 = 0 Outputs aretaken in parallel

(4) Parallel-In Serial-Out Register The asynchronous loadoperation is similar to step (3) After setting 119871 = 0 if 119862 ischanged to 0 the states will be shifted to either right or leftbased on the value of119872

The quantum cost of the circuit in Figure 8 is 74 and14 ancilla inputs are required The circuit complexity iscompared with that of previous work in Table 6 From thetable we see that the present design saves both quantum costand ancilla inputs as compared to the replacement design in[40] It is to be noted that in [40] the number of ancilla inputsis not mentioned We count only the 0-initialized workinginputs as ancilla inputs and do not include a large number ofcontrol inputs as ancilla inputs The present design also saveson quantum cost as compared to the direct design in [26] butrequires slightly more ancilla inputs

6 Online Testable Design ofSequential Circuits

In this section we introduce our proposed technique foronline testing of single line faults in sequential circuit Wefocus only on single line faults because some of the missingcontrol fault and missing gate fault situations can be treatedas single line faults For example if a missing control faultinverts the original target output of the gate then that faultcan be treated as a single line fault at the target output of thegate Similarly if a gate produces an inverted output at the

VLSI Design 9

Q0

Q1

Q2

Q3

0

0

0

0

0

0

C C

0

0

Next state logic triggerFalling-edge

Feedback

Q2

Q1

Q0

+Q3

+Q2

+Q1

+Q0

M M

L LAsynchronous load

0

DR

0

0

Q3

DL

0

0

0

D0

D1

D2

D3

Figure 8 Reversible realization of the four-bit falling-edge triggered universal register [43]

Table 6 Comparison of reversible realization of the four-bit falling-edge triggered universal register with that of the replacement designin [40] and the direct design in [26]

Quantum cost Ancilla input

Replacement design [40] 220 18

Direct design [26] 112 12

Present design 74 14 improvement overreplacement design [40]

6636 2222

improvement overdirect design [26]

3393 minus1667

target then the missing gate will not produce that inversionand this condition can be treated as a single line fault atthat position Thus online detection of single line faults alsodetects some missing control and missing gate faults

61 Online Testing of Single Line Fault in Toffoli Circuits AToffoli circuit is a cascade of NOT CNOT and Toffoli gatesIn [44] a method for online detection of single line fault inToffoli circuits is presented The method in [44] is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) All CNOT and Toffoli gates of the given circuit arereplaced by their corresponding extended versions(EFGs and ETGs respectively) The second target ofall gates is the parity line 119871

(4) The NOT gates in the given circuit are retained If thenumber of NOT gates in the given circuit is odd thenan extra NOT gate is added at the end of the parityline 119871

10 VLSI Design

L = 0 O

I1I2I3

O1

O2

O3

Figure 9 Online testing of a single line fault in a Fredkin circuit

(5) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(6) If the circuit is fault free then the parity output will be0 otherwise it will be 1

62 Online Testing of Single Line Faults in Fredkin CircuitsA Fredkin circuit is a cascade consisting of only Fredkin(controlled swap) gates To our knowledge there is noexisting work on offline or online testing of Fredkin circuitsWe propose here a technique for online testing of single linefaults in Fredkin circuits The procedure is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(4) If the circuit is fault free then the parity output will be0 otherwise it will be 1

A simple example of the above technique is shown in Figure 9In a controlled swap gate the target inputs are either swappedor not swapped depending on the control value Thus theoutputs of a controlled swap gate are a permutation ofthe inputs Similarly the outputs of a Fredkin circuit are apermutation of the inputs In Figure 9 the parity output iscomputed as

119874 = (1198681 oplus 1198682 oplus 1198683) oplus (1198681 oplus 1198682 oplus 1198683) (28)

If there is no single line fault in the circuit then the parityoutput119874 of (28) will be 0 since each pair (input output) willbe canceled If any single line fault occurs anywhere in thecircuit then any of 119868119899 where 119899 isin 1 2 3will be inverted at theoutput Thus the parity output 119874 will be 1 since 119868119899 oplus 119868

1015840

119899= 1

If a single line fault occurs at any point in the parity line theparity output 119874 will also be 1 since if any subexpression in(28) is inverted then 119874 will be 1

63 Online Testing of Single Line Faults in Sequential CircuitsIn our proposedmethod for online testing of single line faultsin sequential circuits we use the technique in [44] for testing

the Toffoli circuits in the (i) Modified Next State Logic andNext State Logic sections together and test the (ii) Feedbacksection and (iii) Output Logic section separately We thenuse our proposed technique for online testing of single linefaults in Fredkin circuits in the Falling-Edge Trigger andResetAsynchronous Load sections together

The online testable version of the reversible sequentialcircuit in Figure 6 is shown in Figure 10 The design of thetestable circuit is described below

(1) The Modified Next State Logic and Next State Logicsections together are a Toffoli circuit We make thiscircuit testable by adding 0-initialized parity input119871119872119873 This portion of the circuit has five active inputs119909 two 1-initialized inputs 1198761 and 1198760 Five CNOTgates are added at the beginning of this portion andanother five CNOT gates are added at the end of thisportion OneCNOT gate and three Toffoli gates in theoriginal circuit are replaced by their correspondingextended versions There are three NOT gates inthe original circuit so an extra NOT gate is addedalong the parity line If any single line fault occursin this section then the parity output 119874119872119873 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 20

(2) The Falling-Edge Trigger and Asynchronous Resetsections together are a Fredkin circuit We make thiscircuit testable by adding 0-initialized parity input119871119879119871This portion of the circuit has eight active inputs119877 119862 1198761+ 1198761 1198760+ 1198760 and two 0-initialized inputsEight CNOT gates are added at the beginning of thisportion and another eight CNOT gates are added atthe end of this portion If any single line fault occursin this section then the parity output 119874119879119871 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 16

(3) The Feedback section of the circuit is a Toffoli circuitWe make this circuit testable by adding 0-initializedparity input 119871119865 This portion of the circuit has fouractive inputs 1198761 1198760 and two 0-initialized inputsThis portion of the circuit is made testable using thetechnique described in Section 61 If any single linefault occurs in this section then the parity output 119874119865will be 1 otherwise it will be 0The overhead quantumcost of this section is 10

(4) The Output Logic section of the circuit is a Toffolicircuit We make this circuit testable by adding 0-initialized parity input 119871119874 This portion of the circuithas two active inputs 119909 and 1198760 This portion of thecircuit is made testable using the technique describedin Section 61 If any single line fault occurs in thissection then the parity output 119874119874 will be 1 otherwiseit will be 0The overhead quantum cost of this sectionis 5

(5) Multiple line faults in different sections can bedetected simultaneously Therefore from the parityoutputs fault sections can be located

VLSI Design 11

Table 7 Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks both before and after addinggates for testability

Filename Inputs Outputs States Total before testability Total after testabilityGC QC Number of lines GC QC Number of lines increase in QC

bbara 4 2 10 46 1096 14 116 1242 18 1330bbsse 7 7 16 99 1361 22 185 1629 26 1970bbtas 2 2 6 21 203 10 73 285 14 4040beecount 3 4 7 53 577 13 111 729 17 2630cse 7 7 16 137 2922 22 223 3266 26 1180dk14 3 5 7 104 973 14 164 1229 18 2630dk512 3 5 4 58 491 12 104 645 16 3140donfile 2 1 24 67 877 13 145 1069 17 2190ex1 9 19 20 355 3979 38 483 4797 42 2060ex2 2 2 19 97 1924 14 177 2178 18 1320ex3 2 2 10 51 715 12 117 867 16 2130ex4 6 9 14 74 618 23 162 838 27 3560ex5 2 2 9 43 631 12 109 767 16 2160ex7 2 2 10 48 680 12 114 826 16 2150keyb 7 2 19 110 4946 19 200 5236 23 590lion9 2 1 9 34 505 11 98 621 15 2300lion 2 1 4 15 79 7 51 137 11 7340planet1 7 19 48 646 4763 38 784 6169 42 2950planet 7 19 48 646 4763 38 784 6169 42 2950s1a 8 6 20 97 3668 24 197 3942 28 750s1 8 6 20 197 3864 24 297 4338 28 1230s8 4 1 5 36 1036 11 90 1150 15 1100sand 11 9 32 288 4941 30 400 5609 34 1350shiftreg 1 1 8 17 29 8 65 99 12 24140sse 7 7 16 98 1378 22 184 1644 26 1930styr 9 10 30 338 6553 29 448 7319 33 1170tav 4 4 4 23 403 12 69 487 16 2080tbk 6 3 32 110 3621 19 200 3911 23 800train11 2 1 11 47 742 11 111 884 15 1910train4 2 1 4 18 103 7 54 167 11 6210

The total overhead quantum cost of the circuit in Figure 10 is20 + 16 + 10 + 5 = 51 The quantum cost of the original circuitin Figure 6 is 53Therefore the quantum cost overhead of thetestable circuit is only 9623

7 Experimental Results

The process for designing the sequential reversible circuitand adding the gates for testability was applied to severalsequential benchmarks from theMCNC suite of benchmarks[48] As shown in Table 7 the additional circuitry requiredfor making the sequential reversible circuit testable adds anaverage of 30 overhead in terms of quantum cost Thehighest percentage overhead occurs for the smallest circuitsthis is a result of needing to copy the input and output linesseveral times In larger circuits the percentage overhead issignificantly lower

8 Conclusion

In this work an improved synthesis approach for sequentialreversible circuits is presented Three design examples aredemonstrated including an arbitrary sequential circuit with2-bit states 1-bit input and 1-bit output (Figure 4) a four-bitfalling-edge triggered updown counter with asynchronousload and a four-bit falling-edge triggered universal registerare shown We compare the quantum cost and the ancillainputs of the three designs with both the replacement designtechnique and the direct design technique reported in [26]The new design of the sequential circuit in Figure 4 saves4479 and 3977 in quantum cost and 6667 and 3333in ancilla inputs as compared to the replacement design anddirect design in [26] respectively The new counter designsaves 2128 in quantumcostwith the samenumber of ancillainputs as compared to the design in [26] The new registerdesign saves 6636 in quantum cost and 2222 in ancilla

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

VLSI Design 7

Q0

Q1

Q2

Q3

0

0

0

0

1

0

C C

0

0

Q3

Q2

Q1

Q0

Q0lowast

Q1lowast

Q2lowast

Q3lowast Q3

+Q2

+Q1

+Q0

M

Q2

Q1

Q0

Q3

M

L LModified next state logic

Nextstatelogic

Falling-edgetrigger Asynchronous load Feedback

D0

D1

D2

D3

+

Figure 7 Reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load [43]

design is similar to that of the previous example (Example 1)The operation of the circuit is discussed below

(1) C = 1 and L = 1 Asynchronous Load The data inputs 11986331198632 1198631 and 1198630 are loaded to the present state outputs 11987631198762 1198761 and 1198760 (respectively) through the controlled swapgates that make up the Asynchronous Load section of thecircuit After loading the input data we set 119871 = 0 to maintainthe present state output

(2) M = 0 Modified Next State Generation for Up CountThe six 119872-controlled CNOT gates of the Modified NextState Logic section will not modify the logic values of theirtargets and the fed-back state values 1198763 1198762 1198761 and 1198760remain unchanged These fed-back state values are used inthe Modified Next State Logic section to generate modifiednext states 1198763lowast 1198762lowast 1198761lowast and 1198760lowast (see (8) to (11))

(3) M = 1 Modified Next State Generation for Down CountThe first three CNOT gates controlled by 119872 complementthe fed-back present states 1198763 1198762 1198761 and 1198760 Thesecomplemented values are used in the Modified Next StateLogic section to generatemodified next states1198763lowast1198762lowast1198761lowastand 1198760lowast (see (12) to (15)) The last three CNOT gates ofthe Modified Next State Logic section restore the fed-backpresent states for use in the Next State Logic section of thecircuit

The circuit in Figure 7 has a quantum cost of 74 andrequires 8 ancilla inputs The complexity of our design is

Table 4 Comparison of reversible realization of the four-bit falling-edge triggered updown counter with asynchronous load with thatin [26] (including data previously presented in [43])

Quantum cost Ancilla inputDesign of [26] 94 8Present design 74 8 improvement overdesign of [26] 2128 0

compared with that in [26] as shown in Table 4 From thetable we see that the present design saves quantum cost withno increase of ancilla inputs

53 Example 3 4-Bit Universal Register In this section weillustrate the synthesis process for a four-bit falling-edgetriggered universal register The truth table representing thenext states and the modified next states is shown in Table 5where 119863119877 is the serial data input The modified next states1198763lowast1198762lowast1198761lowast and1198760lowast are minimized as ESOP expressionsas follows

1198763lowast = 119863119877 oplus 1198763 (16)

1198762lowast = 1198763 oplus 1198762 (17)

1198761lowast = 1198762 oplus 1198761 (18)

1198760lowast = 1198761 oplus 1198760 (19)

8 VLSI Design

Table 5 Truth table representing the next states and the modifiednext states of a four-bit serial-in serial-out right-shift register [43]

Present state Next state Modified next state1198631198771198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

00000 0000 000000001 0000 000100010 0001 001100011 0001 001000100 0010 011000101 0010 011100110 0011 010100111 0011 010001000 0100 110001001 0100 110101010 0101 111101011 0101 111001100 0110 101001101 0110 101101110 0111 100101111 0111 100010000 1000 100010001 1000 100110010 1001 101110011 1001 101010100 1010 111010101 1010 111110110 1011 110110111 1011 110011000 1100 010011001 1100 010111010 1101 011111011 1101 011011100 1110 001011101 1110 001111110 1111 000111111 1111 0000

Using (2) the next states corresponding to (16) to (19) can bedetermined as follows

1198763+ = 119863119877 oplus 1198763 oplus 1198763 = 119863119877 (20)

1198762+ = 1198763 oplus 1198762 oplus 1198762 = 1198763 (21)

1198761+ = 1198762 oplus 1198761 oplus 1198761 = 1198762 (22)

1198760+ = 1198761 oplus 1198760 oplus 1198760 = 1198761 (23)

Similarly the next states of a four-bit serial-in serial-out left-shift register can be determined as follows where 119863119871 is theserial data input

1198763+ = 1198762 (24)

1198762+ = 1198761 (25)

1198761+ = 1198760 (26)

1198760+ = 119863119871 (27)

Equations (20) to (27) are implemented with reversible gatesto build the circuit shown in Figure 8 Multiplexing is neededfor implementing right-shift and left-shift between 119863119877 and1198762 for 1198763+ between 1198763 and 1198761 for 1198762+ between 1198762and 1198760 for 1198761+ and between 1198761 and 119863119871 for 1198760+ This isimplemented using four controlled swap gates controlled bythe shift direction control input 119872 in the Next State Logicsection of the circuit Implementations of the other sectionsare similar to those in Figure 7 The different modes ofoperations are explained below

(1) C = 1 and L = 0 Serial-In Serial-Out Register If119872 = 0expressions (20) to (23) are implemented by the Next StateLogic section and data is shifted right If119872 = 1 expressions(24) to (27) are implemented and data is shifted left When119862 is changed to 0 the next states are passed to the presentstate outputs through the Asynchronous Load section of thecircuit

(2) Serial-In Parallel-Out Register The operation is similar tostep (1) and the present state outputs are taken in parallel

(3) C = 1 and L = 1 Parallel-In Parallel-Out Register Theparallel input values 1198633 1198632 1198631 and 1198630 are loaded to thepresent state outputs through theAsynchronous Load sectionby setting 119871 = 1 and then changing to 119871 = 0 Outputs aretaken in parallel

(4) Parallel-In Serial-Out Register The asynchronous loadoperation is similar to step (3) After setting 119871 = 0 if 119862 ischanged to 0 the states will be shifted to either right or leftbased on the value of119872

The quantum cost of the circuit in Figure 8 is 74 and14 ancilla inputs are required The circuit complexity iscompared with that of previous work in Table 6 From thetable we see that the present design saves both quantum costand ancilla inputs as compared to the replacement design in[40] It is to be noted that in [40] the number of ancilla inputsis not mentioned We count only the 0-initialized workinginputs as ancilla inputs and do not include a large number ofcontrol inputs as ancilla inputs The present design also saveson quantum cost as compared to the direct design in [26] butrequires slightly more ancilla inputs

6 Online Testable Design ofSequential Circuits

In this section we introduce our proposed technique foronline testing of single line faults in sequential circuit Wefocus only on single line faults because some of the missingcontrol fault and missing gate fault situations can be treatedas single line faults For example if a missing control faultinverts the original target output of the gate then that faultcan be treated as a single line fault at the target output of thegate Similarly if a gate produces an inverted output at the

VLSI Design 9

Q0

Q1

Q2

Q3

0

0

0

0

0

0

C C

0

0

Next state logic triggerFalling-edge

Feedback

Q2

Q1

Q0

+Q3

+Q2

+Q1

+Q0

M M

L LAsynchronous load

0

DR

0

0

Q3

DL

0

0

0

D0

D1

D2

D3

Figure 8 Reversible realization of the four-bit falling-edge triggered universal register [43]

Table 6 Comparison of reversible realization of the four-bit falling-edge triggered universal register with that of the replacement designin [40] and the direct design in [26]

Quantum cost Ancilla input

Replacement design [40] 220 18

Direct design [26] 112 12

Present design 74 14 improvement overreplacement design [40]

6636 2222

improvement overdirect design [26]

3393 minus1667

target then the missing gate will not produce that inversionand this condition can be treated as a single line fault atthat position Thus online detection of single line faults alsodetects some missing control and missing gate faults

61 Online Testing of Single Line Fault in Toffoli Circuits AToffoli circuit is a cascade of NOT CNOT and Toffoli gatesIn [44] a method for online detection of single line fault inToffoli circuits is presented The method in [44] is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) All CNOT and Toffoli gates of the given circuit arereplaced by their corresponding extended versions(EFGs and ETGs respectively) The second target ofall gates is the parity line 119871

(4) The NOT gates in the given circuit are retained If thenumber of NOT gates in the given circuit is odd thenan extra NOT gate is added at the end of the parityline 119871

10 VLSI Design

L = 0 O

I1I2I3

O1

O2

O3

Figure 9 Online testing of a single line fault in a Fredkin circuit

(5) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(6) If the circuit is fault free then the parity output will be0 otherwise it will be 1

62 Online Testing of Single Line Faults in Fredkin CircuitsA Fredkin circuit is a cascade consisting of only Fredkin(controlled swap) gates To our knowledge there is noexisting work on offline or online testing of Fredkin circuitsWe propose here a technique for online testing of single linefaults in Fredkin circuits The procedure is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(4) If the circuit is fault free then the parity output will be0 otherwise it will be 1

A simple example of the above technique is shown in Figure 9In a controlled swap gate the target inputs are either swappedor not swapped depending on the control value Thus theoutputs of a controlled swap gate are a permutation ofthe inputs Similarly the outputs of a Fredkin circuit are apermutation of the inputs In Figure 9 the parity output iscomputed as

119874 = (1198681 oplus 1198682 oplus 1198683) oplus (1198681 oplus 1198682 oplus 1198683) (28)

If there is no single line fault in the circuit then the parityoutput119874 of (28) will be 0 since each pair (input output) willbe canceled If any single line fault occurs anywhere in thecircuit then any of 119868119899 where 119899 isin 1 2 3will be inverted at theoutput Thus the parity output 119874 will be 1 since 119868119899 oplus 119868

1015840

119899= 1

If a single line fault occurs at any point in the parity line theparity output 119874 will also be 1 since if any subexpression in(28) is inverted then 119874 will be 1

63 Online Testing of Single Line Faults in Sequential CircuitsIn our proposedmethod for online testing of single line faultsin sequential circuits we use the technique in [44] for testing

the Toffoli circuits in the (i) Modified Next State Logic andNext State Logic sections together and test the (ii) Feedbacksection and (iii) Output Logic section separately We thenuse our proposed technique for online testing of single linefaults in Fredkin circuits in the Falling-Edge Trigger andResetAsynchronous Load sections together

The online testable version of the reversible sequentialcircuit in Figure 6 is shown in Figure 10 The design of thetestable circuit is described below

(1) The Modified Next State Logic and Next State Logicsections together are a Toffoli circuit We make thiscircuit testable by adding 0-initialized parity input119871119872119873 This portion of the circuit has five active inputs119909 two 1-initialized inputs 1198761 and 1198760 Five CNOTgates are added at the beginning of this portion andanother five CNOT gates are added at the end of thisportion OneCNOT gate and three Toffoli gates in theoriginal circuit are replaced by their correspondingextended versions There are three NOT gates inthe original circuit so an extra NOT gate is addedalong the parity line If any single line fault occursin this section then the parity output 119874119872119873 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 20

(2) The Falling-Edge Trigger and Asynchronous Resetsections together are a Fredkin circuit We make thiscircuit testable by adding 0-initialized parity input119871119879119871This portion of the circuit has eight active inputs119877 119862 1198761+ 1198761 1198760+ 1198760 and two 0-initialized inputsEight CNOT gates are added at the beginning of thisportion and another eight CNOT gates are added atthe end of this portion If any single line fault occursin this section then the parity output 119874119879119871 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 16

(3) The Feedback section of the circuit is a Toffoli circuitWe make this circuit testable by adding 0-initializedparity input 119871119865 This portion of the circuit has fouractive inputs 1198761 1198760 and two 0-initialized inputsThis portion of the circuit is made testable using thetechnique described in Section 61 If any single linefault occurs in this section then the parity output 119874119865will be 1 otherwise it will be 0The overhead quantumcost of this section is 10

(4) The Output Logic section of the circuit is a Toffolicircuit We make this circuit testable by adding 0-initialized parity input 119871119874 This portion of the circuithas two active inputs 119909 and 1198760 This portion of thecircuit is made testable using the technique describedin Section 61 If any single line fault occurs in thissection then the parity output 119874119874 will be 1 otherwiseit will be 0The overhead quantum cost of this sectionis 5

(5) Multiple line faults in different sections can bedetected simultaneously Therefore from the parityoutputs fault sections can be located

VLSI Design 11

Table 7 Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks both before and after addinggates for testability

Filename Inputs Outputs States Total before testability Total after testabilityGC QC Number of lines GC QC Number of lines increase in QC

bbara 4 2 10 46 1096 14 116 1242 18 1330bbsse 7 7 16 99 1361 22 185 1629 26 1970bbtas 2 2 6 21 203 10 73 285 14 4040beecount 3 4 7 53 577 13 111 729 17 2630cse 7 7 16 137 2922 22 223 3266 26 1180dk14 3 5 7 104 973 14 164 1229 18 2630dk512 3 5 4 58 491 12 104 645 16 3140donfile 2 1 24 67 877 13 145 1069 17 2190ex1 9 19 20 355 3979 38 483 4797 42 2060ex2 2 2 19 97 1924 14 177 2178 18 1320ex3 2 2 10 51 715 12 117 867 16 2130ex4 6 9 14 74 618 23 162 838 27 3560ex5 2 2 9 43 631 12 109 767 16 2160ex7 2 2 10 48 680 12 114 826 16 2150keyb 7 2 19 110 4946 19 200 5236 23 590lion9 2 1 9 34 505 11 98 621 15 2300lion 2 1 4 15 79 7 51 137 11 7340planet1 7 19 48 646 4763 38 784 6169 42 2950planet 7 19 48 646 4763 38 784 6169 42 2950s1a 8 6 20 97 3668 24 197 3942 28 750s1 8 6 20 197 3864 24 297 4338 28 1230s8 4 1 5 36 1036 11 90 1150 15 1100sand 11 9 32 288 4941 30 400 5609 34 1350shiftreg 1 1 8 17 29 8 65 99 12 24140sse 7 7 16 98 1378 22 184 1644 26 1930styr 9 10 30 338 6553 29 448 7319 33 1170tav 4 4 4 23 403 12 69 487 16 2080tbk 6 3 32 110 3621 19 200 3911 23 800train11 2 1 11 47 742 11 111 884 15 1910train4 2 1 4 18 103 7 54 167 11 6210

The total overhead quantum cost of the circuit in Figure 10 is20 + 16 + 10 + 5 = 51 The quantum cost of the original circuitin Figure 6 is 53Therefore the quantum cost overhead of thetestable circuit is only 9623

7 Experimental Results

The process for designing the sequential reversible circuitand adding the gates for testability was applied to severalsequential benchmarks from theMCNC suite of benchmarks[48] As shown in Table 7 the additional circuitry requiredfor making the sequential reversible circuit testable adds anaverage of 30 overhead in terms of quantum cost Thehighest percentage overhead occurs for the smallest circuitsthis is a result of needing to copy the input and output linesseveral times In larger circuits the percentage overhead issignificantly lower

8 Conclusion

In this work an improved synthesis approach for sequentialreversible circuits is presented Three design examples aredemonstrated including an arbitrary sequential circuit with2-bit states 1-bit input and 1-bit output (Figure 4) a four-bitfalling-edge triggered updown counter with asynchronousload and a four-bit falling-edge triggered universal registerare shown We compare the quantum cost and the ancillainputs of the three designs with both the replacement designtechnique and the direct design technique reported in [26]The new design of the sequential circuit in Figure 4 saves4479 and 3977 in quantum cost and 6667 and 3333in ancilla inputs as compared to the replacement design anddirect design in [26] respectively The new counter designsaves 2128 in quantumcostwith the samenumber of ancillainputs as compared to the design in [26] The new registerdesign saves 6636 in quantum cost and 2222 in ancilla

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

8 VLSI Design

Table 5 Truth table representing the next states and the modifiednext states of a four-bit serial-in serial-out right-shift register [43]

Present state Next state Modified next state1198631198771198763119876211987611198760 1198763+1198762+1198761+1198760 1198763lowast1198762lowast1198761lowast1198760lowast

00000 0000 000000001 0000 000100010 0001 001100011 0001 001000100 0010 011000101 0010 011100110 0011 010100111 0011 010001000 0100 110001001 0100 110101010 0101 111101011 0101 111001100 0110 101001101 0110 101101110 0111 100101111 0111 100010000 1000 100010001 1000 100110010 1001 101110011 1001 101010100 1010 111010101 1010 111110110 1011 110110111 1011 110011000 1100 010011001 1100 010111010 1101 011111011 1101 011011100 1110 001011101 1110 001111110 1111 000111111 1111 0000

Using (2) the next states corresponding to (16) to (19) can bedetermined as follows

1198763+ = 119863119877 oplus 1198763 oplus 1198763 = 119863119877 (20)

1198762+ = 1198763 oplus 1198762 oplus 1198762 = 1198763 (21)

1198761+ = 1198762 oplus 1198761 oplus 1198761 = 1198762 (22)

1198760+ = 1198761 oplus 1198760 oplus 1198760 = 1198761 (23)

Similarly the next states of a four-bit serial-in serial-out left-shift register can be determined as follows where 119863119871 is theserial data input

1198763+ = 1198762 (24)

1198762+ = 1198761 (25)

1198761+ = 1198760 (26)

1198760+ = 119863119871 (27)

Equations (20) to (27) are implemented with reversible gatesto build the circuit shown in Figure 8 Multiplexing is neededfor implementing right-shift and left-shift between 119863119877 and1198762 for 1198763+ between 1198763 and 1198761 for 1198762+ between 1198762and 1198760 for 1198761+ and between 1198761 and 119863119871 for 1198760+ This isimplemented using four controlled swap gates controlled bythe shift direction control input 119872 in the Next State Logicsection of the circuit Implementations of the other sectionsare similar to those in Figure 7 The different modes ofoperations are explained below

(1) C = 1 and L = 0 Serial-In Serial-Out Register If119872 = 0expressions (20) to (23) are implemented by the Next StateLogic section and data is shifted right If119872 = 1 expressions(24) to (27) are implemented and data is shifted left When119862 is changed to 0 the next states are passed to the presentstate outputs through the Asynchronous Load section of thecircuit

(2) Serial-In Parallel-Out Register The operation is similar tostep (1) and the present state outputs are taken in parallel

(3) C = 1 and L = 1 Parallel-In Parallel-Out Register Theparallel input values 1198633 1198632 1198631 and 1198630 are loaded to thepresent state outputs through theAsynchronous Load sectionby setting 119871 = 1 and then changing to 119871 = 0 Outputs aretaken in parallel

(4) Parallel-In Serial-Out Register The asynchronous loadoperation is similar to step (3) After setting 119871 = 0 if 119862 ischanged to 0 the states will be shifted to either right or leftbased on the value of119872

The quantum cost of the circuit in Figure 8 is 74 and14 ancilla inputs are required The circuit complexity iscompared with that of previous work in Table 6 From thetable we see that the present design saves both quantum costand ancilla inputs as compared to the replacement design in[40] It is to be noted that in [40] the number of ancilla inputsis not mentioned We count only the 0-initialized workinginputs as ancilla inputs and do not include a large number ofcontrol inputs as ancilla inputs The present design also saveson quantum cost as compared to the direct design in [26] butrequires slightly more ancilla inputs

6 Online Testable Design ofSequential Circuits

In this section we introduce our proposed technique foronline testing of single line faults in sequential circuit Wefocus only on single line faults because some of the missingcontrol fault and missing gate fault situations can be treatedas single line faults For example if a missing control faultinverts the original target output of the gate then that faultcan be treated as a single line fault at the target output of thegate Similarly if a gate produces an inverted output at the

VLSI Design 9

Q0

Q1

Q2

Q3

0

0

0

0

0

0

C C

0

0

Next state logic triggerFalling-edge

Feedback

Q2

Q1

Q0

+Q3

+Q2

+Q1

+Q0

M M

L LAsynchronous load

0

DR

0

0

Q3

DL

0

0

0

D0

D1

D2

D3

Figure 8 Reversible realization of the four-bit falling-edge triggered universal register [43]

Table 6 Comparison of reversible realization of the four-bit falling-edge triggered universal register with that of the replacement designin [40] and the direct design in [26]

Quantum cost Ancilla input

Replacement design [40] 220 18

Direct design [26] 112 12

Present design 74 14 improvement overreplacement design [40]

6636 2222

improvement overdirect design [26]

3393 minus1667

target then the missing gate will not produce that inversionand this condition can be treated as a single line fault atthat position Thus online detection of single line faults alsodetects some missing control and missing gate faults

61 Online Testing of Single Line Fault in Toffoli Circuits AToffoli circuit is a cascade of NOT CNOT and Toffoli gatesIn [44] a method for online detection of single line fault inToffoli circuits is presented The method in [44] is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) All CNOT and Toffoli gates of the given circuit arereplaced by their corresponding extended versions(EFGs and ETGs respectively) The second target ofall gates is the parity line 119871

(4) The NOT gates in the given circuit are retained If thenumber of NOT gates in the given circuit is odd thenan extra NOT gate is added at the end of the parityline 119871

10 VLSI Design

L = 0 O

I1I2I3

O1

O2

O3

Figure 9 Online testing of a single line fault in a Fredkin circuit

(5) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(6) If the circuit is fault free then the parity output will be0 otherwise it will be 1

62 Online Testing of Single Line Faults in Fredkin CircuitsA Fredkin circuit is a cascade consisting of only Fredkin(controlled swap) gates To our knowledge there is noexisting work on offline or online testing of Fredkin circuitsWe propose here a technique for online testing of single linefaults in Fredkin circuits The procedure is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(4) If the circuit is fault free then the parity output will be0 otherwise it will be 1

A simple example of the above technique is shown in Figure 9In a controlled swap gate the target inputs are either swappedor not swapped depending on the control value Thus theoutputs of a controlled swap gate are a permutation ofthe inputs Similarly the outputs of a Fredkin circuit are apermutation of the inputs In Figure 9 the parity output iscomputed as

119874 = (1198681 oplus 1198682 oplus 1198683) oplus (1198681 oplus 1198682 oplus 1198683) (28)

If there is no single line fault in the circuit then the parityoutput119874 of (28) will be 0 since each pair (input output) willbe canceled If any single line fault occurs anywhere in thecircuit then any of 119868119899 where 119899 isin 1 2 3will be inverted at theoutput Thus the parity output 119874 will be 1 since 119868119899 oplus 119868

1015840

119899= 1

If a single line fault occurs at any point in the parity line theparity output 119874 will also be 1 since if any subexpression in(28) is inverted then 119874 will be 1

63 Online Testing of Single Line Faults in Sequential CircuitsIn our proposedmethod for online testing of single line faultsin sequential circuits we use the technique in [44] for testing

the Toffoli circuits in the (i) Modified Next State Logic andNext State Logic sections together and test the (ii) Feedbacksection and (iii) Output Logic section separately We thenuse our proposed technique for online testing of single linefaults in Fredkin circuits in the Falling-Edge Trigger andResetAsynchronous Load sections together

The online testable version of the reversible sequentialcircuit in Figure 6 is shown in Figure 10 The design of thetestable circuit is described below

(1) The Modified Next State Logic and Next State Logicsections together are a Toffoli circuit We make thiscircuit testable by adding 0-initialized parity input119871119872119873 This portion of the circuit has five active inputs119909 two 1-initialized inputs 1198761 and 1198760 Five CNOTgates are added at the beginning of this portion andanother five CNOT gates are added at the end of thisportion OneCNOT gate and three Toffoli gates in theoriginal circuit are replaced by their correspondingextended versions There are three NOT gates inthe original circuit so an extra NOT gate is addedalong the parity line If any single line fault occursin this section then the parity output 119874119872119873 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 20

(2) The Falling-Edge Trigger and Asynchronous Resetsections together are a Fredkin circuit We make thiscircuit testable by adding 0-initialized parity input119871119879119871This portion of the circuit has eight active inputs119877 119862 1198761+ 1198761 1198760+ 1198760 and two 0-initialized inputsEight CNOT gates are added at the beginning of thisportion and another eight CNOT gates are added atthe end of this portion If any single line fault occursin this section then the parity output 119874119879119871 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 16

(3) The Feedback section of the circuit is a Toffoli circuitWe make this circuit testable by adding 0-initializedparity input 119871119865 This portion of the circuit has fouractive inputs 1198761 1198760 and two 0-initialized inputsThis portion of the circuit is made testable using thetechnique described in Section 61 If any single linefault occurs in this section then the parity output 119874119865will be 1 otherwise it will be 0The overhead quantumcost of this section is 10

(4) The Output Logic section of the circuit is a Toffolicircuit We make this circuit testable by adding 0-initialized parity input 119871119874 This portion of the circuithas two active inputs 119909 and 1198760 This portion of thecircuit is made testable using the technique describedin Section 61 If any single line fault occurs in thissection then the parity output 119874119874 will be 1 otherwiseit will be 0The overhead quantum cost of this sectionis 5

(5) Multiple line faults in different sections can bedetected simultaneously Therefore from the parityoutputs fault sections can be located

VLSI Design 11

Table 7 Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks both before and after addinggates for testability

Filename Inputs Outputs States Total before testability Total after testabilityGC QC Number of lines GC QC Number of lines increase in QC

bbara 4 2 10 46 1096 14 116 1242 18 1330bbsse 7 7 16 99 1361 22 185 1629 26 1970bbtas 2 2 6 21 203 10 73 285 14 4040beecount 3 4 7 53 577 13 111 729 17 2630cse 7 7 16 137 2922 22 223 3266 26 1180dk14 3 5 7 104 973 14 164 1229 18 2630dk512 3 5 4 58 491 12 104 645 16 3140donfile 2 1 24 67 877 13 145 1069 17 2190ex1 9 19 20 355 3979 38 483 4797 42 2060ex2 2 2 19 97 1924 14 177 2178 18 1320ex3 2 2 10 51 715 12 117 867 16 2130ex4 6 9 14 74 618 23 162 838 27 3560ex5 2 2 9 43 631 12 109 767 16 2160ex7 2 2 10 48 680 12 114 826 16 2150keyb 7 2 19 110 4946 19 200 5236 23 590lion9 2 1 9 34 505 11 98 621 15 2300lion 2 1 4 15 79 7 51 137 11 7340planet1 7 19 48 646 4763 38 784 6169 42 2950planet 7 19 48 646 4763 38 784 6169 42 2950s1a 8 6 20 97 3668 24 197 3942 28 750s1 8 6 20 197 3864 24 297 4338 28 1230s8 4 1 5 36 1036 11 90 1150 15 1100sand 11 9 32 288 4941 30 400 5609 34 1350shiftreg 1 1 8 17 29 8 65 99 12 24140sse 7 7 16 98 1378 22 184 1644 26 1930styr 9 10 30 338 6553 29 448 7319 33 1170tav 4 4 4 23 403 12 69 487 16 2080tbk 6 3 32 110 3621 19 200 3911 23 800train11 2 1 11 47 742 11 111 884 15 1910train4 2 1 4 18 103 7 54 167 11 6210

The total overhead quantum cost of the circuit in Figure 10 is20 + 16 + 10 + 5 = 51 The quantum cost of the original circuitin Figure 6 is 53Therefore the quantum cost overhead of thetestable circuit is only 9623

7 Experimental Results

The process for designing the sequential reversible circuitand adding the gates for testability was applied to severalsequential benchmarks from theMCNC suite of benchmarks[48] As shown in Table 7 the additional circuitry requiredfor making the sequential reversible circuit testable adds anaverage of 30 overhead in terms of quantum cost Thehighest percentage overhead occurs for the smallest circuitsthis is a result of needing to copy the input and output linesseveral times In larger circuits the percentage overhead issignificantly lower

8 Conclusion

In this work an improved synthesis approach for sequentialreversible circuits is presented Three design examples aredemonstrated including an arbitrary sequential circuit with2-bit states 1-bit input and 1-bit output (Figure 4) a four-bitfalling-edge triggered updown counter with asynchronousload and a four-bit falling-edge triggered universal registerare shown We compare the quantum cost and the ancillainputs of the three designs with both the replacement designtechnique and the direct design technique reported in [26]The new design of the sequential circuit in Figure 4 saves4479 and 3977 in quantum cost and 6667 and 3333in ancilla inputs as compared to the replacement design anddirect design in [26] respectively The new counter designsaves 2128 in quantumcostwith the samenumber of ancillainputs as compared to the design in [26] The new registerdesign saves 6636 in quantum cost and 2222 in ancilla

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

VLSI Design 9

Q0

Q1

Q2

Q3

0

0

0

0

0

0

C C

0

0

Next state logic triggerFalling-edge

Feedback

Q2

Q1

Q0

+Q3

+Q2

+Q1

+Q0

M M

L LAsynchronous load

0

DR

0

0

Q3

DL

0

0

0

D0

D1

D2

D3

Figure 8 Reversible realization of the four-bit falling-edge triggered universal register [43]

Table 6 Comparison of reversible realization of the four-bit falling-edge triggered universal register with that of the replacement designin [40] and the direct design in [26]

Quantum cost Ancilla input

Replacement design [40] 220 18

Direct design [26] 112 12

Present design 74 14 improvement overreplacement design [40]

6636 2222

improvement overdirect design [26]

3393 minus1667

target then the missing gate will not produce that inversionand this condition can be treated as a single line fault atthat position Thus online detection of single line faults alsodetects some missing control and missing gate faults

61 Online Testing of Single Line Fault in Toffoli Circuits AToffoli circuit is a cascade of NOT CNOT and Toffoli gatesIn [44] a method for online detection of single line fault inToffoli circuits is presented The method in [44] is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) All CNOT and Toffoli gates of the given circuit arereplaced by their corresponding extended versions(EFGs and ETGs respectively) The second target ofall gates is the parity line 119871

(4) The NOT gates in the given circuit are retained If thenumber of NOT gates in the given circuit is odd thenan extra NOT gate is added at the end of the parityline 119871

10 VLSI Design

L = 0 O

I1I2I3

O1

O2

O3

Figure 9 Online testing of a single line fault in a Fredkin circuit

(5) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(6) If the circuit is fault free then the parity output will be0 otherwise it will be 1

62 Online Testing of Single Line Faults in Fredkin CircuitsA Fredkin circuit is a cascade consisting of only Fredkin(controlled swap) gates To our knowledge there is noexisting work on offline or online testing of Fredkin circuitsWe propose here a technique for online testing of single linefaults in Fredkin circuits The procedure is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(4) If the circuit is fault free then the parity output will be0 otherwise it will be 1

A simple example of the above technique is shown in Figure 9In a controlled swap gate the target inputs are either swappedor not swapped depending on the control value Thus theoutputs of a controlled swap gate are a permutation ofthe inputs Similarly the outputs of a Fredkin circuit are apermutation of the inputs In Figure 9 the parity output iscomputed as

119874 = (1198681 oplus 1198682 oplus 1198683) oplus (1198681 oplus 1198682 oplus 1198683) (28)

If there is no single line fault in the circuit then the parityoutput119874 of (28) will be 0 since each pair (input output) willbe canceled If any single line fault occurs anywhere in thecircuit then any of 119868119899 where 119899 isin 1 2 3will be inverted at theoutput Thus the parity output 119874 will be 1 since 119868119899 oplus 119868

1015840

119899= 1

If a single line fault occurs at any point in the parity line theparity output 119874 will also be 1 since if any subexpression in(28) is inverted then 119874 will be 1

63 Online Testing of Single Line Faults in Sequential CircuitsIn our proposedmethod for online testing of single line faultsin sequential circuits we use the technique in [44] for testing

the Toffoli circuits in the (i) Modified Next State Logic andNext State Logic sections together and test the (ii) Feedbacksection and (iii) Output Logic section separately We thenuse our proposed technique for online testing of single linefaults in Fredkin circuits in the Falling-Edge Trigger andResetAsynchronous Load sections together

The online testable version of the reversible sequentialcircuit in Figure 6 is shown in Figure 10 The design of thetestable circuit is described below

(1) The Modified Next State Logic and Next State Logicsections together are a Toffoli circuit We make thiscircuit testable by adding 0-initialized parity input119871119872119873 This portion of the circuit has five active inputs119909 two 1-initialized inputs 1198761 and 1198760 Five CNOTgates are added at the beginning of this portion andanother five CNOT gates are added at the end of thisportion OneCNOT gate and three Toffoli gates in theoriginal circuit are replaced by their correspondingextended versions There are three NOT gates inthe original circuit so an extra NOT gate is addedalong the parity line If any single line fault occursin this section then the parity output 119874119872119873 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 20

(2) The Falling-Edge Trigger and Asynchronous Resetsections together are a Fredkin circuit We make thiscircuit testable by adding 0-initialized parity input119871119879119871This portion of the circuit has eight active inputs119877 119862 1198761+ 1198761 1198760+ 1198760 and two 0-initialized inputsEight CNOT gates are added at the beginning of thisportion and another eight CNOT gates are added atthe end of this portion If any single line fault occursin this section then the parity output 119874119879119871 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 16

(3) The Feedback section of the circuit is a Toffoli circuitWe make this circuit testable by adding 0-initializedparity input 119871119865 This portion of the circuit has fouractive inputs 1198761 1198760 and two 0-initialized inputsThis portion of the circuit is made testable using thetechnique described in Section 61 If any single linefault occurs in this section then the parity output 119874119865will be 1 otherwise it will be 0The overhead quantumcost of this section is 10

(4) The Output Logic section of the circuit is a Toffolicircuit We make this circuit testable by adding 0-initialized parity input 119871119874 This portion of the circuithas two active inputs 119909 and 1198760 This portion of thecircuit is made testable using the technique describedin Section 61 If any single line fault occurs in thissection then the parity output 119874119874 will be 1 otherwiseit will be 0The overhead quantum cost of this sectionis 5

(5) Multiple line faults in different sections can bedetected simultaneously Therefore from the parityoutputs fault sections can be located

VLSI Design 11

Table 7 Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks both before and after addinggates for testability

Filename Inputs Outputs States Total before testability Total after testabilityGC QC Number of lines GC QC Number of lines increase in QC

bbara 4 2 10 46 1096 14 116 1242 18 1330bbsse 7 7 16 99 1361 22 185 1629 26 1970bbtas 2 2 6 21 203 10 73 285 14 4040beecount 3 4 7 53 577 13 111 729 17 2630cse 7 7 16 137 2922 22 223 3266 26 1180dk14 3 5 7 104 973 14 164 1229 18 2630dk512 3 5 4 58 491 12 104 645 16 3140donfile 2 1 24 67 877 13 145 1069 17 2190ex1 9 19 20 355 3979 38 483 4797 42 2060ex2 2 2 19 97 1924 14 177 2178 18 1320ex3 2 2 10 51 715 12 117 867 16 2130ex4 6 9 14 74 618 23 162 838 27 3560ex5 2 2 9 43 631 12 109 767 16 2160ex7 2 2 10 48 680 12 114 826 16 2150keyb 7 2 19 110 4946 19 200 5236 23 590lion9 2 1 9 34 505 11 98 621 15 2300lion 2 1 4 15 79 7 51 137 11 7340planet1 7 19 48 646 4763 38 784 6169 42 2950planet 7 19 48 646 4763 38 784 6169 42 2950s1a 8 6 20 97 3668 24 197 3942 28 750s1 8 6 20 197 3864 24 297 4338 28 1230s8 4 1 5 36 1036 11 90 1150 15 1100sand 11 9 32 288 4941 30 400 5609 34 1350shiftreg 1 1 8 17 29 8 65 99 12 24140sse 7 7 16 98 1378 22 184 1644 26 1930styr 9 10 30 338 6553 29 448 7319 33 1170tav 4 4 4 23 403 12 69 487 16 2080tbk 6 3 32 110 3621 19 200 3911 23 800train11 2 1 11 47 742 11 111 884 15 1910train4 2 1 4 18 103 7 54 167 11 6210

The total overhead quantum cost of the circuit in Figure 10 is20 + 16 + 10 + 5 = 51 The quantum cost of the original circuitin Figure 6 is 53Therefore the quantum cost overhead of thetestable circuit is only 9623

7 Experimental Results

The process for designing the sequential reversible circuitand adding the gates for testability was applied to severalsequential benchmarks from theMCNC suite of benchmarks[48] As shown in Table 7 the additional circuitry requiredfor making the sequential reversible circuit testable adds anaverage of 30 overhead in terms of quantum cost Thehighest percentage overhead occurs for the smallest circuitsthis is a result of needing to copy the input and output linesseveral times In larger circuits the percentage overhead issignificantly lower

8 Conclusion

In this work an improved synthesis approach for sequentialreversible circuits is presented Three design examples aredemonstrated including an arbitrary sequential circuit with2-bit states 1-bit input and 1-bit output (Figure 4) a four-bitfalling-edge triggered updown counter with asynchronousload and a four-bit falling-edge triggered universal registerare shown We compare the quantum cost and the ancillainputs of the three designs with both the replacement designtechnique and the direct design technique reported in [26]The new design of the sequential circuit in Figure 4 saves4479 and 3977 in quantum cost and 6667 and 3333in ancilla inputs as compared to the replacement design anddirect design in [26] respectively The new counter designsaves 2128 in quantumcostwith the samenumber of ancillainputs as compared to the design in [26] The new registerdesign saves 6636 in quantum cost and 2222 in ancilla

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

10 VLSI Design

L = 0 O

I1I2I3

O1

O2

O3

Figure 9 Online testing of a single line fault in a Fredkin circuit

(5) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(6) If the circuit is fault free then the parity output will be0 otherwise it will be 1

62 Online Testing of Single Line Faults in Fredkin CircuitsA Fredkin circuit is a cascade consisting of only Fredkin(controlled swap) gates To our knowledge there is noexisting work on offline or online testing of Fredkin circuitsWe propose here a technique for online testing of single linefaults in Fredkin circuits The procedure is as follows

(1) A 0-initialized parity line 119871 is added to the givencircuit

(2) Assume that the given circuit has119901 inputsoutputs Atthe beginning of the circuit 119901CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(3) At the end of the circuit 119901 CNOT gates are addedwhere the controls of the CNOT gates are the 119901 inputlines and the target of all the CNOT gates is the parityline 119871

(4) If the circuit is fault free then the parity output will be0 otherwise it will be 1

A simple example of the above technique is shown in Figure 9In a controlled swap gate the target inputs are either swappedor not swapped depending on the control value Thus theoutputs of a controlled swap gate are a permutation ofthe inputs Similarly the outputs of a Fredkin circuit are apermutation of the inputs In Figure 9 the parity output iscomputed as

119874 = (1198681 oplus 1198682 oplus 1198683) oplus (1198681 oplus 1198682 oplus 1198683) (28)

If there is no single line fault in the circuit then the parityoutput119874 of (28) will be 0 since each pair (input output) willbe canceled If any single line fault occurs anywhere in thecircuit then any of 119868119899 where 119899 isin 1 2 3will be inverted at theoutput Thus the parity output 119874 will be 1 since 119868119899 oplus 119868

1015840

119899= 1

If a single line fault occurs at any point in the parity line theparity output 119874 will also be 1 since if any subexpression in(28) is inverted then 119874 will be 1

63 Online Testing of Single Line Faults in Sequential CircuitsIn our proposedmethod for online testing of single line faultsin sequential circuits we use the technique in [44] for testing

the Toffoli circuits in the (i) Modified Next State Logic andNext State Logic sections together and test the (ii) Feedbacksection and (iii) Output Logic section separately We thenuse our proposed technique for online testing of single linefaults in Fredkin circuits in the Falling-Edge Trigger andResetAsynchronous Load sections together

The online testable version of the reversible sequentialcircuit in Figure 6 is shown in Figure 10 The design of thetestable circuit is described below

(1) The Modified Next State Logic and Next State Logicsections together are a Toffoli circuit We make thiscircuit testable by adding 0-initialized parity input119871119872119873 This portion of the circuit has five active inputs119909 two 1-initialized inputs 1198761 and 1198760 Five CNOTgates are added at the beginning of this portion andanother five CNOT gates are added at the end of thisportion OneCNOT gate and three Toffoli gates in theoriginal circuit are replaced by their correspondingextended versions There are three NOT gates inthe original circuit so an extra NOT gate is addedalong the parity line If any single line fault occursin this section then the parity output 119874119872119873 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 20

(2) The Falling-Edge Trigger and Asynchronous Resetsections together are a Fredkin circuit We make thiscircuit testable by adding 0-initialized parity input119871119879119871This portion of the circuit has eight active inputs119877 119862 1198761+ 1198761 1198760+ 1198760 and two 0-initialized inputsEight CNOT gates are added at the beginning of thisportion and another eight CNOT gates are added atthe end of this portion If any single line fault occursin this section then the parity output 119874119879119871 will be 1otherwise it will be 0 The overhead quantum cost ofthis section is 16

(3) The Feedback section of the circuit is a Toffoli circuitWe make this circuit testable by adding 0-initializedparity input 119871119865 This portion of the circuit has fouractive inputs 1198761 1198760 and two 0-initialized inputsThis portion of the circuit is made testable using thetechnique described in Section 61 If any single linefault occurs in this section then the parity output 119874119865will be 1 otherwise it will be 0The overhead quantumcost of this section is 10

(4) The Output Logic section of the circuit is a Toffolicircuit We make this circuit testable by adding 0-initialized parity input 119871119874 This portion of the circuithas two active inputs 119909 and 1198760 This portion of thecircuit is made testable using the technique describedin Section 61 If any single line fault occurs in thissection then the parity output 119874119874 will be 1 otherwiseit will be 0The overhead quantum cost of this sectionis 5

(5) Multiple line faults in different sections can bedetected simultaneously Therefore from the parityoutputs fault sections can be located

VLSI Design 11

Table 7 Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks both before and after addinggates for testability

Filename Inputs Outputs States Total before testability Total after testabilityGC QC Number of lines GC QC Number of lines increase in QC

bbara 4 2 10 46 1096 14 116 1242 18 1330bbsse 7 7 16 99 1361 22 185 1629 26 1970bbtas 2 2 6 21 203 10 73 285 14 4040beecount 3 4 7 53 577 13 111 729 17 2630cse 7 7 16 137 2922 22 223 3266 26 1180dk14 3 5 7 104 973 14 164 1229 18 2630dk512 3 5 4 58 491 12 104 645 16 3140donfile 2 1 24 67 877 13 145 1069 17 2190ex1 9 19 20 355 3979 38 483 4797 42 2060ex2 2 2 19 97 1924 14 177 2178 18 1320ex3 2 2 10 51 715 12 117 867 16 2130ex4 6 9 14 74 618 23 162 838 27 3560ex5 2 2 9 43 631 12 109 767 16 2160ex7 2 2 10 48 680 12 114 826 16 2150keyb 7 2 19 110 4946 19 200 5236 23 590lion9 2 1 9 34 505 11 98 621 15 2300lion 2 1 4 15 79 7 51 137 11 7340planet1 7 19 48 646 4763 38 784 6169 42 2950planet 7 19 48 646 4763 38 784 6169 42 2950s1a 8 6 20 97 3668 24 197 3942 28 750s1 8 6 20 197 3864 24 297 4338 28 1230s8 4 1 5 36 1036 11 90 1150 15 1100sand 11 9 32 288 4941 30 400 5609 34 1350shiftreg 1 1 8 17 29 8 65 99 12 24140sse 7 7 16 98 1378 22 184 1644 26 1930styr 9 10 30 338 6553 29 448 7319 33 1170tav 4 4 4 23 403 12 69 487 16 2080tbk 6 3 32 110 3621 19 200 3911 23 800train11 2 1 11 47 742 11 111 884 15 1910train4 2 1 4 18 103 7 54 167 11 6210

The total overhead quantum cost of the circuit in Figure 10 is20 + 16 + 10 + 5 = 51 The quantum cost of the original circuitin Figure 6 is 53Therefore the quantum cost overhead of thetestable circuit is only 9623

7 Experimental Results

The process for designing the sequential reversible circuitand adding the gates for testability was applied to severalsequential benchmarks from theMCNC suite of benchmarks[48] As shown in Table 7 the additional circuitry requiredfor making the sequential reversible circuit testable adds anaverage of 30 overhead in terms of quantum cost Thehighest percentage overhead occurs for the smallest circuitsthis is a result of needing to copy the input and output linesseveral times In larger circuits the percentage overhead issignificantly lower

8 Conclusion

In this work an improved synthesis approach for sequentialreversible circuits is presented Three design examples aredemonstrated including an arbitrary sequential circuit with2-bit states 1-bit input and 1-bit output (Figure 4) a four-bitfalling-edge triggered updown counter with asynchronousload and a four-bit falling-edge triggered universal registerare shown We compare the quantum cost and the ancillainputs of the three designs with both the replacement designtechnique and the direct design technique reported in [26]The new design of the sequential circuit in Figure 4 saves4479 and 3977 in quantum cost and 6667 and 3333in ancilla inputs as compared to the replacement design anddirect design in [26] respectively The new counter designsaves 2128 in quantumcostwith the samenumber of ancillainputs as compared to the design in [26] The new registerdesign saves 6636 in quantum cost and 2222 in ancilla

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

VLSI Design 11

Table 7 Results showing gate count (GC) and quantum cost (QC) for a selection of sequential benchmarks both before and after addinggates for testability

Filename Inputs Outputs States Total before testability Total after testabilityGC QC Number of lines GC QC Number of lines increase in QC

bbara 4 2 10 46 1096 14 116 1242 18 1330bbsse 7 7 16 99 1361 22 185 1629 26 1970bbtas 2 2 6 21 203 10 73 285 14 4040beecount 3 4 7 53 577 13 111 729 17 2630cse 7 7 16 137 2922 22 223 3266 26 1180dk14 3 5 7 104 973 14 164 1229 18 2630dk512 3 5 4 58 491 12 104 645 16 3140donfile 2 1 24 67 877 13 145 1069 17 2190ex1 9 19 20 355 3979 38 483 4797 42 2060ex2 2 2 19 97 1924 14 177 2178 18 1320ex3 2 2 10 51 715 12 117 867 16 2130ex4 6 9 14 74 618 23 162 838 27 3560ex5 2 2 9 43 631 12 109 767 16 2160ex7 2 2 10 48 680 12 114 826 16 2150keyb 7 2 19 110 4946 19 200 5236 23 590lion9 2 1 9 34 505 11 98 621 15 2300lion 2 1 4 15 79 7 51 137 11 7340planet1 7 19 48 646 4763 38 784 6169 42 2950planet 7 19 48 646 4763 38 784 6169 42 2950s1a 8 6 20 97 3668 24 197 3942 28 750s1 8 6 20 197 3864 24 297 4338 28 1230s8 4 1 5 36 1036 11 90 1150 15 1100sand 11 9 32 288 4941 30 400 5609 34 1350shiftreg 1 1 8 17 29 8 65 99 12 24140sse 7 7 16 98 1378 22 184 1644 26 1930styr 9 10 30 338 6553 29 448 7319 33 1170tav 4 4 4 23 403 12 69 487 16 2080tbk 6 3 32 110 3621 19 200 3911 23 800train11 2 1 11 47 742 11 111 884 15 1910train4 2 1 4 18 103 7 54 167 11 6210

The total overhead quantum cost of the circuit in Figure 10 is20 + 16 + 10 + 5 = 51 The quantum cost of the original circuitin Figure 6 is 53Therefore the quantum cost overhead of thetestable circuit is only 9623

7 Experimental Results

The process for designing the sequential reversible circuitand adding the gates for testability was applied to severalsequential benchmarks from theMCNC suite of benchmarks[48] As shown in Table 7 the additional circuitry requiredfor making the sequential reversible circuit testable adds anaverage of 30 overhead in terms of quantum cost Thehighest percentage overhead occurs for the smallest circuitsthis is a result of needing to copy the input and output linesseveral times In larger circuits the percentage overhead issignificantly lower

8 Conclusion

In this work an improved synthesis approach for sequentialreversible circuits is presented Three design examples aredemonstrated including an arbitrary sequential circuit with2-bit states 1-bit input and 1-bit output (Figure 4) a four-bitfalling-edge triggered updown counter with asynchronousload and a four-bit falling-edge triggered universal registerare shown We compare the quantum cost and the ancillainputs of the three designs with both the replacement designtechnique and the direct design technique reported in [26]The new design of the sequential circuit in Figure 4 saves4479 and 3977 in quantum cost and 6667 and 3333in ancilla inputs as compared to the replacement design anddirect design in [26] respectively The new counter designsaves 2128 in quantumcostwith the samenumber of ancillainputs as compared to the design in [26] The new registerdesign saves 6636 in quantum cost and 2222 in ancilla

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

12 VLSI Design

Q1

Q1

x

C

R

Q0

Q1 Q1

lowast

Q0

Q0 Q0Q0

Q1

C

R

z

lowast

Q1+

Q0+

Modified next state logic Next state logic Falling-edge trigger Asynchronous reset Feedback Output logic

0

0

0

0

1

1

OMNOTLOF

OO

LMN = 0

L４ = 0

LF = 0

LO = 0

Figure 10 Online testable design of reversible sequential circuit of Figure 6 for single line fault testing

inputs as compared to the replacement design in [40] Theregister design also saves 3393 in quantum cost with a1667 increase in ancilla inputs over that in [26]

We also present an online testable design for sequen-tial reversible circuits for detecting single line faults Thetechnique presented in [44] is used for testing Toffoli-cascade portions of the circuit For testing sections of thecircuit built from controlled swap gates we propose a newtesting technique The testable design can simultaneouslydetect multiple single line faults in different sections of thecircuit As shown in Figure 10 the online testable versionof Figure 6 requires only 9623 quantum cost overheadFurthermore tests of several benchmarks indicate that as thecircuit complexity grows the percentage overhead requiredfor testability decreases

Future work includes automation of the mapping processand consideration of online testability for all three faultmodels

Disclosure

The first author did most of his work at the University ofLethbridge while on sabbatical from East West UniversityDhaka Bangladesh

Conflicts of Interest

The authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

The second author was supported by a grant from CanadarsquosNational Science and Engineering Research Council(NSERC) while pursuing this research

References

[1] G E Moore ldquoCramming more components onto integratedcircuitsrdquo Electronics vol 38 p 8 1965

[2] E P DeBenedictis ldquoThe Boolean logic taxrdquo Computer vol 49no 4 Article ID 7452299 pp 79ndash82 2016

[3] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 44pp 183ndash191 2000

[4] C H Bennett ldquoLogical reversibility of computationrdquo IBMJournal of Research and Development vol 17 no 6 pp 525ndash5321973

[5] A DeVos and Y V Rentergem ldquoPower consumption inreversible logic addressed by a ramp voltagerdquo in Proc 15th IntWorkshop Power Timing Model Optim Simul ser LNCS 3728pp 207ndash216 2005

[6] J Ren andVK Semenov ldquoProgresswith physically and logicallyreversible superconducting digital circuitsrdquo IEEE Transactionson Applied Superconductivity vol 21 no 3 pp 780ndash786 2011

[7] J Ren V K Semenov Y A Polyakov D V Averin and J-S TsaildquoProgress towards reversible computing with nsquid arraysrdquoIEEE Transactions on Applied Superconductivity vol 19 no 3pp 961ndash967 2009

[8] N Kostinski M P Fok and P R Prucnal ldquoExperimentaldemonstration of an all-optical fiber-based Fredkin gaterdquoOpticsExpresss vol 34 no 18 pp 2766ndash2768 2009

[9] C Taraphdar T Chattopadhyay and J N Roy ldquoMach-Zehnderinterferometer-based all-optical reversible logic gaterdquo Optics ampLaser Technology vol 42 no 2 pp 249ndash259 2010

[10] X Ma J Huang C Metra and F Lombardi ldquoReversible gatesand testability of one dimensional arrays of molecular QCArdquoJournal of Electronic Testing vol 24 no 1-3 pp 1244-1245 2008

[11] XMa J Huang CMetra and F Lombardi ldquoDetectingmultiplefaults in one-dimensional arrays of reversible QCA gatesrdquoJournal of Electronic Testing vol 25 no 1 pp 39ndash54 2009

[12] S Bandyopadhyay ldquoNanoelectric implementation of reversibleand quantum logicrdquo Supperlattices Microstruct vol 23 no 3-4pp 445ndash464 1998

[13] M A Nielsen and I L Chuang Quantum Computationand Quantum Information Cambridge University Press Cam-bridge UK 1st edition 2000

[14] V V Shende A K Prasad I L Markov and J P HayesldquoSynthesis of reversible logic circuitsrdquo IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems vol22 no 6 pp 710ndash722 2003

[15] D Maslov and GW Dueck ldquoReversible cascades with minimalgarbagerdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 23 no 11 pp 1497ndash1509 2004

[16] K N Patel J P Hayes and I L Markov ldquoFault testingfor reversible circuitsrdquo IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems vol 23 no 8 pp 410ndash416 2004

[17] D PVasudevan P K Lala J Di and J P Parkerson ldquoReversible-logic design with online testabilityrdquo IEEE Transactions onInstrumentation and Measurement vol 55 no 2 pp 406ndash4142006

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

VLSI Design 13

[18] V V Shende S S Bullock and I L Markov ldquoSynthesis ofquantum-logic circuitsrdquo IEEE Transactions on Computer-AidedDesign of IntegratedCircuits and Systems vol 25 no 6 pp 1000ndash1010 2006

[19] P Gupta A Agarwal and N K Jha ldquoAn algorithm for synthesisof reversible logic circuitsrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 25 no 11pp 2317ndash2330 2006

[20] A K Prasad V V Shende I L Markov J P Hayes and K NPatel ldquoData structures and algorithms for simplifying reversiblecircuitsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 2 no 4 pp 277ndash293 2006

[21] D Maslov G W Dueck D M Miller and C NegrevergneldquoQuantum circuit simplification and level compactionrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 27 no 3 pp 436ndash444 2008

[22] D Groszlige R Wille G W Dueck and R Drechsler ldquoExactmultiple-control Toffoli network synthesis with SAT tech-niquesrdquo IEEE Transactions on Computer-Aided Design of Inte-grated Circuits and Systems vol 28 no 5 pp 703ndash715 2009

[23] S N Mahammad and K Veezhinathan ldquoConstructing onlinetestable circuits using reversible logicrdquo IEEE Transactions onInstrumentation and Measurement vol 59 no 1 pp 101ndash1092010

[24] T Toffoli ldquoReversible computingrdquo MIT Lab Comput SciCambridge MA USA 1980

[25] H Thapliyal N Ranganathan and S Kotiyal ldquoDesign oftestable reversible sequential circuitsrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 21 no 7 pp1201ndash1209 2013

[26] M H A Khan ldquoDesign of reversible synchronous sequentialcircuits using pseudo Reed-Muller expressionsrdquo IEEE Transac-tions on Very Large Scale Integration (VLSI) Systems vol 22 no11 pp 2278ndash2286 2014

[27] A Barenco C H Bennett R Cleve et al ldquoElementary gates forquantum computationrdquo Physical Review A Atomic Molecularand Optical Physics vol 52 no 5 pp 3457ndash3467 1995

[28] J A Smolin and D P DiVincenzo ldquoFive two-bit quantum gatesare sufficient to implement the quantum Fredkin gaterdquo PhysicalReview A Atomic Molecular and Optical Physics vol 53 no 4pp 2855-2856 1996

[29] D M Miller R Wille and Z Sasanian ldquoElementary quantumgate realizations for multiple-control Toffoli gatesrdquo in Proceed-ings of the 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL rsquo11) pp 288ndash293 Finland May 2011

[30] J-L Chen X-Y Zhang L-L Wang X-Y Wei and W-QZhao ldquoExtended Toffoli gate implementation with photonsrdquo inProceedings of the 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT rsquo08) pp 575ndash578 China October 2008

[31] T Sasao ldquoLogic Synthesis and Optimizationrdquo in ch AND-EXOR Expressions andTheir Optimization pp 287ndash312 KluwerNorwell MA USA 1993

[32] N M Nayeem and J E Rice ldquoImproved ESOP-based synthesisof reversible logicrdquo in Reed-Muller Workshop May 2011

[33] J E Rice ldquoAn overview of fault models and testing approachesfor reversible logicrdquo in Proceedings of the 14th IEEE PacificRim Conference on Communications Computers and SignalProcessing (PACRIM rsquo13) pp 125ndash130 Victoria Canada August2013

[34] J Zhong and J C Muzio ldquoAnalyzing fault models for reversiblelogic circuitsrdquo in Proceedings of the 2006 IEEE Congress on Evo-lutionary Computation (CEC rsquo06) pp 2422ndash2427 VancouverBC Canada 2006

[35] I Polian J P Hayes T Fiehn and B Becker ldquoA family of logicalfault models for reversible circuitsrdquo in Proceedings of the 14thAsian Test Symposium (ATS rsquo05) pp 422ndash427 Kolkata IndiaDecember 2005

[36] J E Rice ldquoA new look at reversible memory elementsrdquo inProceedings of the 2006 IEEE International Symposium onCircuits and Systems (ISCAS rsquo06) pp 243ndash246 May 2006

[37] S K S Hari S Shroff S NMahammad andV Kamakoti ldquoEffi-cient building blocks for reversible sequential circuit designrdquo inProceedings of the 2006 49thMidwest SymposiumonCircuits andSystems (MWSCAS rsquo06) pp 437ndash441 IEEE Puerto Rico August2006

[38] H Thapliyal and A P Vinod ldquoDesign of reversible sequentialelements with feasibility of transistor implementationrdquo in Pro-ceedings of the 2007 IEEE International Symposium on Circuitsand Systems (ISCAS rsquo07) pp 625ndash628 USA May 2007

[39] M-L Chuang and C-Y Wang ldquoSynthesis of reversible sequen-tial elementsrdquo ACM Journal on Emerging Technologies in Com-puting Systems vol 3 no 3 pp 1ndash19 2008

[40] HThapliyal andN Ranganathan ldquoDesign of reversible sequen-tial circuits optimizing quantum cost delay and garbage out-putsrdquo ACM Journal on Emerging Technologies in ComputingSystems vol 6 no 4 pp 141ndash1435 2008

[41] M Haghparast and M S Gharajeh ldquoDesign of a nanometricreversible 4-bit binary counter with parallel loadrdquo AustralianJournal of Basic and Applied Sciences vol 5 no 7 pp 63ndash712011

[42] M H A Khan and M Perkowski ldquoSynthesis of reversible syn-chronous countersrdquo in Proceedings of the 41st IEEE InternationalSymposium on Multiple-Valued Logic (ISMVL rsquo11) pp 242ndash247Finland May 2011

[43] M H A Khan and J E Rice ldquoImproved synthesis of reversiblesequential circuitsrdquo inProceedings of the 2016 IEEE InternationalSymposium on Circuits and Systems (ISCAS rsquo16) pp 2302ndash2305Canada May 2016

[44] N M Nayeem and J E Rice ldquoOnline fault detection inreversible logicrdquo in Proceedings of the 2011 IEEE InternationalSymposiumonDefect and Fault Tolerance inVLSI andNanotech-nology Systems (DFT rsquo11) pp 426ndash434 Vancouver BC CanadaOctober 2011

[45] J P Hayes I Polian and B Becker ldquoTesting for missing-gatefaults in reversible circuitsrdquo in Proceedings of the 13th AsianTest Symposium (ATS rsquo04) pp 100ndash105 Washington DC USA2004

[46] D K Kole H Rahaman D K Das and B B BhattacharyaldquoSynthesis of online testable reversible circuitrdquo in Proceedingsof the 13th IEEE International Symposium on Design andDiagnostics of Electronic Circuits and Systems (DDECS rsquo10) pp277ndash280 Austria April 2010

[47] M A Nashiry G G Bhaskar and J E Rice ldquoOnline testing forthree fault models in reversible circuitsrdquo in Proceedings of the45th IEEE International Symposium on Multiple-Valued Logic(ISMVL rsquo15) pp 8ndash13 Waterloo Canada May 2015

[48] P Fiser Collection of Digital Design Benchmarks 2017 httpsdddfitcvutczprjBenchmarks

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