First Demonstration of a Surface Mountable, Ultra-Thin Glass BGA Package for Smart Mobile Logic Devices

Venky Sundaram*, Yoichiro Sato^, Toshitake Seki+, Yutaka Takagi+, Vanessa Smet, Makoto Kobayashi#, and Rao Tummala

3D Systems Packaging Research Center, Georgia Institute of Technology, Atlanta, GA 30332, USA ^Asahi Glass Company, Yokohama, Japan

+NGK Spark Plug Co. Ltd., Aichi Prefecture, Japan #Namics Corporation, Niigata, Japan

*vs24@gatech.edu

Abstract This paper presents the first demonstration of an ultra-thin

glass BGA package that is assembled on to mother board with standard SMT technology. Such a package has many new advances that include ultra-thin glass, high speed through via hole formation and copper metallization, double-side RDL wiring with advanced 3 micron ground rules, and Cu-SnAg microbump assembly of a 10mm silicon test die. Glass, as a package, overcomes the shortcomings of organic packages in bump pitch, CTE mismatch to Si and warpage and silicon interposers in electrical performance and cost. Glass packages are being developed to manufacture both as wafers for improved performance over Si and as panels to improve bump pitch over organic packages. Glass, therefore, is not just a high performance and low volume technology, like silicon interposers, but a pervasive package technology with lower cost, higher performance and thinner than silicon and organic packages. Glass has compelling benefits in thickness and I/O pitch reduction and reliability for one of the highest volume applications, namely, the packaging of high I/O logic devices for smart mobile systems. This paper represents a paradigm shift in ultra-thin packages using large glass panels for future smart mobile and high performance devices, and the first demonstration of 100um thin glass packages with 50-80um chip-level I/O pitch and 18mm x 18mm body size surface mount assembly at 400um pitch.

Introduction Glass packaging started at Georgia Tech and many other

R&D groups as a lower cost and higher performance alternative to silicon interposers, due to the low loss and large panel availability of ultra-thin glass [1]. The Georgia Tech team began to demonstrate such an interposer with its industry partners addressing major barriers that include the handling of large, ultra-thin glass panels, forming large number of ultra-small through vias at small pitch, metallization of these small copper vias without defects and with good adhesion, forming 2-5 micron RDL wiring layers with bump pitch at 20-50 microns, assembly of chips to these brittle substrates, and improving its thermal conductivity. It became clear that glass can be a pervasive platform technology that is both a high performance and very low cost technology. As the glass packaging technology matures and is applied to high volume applications, it should be at the same or lower cost than organic packaging. Glass simplifies the material manufacturing compared to laminates, since FR-4 or low CTE laminates require four different materials and process technologies such as glass fiber, glass and ceramic fillers,

epoxy, flame retardant and all these put together to form the 5th material that is called core or prepreg. In the case of glass, it is one material and one process and is ultra-thin to start with, driven by touch displays. Glass also reduces the processing cost per package since it can be scaled to much larger manufacturing panels or roll to roll than FR-4, driven by its superior dimensional stability and higher modulus. Glass is a high temperature material, resistant to moisture and is available in many compositions with many CTEs, from below Si CTE to above GaAs CTE.

Glass is seen, therefore, not just as a high performance interposer technology, but as a pervasive low cost platform packaging technology that is suitable for packaging all devices that are packaged currently that include single chip logic and memory packaging, MEMS & Sensors Packaging, RF, Power & Analog Packaging. In addition, it is applicable and is being developed for packaging of 2.5D multichip packaging with ultra-high number of interconnections between chips in side-by-side configuration. Ultimately, it is being developed as a superior alternative to 3D ICs, but without TSVs, in what is called 3D interposers and packages. Other applications that are being explored include 3D IPDs for passives on both sides of ultra-thin glass, and 3DIPAC for ultra-thin passives and actives on both sides with shortest distance between actives and passives. The specific applications for 3D IPACs include cell phone cameras, RF and power modules, 3D optoelectronics replacing electronic TSVs with Photonics.

This paper focuses on one of the highest volume applications, namely, the packaging of high I/O logic devices for smart mobile systems. A schematic of the glass BGA package that can be SMT attached to FR-4 motherboard, is shown in Figure 1.

PWB

IC

180um Glass

BGA

Figure 1. Glass BGA Package for Smart Mobile Application

Processors Previously, the authors have reported individual building

block technologies such as through via hole formation, metallization and reliability, electrical characterization of

978-1-4799-2407-3/14/$31.00 ©2014 IEEE 365 2014 Electronic Components & Technology Conference

glass substrates and initial board-level assembly and reliability [1, 2]. This paper, for the first time, integrates all the glass package building blocks into the first thin glass BGA package demonstration.

The second section describes some of the building block technology advances in glass packaging. The third section presents the first glass substrate process or record (POR) with a full process flow, materials and tools. The fourth section presents the first demonstration of a mobile glass BGA package including test vehicle design, glass substrate fabrication, chip and board level assembly. The fifth section analyzes the warpage and thermal behavior of glass BGA packages and the final section summarizes the research.

Glass Package Building Block Technologies Initial advances in through package vias (TPV) and re-

distribution layers (RDL) on glass have been previously reported [2]. This section describes the latest advances in TPV, RDL and glass assembly.

Through Package Vias (TPV) in Ultra-Thin Glass: The single biggest barrier to the use of glass as an interposer and package is its brittleness, resulting in cracking of glass during via hole formation of small diameter TPVs at small pitch. Addressing this barrier requires overcoming a number of fundamental challenges including handling of thin glass, defect-free via hole formation, and low-stress conductive via metallization at high speed. The glass interposer starts with ultra-thin glass (30-180µm) enabled by innovations in fusion draw and float glass formation technologies in defect-free panels and wafers. Thinner glass, not only enables the formation of ultra-small TPVs having TSV-like dimensions (<10µm via diameter) with low aspect ratios, it also significantly increases the throughput of via hole formation. Thin glass also reduces interconnect length, hence shorter signal path, leading to smaller latency.

Glass, however, is inherently brittle; and handling of ultra-thin glass during processing is, therefore, a key challenge. A double-sided, panel-based process was developed using polymer lamination of glass with low modulus and low electrical loss (tan δ) polymers. Polymer lamination, not only facilitates handling of thin glass, but also reduces laser impact on the glass surface during laser via formation and avoids direct metallization on glass surfaces. This novel handling method was previously demonstrated at 180um glass thickness, but has recently been applied successfully to fabricate double side ultra-thin glass panel substrates as thin as 30um thin drawn glass, without the use of bonded carriers, as shown in Figure 2.

Several methods have been investigated and four different methods have been demonstrated with via formation speed of greater than 1000 vias per second. Two of these methods are laser based, and the other two have been provided by Asahi Glass and Corning Glass respectively [3, 4]. The key to reliable TPV hole formation is to minimize heat and stress accumulation, and prevent micro crack formation. Metallization of TPVs was carried out using low cost wet electroless plating of thin copper, followed by electroplating of thick copper.

Figure 2. Demonstration of Handling of Ultra-Thin 30um Glass Through TPV and RDL Fabrication without Carriers

A low cost, package substrate-compatible, semi-additive-

plating (SAP) approach was developed to metallize the TPVs and double-sided wiring simultaneously. Wet chemistry for metallization (as opposed to vacuum-based sputtering), enables large panel processing. Both conformal and via fill plating processes have been applied to thin glass TPVs. Figure 3 shows cross-section images of metallized TPVs formed by excimer laser ablation and the impact of thickness reduction on reducing the via diameter and pitch.

Figure 3. TPV in Thin and Ultra-Thin Glass by Excimer Laser Ablation and Semi-Additive Copper Plating Processes

3-5um Redistribution Layers (RDL) on Glass: Fine pitch re-distribution layers were fabricated on both

sides of the thin glass with TPV simultaneously using low cost panel level processes, without the use of any chemical-mechanical polishing (CMP) or vacuum deposition methods, resulting lower cost than wafer back end of line processes used on silicon interposers. The goal was to shrink the design rules for lines and vias in each layer, in order to minimize the total number of metal layers. For the mobile glass package, a 2 + 0 + 2 layer structure was targeted with ultra-fine lines on both metal layers on top and bottom of the glass. A schematic of the target design rules to support 50um I/O bump pitch is shown in Figure 4.

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Figure 4. Schematic Cross-section of GEN 1 Target Dimensions for RDL Layer on Glass Interposer

Glass has an ultra-flat and smooth surface similar to silicon and better than organic laminate cores, and hence can extend the semi-additive plating process limits for line width reduction faced by organic substrates. Silicon interposers can achieve sub-micron line widths, but have line resistivity and cost challenges driven by single sided thin film processes and back end of line damascene processes on wafers. An ultra-smooth polymer dry film dielectric, ZEONIFTM ZS-100 from Zeon Corporation, Japan, with 10um and 15um thickness, was laminated on both sides of the thin glass to achieve a flat and smooth surface for electroless seed layer plating and lithography. A low cost and large panel scalable wet metallization process combined with large field size lithography and high resolution dry film photoresists was used to fabricate a test vehicle with line widths and spaces from 1um to 10um. A projection UV lithography tool, UX44101 from Ushio Japan, was used for imaging on a high resolution dry film resist from Hitachi Chemical. Major challenges in the semi-additive process, including seed layer adhesion to polymer dielectric, photoresist adhesion to smooth seed layer, and seed layer etching, have been overcome. A top view SEM micrograph and a cross-section of 5um lines and spaces used to route five rows of 50um I/O pitch bumps is shown in Figure 5.

5/5 um L/SAA

4.2um11.1um

Figure 5. Top View SEM and Cross-section of 5um lines and

spaces with 11um copper thickness fabricated on ZS-100 Polymer RDL Layer on Glass

Generation 1 Glass Substrate Process of Record (POR)

A Georgia Tech glass consortium involving a global team of industry end users and supply chain partners was launched in 2010 to address the technical challenges to the realization of ultra-thin glass interposers and packages. The team has demonstrated the first generation glass substrate with a process of record (POR) overcoming all the major barriers, namely, fine pitch and high speed through package vias

(TPV), thin glass handling, Cu TPV reliability and double side re-distribution layers at 50µm I/O pitch. The Gen 1 glass substrate, was demonstrated using 100µm and 150µm thin glass made by advanced float and fusion draw processes from Asahi Glass, Corning, and Schott Glass companies. The fine pitch through vias were formed using a high speed laser process, demonstrating high throughput in excess of 1000-2000 vias per second. Multi-layer and double side RDL with low cost materials, tools and processes using ultra-thin dry film polymers with lithographic ground rules down to 3-5um, discussed in the previous section were integrated on thin glass with fine pitch TPVs. A complete process flow, bill of materials, tool sets for manufacturing, and design rules have been compiled, ready for transfer to industry partners for prototyping and volume manufacturing. Extensive reliability tests have been conducted and the through via daisy chains at 120µm pitch, metallized with plated copper, have passed more than 1500 accelerated thermal cycle (-55°C to 125°C) tests with MSL-1 and MSL-3 pre-conditioning. A cross-section and top view of a four metal layer double sided glass substrate is shown in Figure 6.

180 um Thin GlassGEN 1 POR Ready for Prototypes

Figure 6. First Process of Record (POR) for Glass Substrate Fabrication Demonstrated by Georgia Tech and Its Partners

The demonstration of the first POR for glass substrates

represents a major milestone in the glass technology development and has been subsequently used to optimize assembly processes for thermo-compression bonding at chip-level and BGA reflow at board-level. The POR was also used to design, fabricate and assemble the first mobile glass BGA package demonstrator targeted at application processors as explained in the following section.

Glass BGA Package Demonstrator for Mobile Application Processors

The smart mobile package test vehicle is the first demonstration of a fully integrated glass package with assembly of a silicon test die on an ultra-thin glass interposer with vias and double sided routing layers, with a fully populated BGA ready for SMT attach to the motherboard. This test vehicle consists of a mobile application processor package emulator with ~5,500 I/Os on a 10mm x 10mm test die, a 100µm thick glass substrate with 4 metal layers, and an SMT-compatible 18.4mm x 18.4mm BGA package at 400µm pitch.

Test Vehicle Design: The 10mm x 10mm test die has four peripheral rows of bumps at 80/40 µm pitch in a staggered configuration, and a central area array at 150 µm pitch. A 4-

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metal-layer interposer structure with 120 µm pitch TPVs and BMVs, and 4-7um L/S was designed to escape route such a high I/O density down to the BGA for SMT interconnection to printed wiring board (PWB). Figure 7 illustrates an example of escape routing on the top metal layer used in this test vehicle design. The final design was panelized on a 150mm x 150mm quarter panel containing 24 individual BGA package units.

Bump Pad

4/4μm L/S

RDL Via

Figure 7. Schematic of Escape Routing with 4 µm Lines and Spaces connecting Microbump Landing Pads to RDL Vias on

the Top Layer of Glass Substrate

Process Flow: A complete process flow starting with thin glass and covering the substrate fabrication, chip assembly, BGA balling, dicing and SMT placement on PWB is shown in Figure 8.

1. Glass surface treatment

2. Double side polymer laminationZS-100 20μm

3. TPV formationExcimer or CO2 laser

4. TPV & 1st RDL metallizationSemi-Additive Process

5. Double side polymer laminationCu treatment, 20μm ZS-100

6. RDL micro via formationUV laser

7. RDL Via and 2nd RDL metallizationSemi-Additive Process

8. Passivation & surface finish

9. Chip-level InterconnectionPanel-level process

10. BGA balling & singulationBall drop & dicing

11. Board-level SMT assemblyAssembly on PWB board Batch reflow

PWB

Singulation

Figure 8. Complete Process Flow Starting with Bare Glass and Ending in SMT Attach of Glass BGA Package to PWB

Chip-Level Assembly: Die-to-panel assembly was achieved by low-pressure thermocompression bonding with a pre-applied polymer (BNUF, NCF or NCP) using a Finetech Matrix semi-automatic flip-chip bonder with a placement accuracy of 3um. A 6" x 6" panel can be accommodated on the stage of the flip-chip bonder to achieve panel-level assembly. The assembly sequence was as follows:

1- Dispensing pre-applied polymer on the substrate bonding areas, followed by B-staging of BNUF (skipped for NCF or NCP)

2- Panel placement on the stage of the flip-chip bonder, kept in place with vacuum, and heating the plate to 70-90degC to lower the viscosity of the polymer material, so as to not introduce any misalignment when placing the die

3- Pick and place and thermocompression bonding of each die individually on the panel. The heat transfer was unidirectional from the chip-side. After placement with a higher applied pressure (necessary to create contact through the viscous polymer), the pressure was reduced to 1.5MPa and temperature ramped up to 260C (lead-free reflow temp), maintained for 3 seconds to allow IMC formation with the ultra-short bumps. Ramping down the temperature before moving on to the next die.

4- After bonding of all dies, a batch-type post-cure in air was used to fully cure the polymer material for 1 hour at 165C for NCP, 3 hours at 165C for BNUF.

This bonding scheme enables bonding on a panel with low warpage, is scalable to thermo-compression bonders used in production, and allows the assembly of a single die without affecting the adjacent dies. Figure 9 shows a cross-section micrograph of the Cu-SnAg interconnects from chip to glass. One of the key benefits of glass for mobile processor packaging is the high modulus of glass core (~80 GPa) compared to that of low CTE organic core (~20-35 GPa), which reduces warpage during chip assembly. The high glass transition of temperature of glass at around 550C results in no change in the glass modulus during the entire assembly temperature ramp, hold and cool down cycle.

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Si die

Glass Core

Figure 9. Cross-section Micrograph of Fine Pitch Cu-SnAg Interconnections on Thin Glass Substrate by Thermo-

Compression Bonding

The warpage behavior of thin glass was measured using a Akrometrix PS-200 Shadow Moire tool, and compared to the normalized warpage of thin core organic substrates for similar die size and package size available in recent published literature. The high and stable modulus of glass combined with low CTE of around 3.8 ppm/C resulted in very low warpage for the glass substrate as shown in Figure 10, which will enable scalability to thinner packages.

-150

-100

-50

0

50

100

150

0 50 100 150 200 250 300Temperature (°C)

War

page

(µm

)

Glass (0.18mm)

Organic (0.21mm)

Figure 10. Reduced Warpage of High Modulus Glass

Substrate Compared to Organics after Lead-Free Solder TCB Bonding and Underfill Cure

SMT Attach to PWB: Silicon interposers for high performance applications are typically assembled to an organic BGA package which is then mounted to the PWB. This results in much higher cost in the bill of materials (BOM) and added thickness as well additional sites for interconnection failures. For cost sensitive mobile applications, it is preferred to have only one level of packaging from chip level to board level. The glass BGA package was designed to be directly SMT attached to standard FR-4 PWBs using reworkable lead-free solder ball interconnections without the use of underfill at board level. Glass offers the ability to tailor the CTE from 3ppm/C to 10ppm/C with several CTE values available in between. This benefit of selecting glass CTE in between that of silicon and FR-4 enables board-level reliability of glass BGA packages extendable to larger body sizes [5]. Figure 11 shows the top view of a fully integrated glass BGA package for the mobile application processor emulator after SMT attach to board. A customized mechanical dicing process was developed in partnership with Disco, Japan to singulate the glass packages prior to SMT pick and place and reflow. The glass substrate has extremely low warpage even after three reflows, first at die bonding, second at BGA ball reflow on the

back side of the glass substrate, and third at board level SMT attach.

Glass

PWB

Die

Figure 11. First Demonstration of Glass BGA Package for Mobile Application Processors with 18mm x 18mm body size

and 400um BGA pitch using 100um Thin Glass

Conclusions This paper presented the first demonstration of an ultra-

thin glass BGA package for mobile application processors that is assembled on to mother board with standard SMT technology. Such a package integrated for the first time, a number of building block technologies in ultra-thin glass, high speed through via hole formation and copper metallization, double-side RDL wiring with advanced 3 micron ground rules, and Cu-SnAg microbump assembly of a 10mm silicon test die. Glass, as a package, overcomes the shortcomings of organic packages in bump pitch, CTE mismatch to Si and warpage and silicon interposers in electrical performance and cost. Glass, therefore, is not just a high performance and low volume technology, like silicon interposers, but a pervasive package technology with lower cost, higher performance and thinner than silicon and organic packages.

Acknowledgments The authors would like to acknowledge the numerous

contributions of the glass packaging team from GT PRC and its industry partners to this work. This work was supported by funding from the Low Cost Glass Interposers & Packages (LGIP) global industry consortium at Georgia Tech PRC.

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