IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AIND CONTROL INSTRUMENTATION, VOL. IECI-25, NO. 1, FEB. 1978 45

figuration space) and the probable holding time spent in eachregion is incorporated into the controller. This informationis used in conjunction with the plant measurements to learnwhich region the plant is in, so that the proper control can beapplied.The structure of the controller is a bank of Kalman filters

each matched to a region of the configuration space. Thefilter estimates are multiplied by correspoonding feedbackgains (different regions require different gains) and the overallstate variable feedback to the plant is computed as a weightedsum of the individual feedback values.The number of regions used in the formulation of the con-

troller depends on the design criteria and on the nature of thenonlinear system itself. For example, a larger operationalrange or better accuracy will require more regions. The typeand magnitude of the nonlinearity will also influence the num-ber of regions. It is necessary that the domain of attractionof adjacent regions be overlapping in order to drive from oneregion to another; however, this last requirement is usuallysatisfied if the number of regions is chose'n solely to givereasonably good accuracy.Each Kalman filter operates independently on the current

measurement, thus making this controller amendable toparallel processing. In addition, the filter gains can be precom-puted and stored in tabular format (unlike most nonlinearfilters, such as the "extended Kalman filter [8] "). These two

advantages yield a very low execution time for the imple-mented controller.The nonlinear oscillator example reported herein represents

a significant control problem due to the rapid movement ofthe state between regions. The results have been very encour-aging, even for large levels of noise. Plans are already under-way for the application of this type of controller to nonlinearstochastic systems of medium order (4-12).

REFERENCES

[1] O.- J. Oaks and G. Cook, 'Piecewise linea control of nonlinearsystems," IEEE Trans. IECI, vol. 23, no. 1 'pp. 56-63.

[2] H. F. VanLandingham and R. L, Moose, "'Digital control of highperformance aircraft using adaptive estimation techniques," IEEETrans. AES, vol. 12, no. 2, March 1977.

[3] P. E. Zwicke, R. L. Moose, and H. F. VanLandingham, "Estimationfor nonlinear systems," Proc. 9th Southeastern Symposim on Sys-tem Theory, UNCC, Charlotte, NC., March 1977.

[4] H. F. VanLandingham, R. L. Moose, and P. E, Zwicke, "Controlof nonlinear stochastic systems using adaptive estimation," South-eastcon Proceedings, Williamsburg, VA., April 1977.

[5l R. L. Moose and P. E. Wang, "An adaptive estimatQr with learningfor a plant con'taining semi-Markov switching parameters," IEETrans. SMC, vol. 3, May 1973.

[6] D. G. Lainiotis, "Partitioning: A unifying famework for adaptivesystems, II: Control," IEEE Proceedings, August, 1976.

[7] R. A. Howard, "System analysis of semi-Markov processes," IETrans. vol. ME-8, April 1964,

[8] A. Gielb, et al., Applied Optimal 4stimation, MIT Press, Cambridge,MA., 1974, Chap. 6.

[9] J. S. Meditch, Stochastic Optimal Linear Estimation and ControI,McGraw-Hill Book Co., New York, 1969 Chap. 5.

t iring Circuit or ree-rbase

yristor-Bridge Rectifier

B. ILANGO, R. KRISHNAN, R. SUBRAMANIAN, AND S. SADASIVAM

Abstract-Existing firing schemes for the firing of three-phase SCRbridge rectifiers used for industrial applications employ equidistantfiring pulses. Mostly they consist of six identical phase control circuits.In this paper a compact scheme using minimum integrated circuit com-ponents is described. It has a fast response for triggering angle correc-tion andd gives a full range control of voltage.

Manuscript received September 28, 1976; revised March 30, 1977.B. Ilango is with the Department of Power Systems Engineering,

College of Engineering, Guindy, Madras 600025, India.R. Krishnan and R. Subramanian are with the Department of Electri-

cal Engineering, College of Engineering, Guindy, Madras 600025, India.S. Sadasivam is with the Department of Electrical Engineering,

Central Polytechnic, Madras 600020, India.

INTRODUCTION

T"HE INDIVIDUAL phase control of three-phase rectifiersfor industrial applications [1] uses a large number of

components. But it has an advantage in the form of minirnumdelay of one sixth of a period for the corrections of the firingangle. An economic equidistant pulse firing scheme [21 utiliz-ing minimum components using integrated circuit chips hasgiven insignificant error in the equidistant spacings in the firingangle and simpler generation of synchronized and phasecontrolled pulse train in comparison to other existing schemnes.The chief disadvantage of the above scheme is its inability to

0018-9421/78/0200-0045$00.75 C 1978 IEEE

46 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-25, NO. 1, FEB. 1978

4 6

3' CONTROLLED RE(

2]

!CTIFIER MODULATING

Fig. 1. 30 full-wave controlled rectifier firing circuit-block diagram.

correct the firing angle within a time of one period of acsupply.The ripples from a half-wave rectified voltage are made use

of for the simultaneous pulse triggering of SCR's in bridgeponfi uration [3]t This simple firing scheme gives only 25 to100 control of conduction angle.In the proposed scheme, rectified voltages are obtained

through a full-wave rectifier and the dc voltage is blocked.Thp ripple potential is utilized for generating trigger pulsesand for synchronization. Steering of pulses to the appropriateS R's is ac omplished through a logic circuitry. Full controlover conduction angle is achieved. A control voltage will alterthe firing angle within a maximum period of one sixth of acyc e. This scheme is implemented with a minimum numberof integrated circuit chips.

PROPOSED SCHEME

Fig. 1 shows the block diagram of the three-phase full-wave controlled rectifier firing circuit. A stage by stage de-sign is explained below. The complete firing circuit is givenin Fs. 2.

Development of Firing CircuitA given SCR in the three-phase full-wave bridge (Fig. 1)

begins to conduct when its anode voltage becomes positive(its voltage is crossing 600), if gate pulse is applied at thisinstant. Within one cycle, six SCR's should be fired. So thegate pulses should have a frequency six times the supplyfrequency.Three identical single-phase filament transformers, each

having a center tapped secondary, are taken. The secondaries

are connected in double star. The two half-wave rectificationsare done by six diodes. The rectified voltage would be dcvoltage superimposed by (third) harmonic ripples as shown inFig. 3d1, for half-wave rectifier 1. Fig. 3.3 gives the same forrectifier 2.

DC Voltage BlockingThe (third) harmonic ripples can be used as the triggering

source. So the unwanted dc voltage is blocked using a resis-tance and capacitance combination. The output is shown inFig. 3.2 for rectifier 1 Fig. 3.4 gives the same for rectifier 2.The value of resistance is determined by maximum inputresistance for the monostable 1 and 3. For dc blocking, thetime constant of RC coupling should be large compared toperiod of ripple.

Firing Angle ControlThe (third) harmonic ripples (Fig. 3.1) from half-wave

rectifier 1 are given as triggering inputs to monostable 1. Theoutput of the monostable 1 would be rectangular pulses ofripple frequency (Fig. 3.5). The input to monostable re-quires voltage more than 0.8 V to give output. To get outputpulses at zero crossing of input ripple, as weli as variations infiring angle, another monostable 2 is used. By varying the RCcombination of monostable 1, the negative edge of the outputpulse of it is varied. This output pulse is used as input pulseto monostable 2. By varying the negative edge of monostable1, the positive edge of output of monostable 2 can be variedeven from the zero crossing of the ripple (Fig. 3.6). The sameis shown for the half-wave rectifier 2 in Figs. 3.7 and 3.8. Theoutputs of monostables 2 and 4 (Figs. 3.6 and 3.8) are given

ILANGO etal: FIRING CIRCUIT FOR RECTIFIER

sM

G,.

bo

C 0o -230 / 9-0-9FILAMENT

TRANSFORMERS

DIFF ERENTIATOR

Fig. 2. 3,0 full-wave controlled rectifier firing circuit.

as the inputs to the OR gate and its output is shown in Fig.3.9. By varying the resistance in the RC combination of themonostable 1 , full control over the conduction angle is achieved.

Mod-6 Counter Plus DecoderThe output pulses of monostable 2 are given as clock pulses

to the mod-6 counter. A decade counter (Fig, 4.1) is modifiedand used as a mod-6 counter (Fig. 4.2). The output of themod-6 counter is given to the decoder. The decoder willdecode the input pulses so that the output would be onepulse for six input pulses (Fig. 3.11). An inverter is used toget positive pulses.

Steenrng ProcessFiring pulses should be directed to the gate of that SCR (say

SCR1) for which the anode voltage is positive (that is, crossing600), At the instant of switching, the counter may store anynumber from 0 to 5. Hence, the firing pulse will not reach thecorrect SCR. For example, the counter may store the number3, which causes a firing pulse to be sent to SCR 4 (the anodemay not be positive), whereas the correct SCR to which thepulse to be supplied is SCR1 (the anode will be positive). Toavoid this, a steering pulse is produced to ensure the correctsupply of gate pulse to the correct SCR.For the production of a steering signa, a third monostable

is used. It has its input from the secondary of any one of thefilament transformers (the wave shape of this input voltage issimilar to the anode voltage of say SCR1, Fig. 3.14). The out-put from the monostable 5 is taken from Q. The outputwaveform is shown in Fig. 3.16. The position of the positiveedge of this output can be varied by varying the RC of mono-stable 5, This positive edge is placed at 600 with respect tothe input waveform of monostable 5. This output of mono-stable 5 is differentiated; the resultant negative pulse may be

clipped and the remaining positive pulse occurs (Fig. 3.18) atthe 600 point of the monostable input voltage, which is alsothe same point of anode voltage of SCR1. That is, the positionof the positive pulse indicates that the anode of SCR1 be-comes positive. This positive pulse repeats for every 3600,which can be exploited as explained below to stop the count-ing of the decade counter and reset to 0 storage. So 0 storageis made to appear at the gate of SCR1 (its anode is positive).The positive pulse from the differentiator is applied to one

of the inputs of two OR gates (Fig. 4.3). The other inputs tothe OR gates are from B and C of the decade counter. Theoutputs of the OR gates are applied to 2 and 3 of the decadecounter.Table I gives its truth table. Only at the sixth pulse do the

B and C outputs become 1 and 1. Whenever the B and C tryto send 1 and 1 to 2 and 3 of the decade counter, it resets to0. So the counter acts as mod-6 counter as shown in Fig. 4.2.Table II gives the outputs of OR gates for all 6 possible inputsfrom B and C of the decade counter, and 1 from the differen-tiator (This 1 is the positive pulse representing the 60' crossingof the anode voltage of SCR1). The outputs of the OR gatesare always 1 and 1 which are applied to 2 and 3 of the decadecounter (Fig. 4.3). As said earlier, the counter resets to 0,Table III gives the outputs of the OR gates for all 6 possibleinputs from B and C of the decade counter and 0 from thedifferentiator (0 represents that the angle is less than 600 ofanode voltage of SCR1, that is, the anode of SCR1 is not posi-tive). The outputs of OR gates are not 1 and 1, so the counterdoes not reset (that is, the counting proceeds), so that nogate pulse to the nonpositive anode of SCRI. This is therequirement.Thus monostable 5, followed by the differentiator, the OR

gates, and the counter is made to send a signal to steer theapplication of Pate oulse to that SCR for which the anode is

47

48 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-25, NO. 1, FEB. 1978

FIG.3.1 OUTPUT OF 30 HALFWAVE RECTIFIER 1 FIG. 3.12 ASTABLE OSCILLATOR OUTPUT

FIG. 3.2 THIRD HORMONIC RIPPLE AFTER DC VOLT L J LBLOCKING OF 3.1 IL IL

IiL I!LFIG. 3.3 OUTPUT OF 30 HALFWAVE RECTIFIER 2 }i ll

-- ------ . ---- ----- -~- FIG. 3.13 OUTPUT OF AND GATES

FIG. 3.4 THIRD HORMONIC RIPPLE AFTER DC VOLT Vab -Vca Vbc ab Vc Vbc Vab Vc Vbc -Vab Vca VbcBLOCKING OF 3.3

NEGATIVE EDGE POSITION IS VARIABLE ( SPAN 120 /

^~~~~~~ vFIG. 3.5 OUTPUT OF MONOSTABLE 1

POSITIVE EDGE POSITION IS VARIABLE ( SPAN 1200)

FIG. 3.6 OUTPUT OF MONOSTABLE 2FIQ3.14 APPLIED WAVEFORM TO MONOSTABLE 5/ANODE OF SCR1

H H H H LI ___ ____

s 1 3

FIG.3.7 OUTPUT OF MONOSTABLE 31 6

2

FIG. 3.15 FIRING SEQUENCE (each SCR conducts for 1200)

FIG.3.8 OUTPUT OF MONOSTABLE 4

FIG.3.16 OYTPUT OF MONOSTABLE 4

FIG. 3.9 FIG.3.10 OUTPUT OF OR GATE/ INPUT OFMOD.6 COUNTER

FIG. 3.17 OUTPUT OF DIFFERENTIATOR

n Lz LNI I

Ji L- ,FIG.3.18 POSITIVE PULSE EXISTS WHENEVER ANODEVOLTAGE OF SCR1 CROSSES 600FIG.3.11 OUTPUT OF J L

DECODER AFTERINVERSION J L

Fig. 3.

ILANGO et al.: FIRING CIRCUIT FOR RECTIFIER

14 13 12 11 10 9 8

1 2 3 4 5 6 7

T T-,IL-

FIG. 42 7490 AS MOD - 6 COUNTER

FIG. 4.3 DECADE COUNTER PLUS OR LOGIC

Fig. 4.

positive, whatever may be the initially stored number whilestarting.

ModulationSustained triggering is necessary to ensure reliable operation

for different gate and load characteristics. Power dissipationin the SCR gate is less, compared with continuous sustainedtriggering. To get sustained triggering pulse, modulation ofcontrol pulses (Fig. 3.11) for the SCR gate is necessary. Con-trol pulses and high-frequency output (of the order of 5 KHz)of astable multivibrator (Fig. 3.12) are given as inputs to anAND gate The output of the AND gate would be the modu-lated control pulses (Fig. 3.13).

Buffer Stage

In the case of the three-phase operation of an SCR bridgecircuit, the gates must be driven through pulse transformersbecause of the isolation required between different phases as

well as trigger circuits.

Protection

The dc blocking resistance of RC combination connected tomonostables 1 and 3 is shunted by a transistor. The transistorbase will receive a signal in case of a fault in the power circuit,driving the transistor to saturation. This will cut the inputpulses to monstables 1 and 3, and hence, the SCR's wouldnot be given the gate pulses. This simple fast-acting schemecan be implemented.

CONCLUSION

The scheme discussed above is found to work satisfactorilyover the entire conduction period. Apart from the require-

TABLE ITRUTH TABLE OF DECADE COUNTER

COUNT - OUTPUTD C B -A

6 6 __O O 0 0 0__1___ 0 0 0 1

2 __ 0 0 1 03 0 0 1 1

4.__ 0 10 0_ _ ,0 1 0 1

6__ __0

7 0 1 18 1 0 0 0

- __ _____0

TABLE II

CONTINPUT TOO LOGIC FROM OUTPUTS OFB C Dittrentiator WO'LOGIC NOTE:

O o 0.N___ 1 1 1 COUNTER RE1 O 0 -j 1 1 ZERO (-.BC

..,__.i__ o. ARE...AN.2 '1 1 1 1 PUTS OF'OI3 1O 1 1 1 ~~~~~~~AREI ANDC 1)4 O 11.L1 THEOINPUTS5 O 1 1 16 _t__ 1 1 __ NFEET

TABLE III

COUNT IN~''-TQLOGIC FROMI OUTPUTS OFC C Diferenti_tor ORLOGIC NOTE:0 0 0 O O O COUNTER PF1 0 0 O 0 0 COUNTING{( .

2 1 o 0 110 OUTPUTS o3 O__ i1~ O ARE NOT 1 A-_ - [0 [_O WHENEVER4 0 1 0 0 FROM__ FFE__ .. .. . . ARE O'

6 _ 0

ESETS TOOTH OUT-IRLOGICI)WHENEVER;FROMIATOR ARE 1

ROCEEDS1 BOTH)F'OR'LOGICiND 1)THE INPUTSRENT IATOR

ment of a lesser number of components, discrete componentsare utilized to the minimum. Pulse steering is achieved using alogic circuitry. Response of the firing angle to control voltageis almost instantaneous.

ACKNOWLEDGMENTThe authors wish to thank Prof. T. R. Natesan and Prof.

V. N. Sujeer of the Electrical Engineering Department, Collegeof Engineering, Guindy, Madras, India, for the facilities madeavailable for this work.

REFERENCES

[1I T. Krishnan and B. Ramaswami, "A fast response d.c. motor con-trol," IEEE Trans. Id. App., vol. IA-1O, pp. 643-65 1, 1974.

2] Remy Simard and V. Rajagopalan, "Economical equidistant pulsefiring scheme for thyristorized D.C. driyes,' IEEE Trans. IndElectron. Contr. Instmm., vol. IECI-22, No. 3, pp. 425-429, 1975.

[31 J. S. Wade Jr. and L. G. Aya, "Design for simultaneous pulse trig-gering of SCRs in three phase bridge configuration," IEEE Trans.Id. Electron. Contr. Instmm., vol. IECI-18, no. 3, pp. 104-106,1971.

INPUT V-s

.-

I

NC A D I C

14 13 12 11 10 9 8

1 2 3 4 5 6 7

BD RNO RO2 NC Vcc Rg1 Rg2INPUT

FIG. 41 7490 DECADE COUNTER

4S9

INPUT