Analysis of a PLL Based Frequency Synthesis

A thesis submitted to the Department of Electrical and Electronic

Engineering in Partial Fulfillment of the Requirement for the Degree

of

B.Sc. in Electrical and Electronic Engineering (EEE)

UNIVERSITY OF INFORMATION TECHNOLOGY & SCIENCES

(UITS)School of Computer Science and Engineering

Dhaka, Bangladesh 2011

1

University of Information Technology & Sciences

(UITS)GA-37/1 Progati Sarani, Baridhara J-Block, Gulshan, Dhaka-1212, Bangladesh

A Thesis on

Analysis of a PLL Based Frequency Synthesis

Submitted byName ID

Reduwan Ahmad Ashrafi 08310087

Md.Kazi Noman Arefin 08310090

Md.Shamsul Arfin 08410067

Supervisor

Md. Qamarul HasanLecturer, Dept. of Electrical & Electronic Engineering (EEE)

University of Information Technology and Sciences (UITS)

2

Dedication

To our Parents………..….

3

Declaration

It is hereby declared that this thesis or any part of it has not been submitted elsewhere for the award

of any degree or diploma.

Signature of the Supervisor:

Md.Qamarul Hasan

Signature of the Candidates:

Reduwan Ahmad Ashrafi

Md.Kazi Noman Arefin

Md.Shamsul Arfin

4

Acknowledgements

In the name of Allah, the Most Beneficent and Most Merciful.

First of all, we would like to thanks our parents for giving us effort and strength to achieve the

goals. We would like to special thanks to our supervisor, Md. Qamarul Hasan for his generous

support, comments, advice and guidance throughout the duration of our thesis. Without his

continuous support and interest, this thesis would not have been the same as presented here.

And last but not the least we express our hearty thanks to almighty Allah and all those who

supported us directly or indirectly to complete this task.

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Abstract

PLLs are critical for frequency accuracy in wireless systems, helping to minimize interchannel

interference (ICI) by limiting spectral spreading. In addition, time-division-multiple-access

(TDMA) cellular communications systems require synthesizers capable of tuning to a new channel

within a small fraction of each time slot. This leads to the need for minimal locking time. The

suppression of reference spurious signals and phase noise is also critical in modern digital

communications systems, as well as wide tuning range and good frequency stability. In this Thesis

paper here is discussing about the PLL fundamental elements, elements characteristics, basic

equation of PLL and analysis the PLL parameters with the help of MATLAB. In MATLAB

simulation test, here is analyzing the optimizing value of the PLL and desired lock time is 0.006ms.

In this Thesis analysis the effects shows phase noise, frequency output, phase error and phase

detector parameters in the performance.By using Kp=2,Fref=10000,No=800 and Fz=100, Fp1=0.001,

Fp2=1000 values get the more optimizing locking time will be 0.006ms .

.

6

Table of Contents

Abstract 6

Table of Contents 8,9,10,11,12

List of Tables 10

List of Figures 10,11,12

7

8

Chapter 1 Overview of PLL Frequency Synthesizer...…………….1

1.1 Frequency……………………………………………………………1

1.2 Frequency Synthesis…………………………………………………2

1.2.1 Synthesizer Types……………………………………………………3

1.3 Phase Locked (Indirect) Synthesizer………………………………...3

1.4 Basic Synthesizer phase locked loop………………………………...3

1.5 Basic Example ……..……………………………………………......4

1.6 Mathematical Representation of PLL…………………………..........4

1.7 Practical Consideration…………………………………………........5

Chapter 2 Mathematical representation of PLLs ……………...………6

2.1 Solution of the Basic PLL Equation in the Time Domain………....…9

2.1.1 Solution in the Closed Form……………………...……...................10

2.1.2 Linearized Solution……………………………………..……...…...10

2.2 Solution of the Basic PLL Equation in the frequency Domain…….10

2.3 Order and type of PLLs………………………………..…………..12

2.3.1 Order of PLLs……………………………………….……….……14

2.3.2 Type of PLLs…………………………………………..……….….14

2.3.3 Steady State Errors…………………………………..........….……15

2.3.3.1 Phase steps………………………………………...….…..........…15

2.3.3.2 Frequency steps…………………………………………...……...16

2.3.3.3 Frequency ramps…………………………………………..……...16

2.4 Block Diagram Algebra…………..…………………..…….........16

Chapter 3 Elements of PLL Frequency Synthesis.................................19

3.1 Phase Detector…………………………………………..………….19

3.1.1 Types of Phase Detector…………………………..…………..……20

3.1.1.1 Phase Only Sensitive Detector………………………….…………20

3.1.1.2 Phase Frequency Sensitive Detector……………………...………21

3.2 PLL Loop Filter………………………………..……………….….21

3.2.1 Loop Filter Type.................................................................................22

3.2.1.1 Passive Loop Filter………………………………………………..22

3.2.1.2 Active Loop Filter (Type A)…………………………………...…23

3.2.1.3 Active Loop Filter (Type B)………………………………...……23

3.3 Voltage Control Oscillator…………………………….……….…. …24

3.3.1 Types of VCOs…………………………………………………... ...24

3.3.1.1 Harmonic Oscillators…………………………….. ………………24

3.3.1.2 Relaxation Oscillators……………………………………..….…. 24

3.3.2 Comparison Between Harmonic Oscillator & Relaxation Oscillator25

Chapter 01Introduction to PLL Frequency Synthesis

A phase-locked loop (PLL) is a control system that tries to generate an output signal whose phase is

related to the phase of the input "reference" signal. It is an electronic circuit consisting of a variable

frequency oscillator and a phase detector that compares the phase of the signal derived from the

oscillator to an input signal. The signal from the phase detector is used to control the oscillator in a

feedback loop. The circuit compares the phase of the input signal with the phase of a signal derived

from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched.

Frequency is the derivative of phase. Keeping the input and output phase in lock step implies

keeping the input and output frequencies in lock step. Consequently, a phase-locked loop can track

an input frequency, or it can generate a frequency that is a multiple of the input frequency. The

former property is used for demodulation, and the latter property is used for indirect frequency

synthesis.

Phase-locked loops are widely used in radio, telecommunications, computers and other electronic

applications. They may generate stable frequencies, recover a signal from a noisy communication

channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Since a

single integrated circuit can provide a complete phase-locked-loop building block, the technique is

widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to

many giga hertz’s.

Phase-locked-loop (PLL) frequency synthesis is used throughout communications systems to

provide a stable source of carrier and baseband signals. Since a PLL can be considered a subsystem

within a larger communications system, it is appropriate to analyze this type of network with the

help of a system-level simulator. PLL synthesizer through the connection of its standard built-in

behavioral components, such as a voltage-controlled oscillator (VCO), phase detector, components

for loop filter design, reference oscillator and frequency divider. In this Chapter giving the basic

idea about PLL frequency synthesizer. [11]

13

1.1 FrequencyFrequency is typically considered as a parameter, such as voltage or current, which can be used in

defining the state of a system. But, in the study of frequency synthesis, a frequency can itself be

considered a state variable. As with voltages and currents, frequencies can be added and subtracted

in electronics circuits, and can be multiplied or divided by a constant. A frequency can also be

transformed to or from other variables. Since these are the basic processes that are used in

frequency synthesis. If a signal is periodic over a given interval, it have been say that it has an

instantaneous frequency defined, in that interval, as the reciprocal of the time between repetitions.

If the period is continuously changing, it can still often identity an instantaneous frequency. If the

signal is considered a constant-amplitude sine wave, there is a correspondence between

instantaneous magnitude and phase, and frequency is the time derivative of phase. Figure shows a

segment of a sine wave whose instantaneous frequency is .[4]

Figure 1.1 A Signal that is periodic over an interval

1.2 Frequency SynthesisA frequency synthesizer is an electronic system for generating any of a range of frequencies from a

single fixed time base or oscillator. They are found in many modern devices, including radio

receivers, mobile telephones, radiotelephones, walkie-talkies, CB radios, satellite receivers, GPS

systems, etc. A frequency synthesizer can combine frequency multiplication, frequency division,

and frequency mixing (the frequency mixing process generates sum and difference frequencies)

operations to produce the desired output signal.[3]

14

1.2.1 Synthesizer TypesThree types of synthesis can be distinguished. The first and second types are routinely found as

stand-alone architecture: Direct Analog Synthesis (also called a mix-filter-divide architecture as

found in the 1960s HP 5100A) and by comparison the more modern Direct Digital Synthesizer

(DDS) (Table-Look-Up). The third type is routinely used as communication system IC building-

blocks: indirect digital (PLL) synthesis including integer-N and fractional-N.[3]

1.3 Phase-Locked (Indirect) SynthesizerThe phase-locked (PL) synthesizer, in effect, multiples the reference frequency by a variable

number, it does so by dividing its output frequency by that variable number and adjusting the

output frequency so that, after division, it is equal to the reference frequency.

A phase locked loop is a feedback control system. It compares the phases of two input signals and

produces an error signal that is proportional to the difference between their phases. The error

signals are then low pass filtered and used to drive a voltage-controlled oscillator (VCO) which

creates an output frequency. The output frequency is fed through a frequency divider back to the

input of the system, producing a negative feedback loop. If the output frequency drifts, the phase

error signal will increase, driving the frequency in the opposite direction so as to reduce the error.

Thus the output is locked to the frequency at the other input. This other input is called the reference

and is usually derived from a crystal oscillator, which is very stable in frequency.[4]

1.4 Basic Synthesizer Phase-Locked Loop

Figure 1.2 Synthesizer phase-locked loops: Basic synthesizer Block Diagram

The block diagram below shows the basic elements and arrangement of a PLL based frequency

synthesizer. The key to the ability of a frequency synthesizer to generate multiple frequencies is the

15

divider placed between the output and the feedback input. This is usually in the form of a digital

counter, with the output signal acting as a clock signal. The counter is preset to some initial count

value, and counts down at each cycle of the clock signal. When it reaches zero, the counter output

changes state and the count value is reloaded. This circuit is straightforward to implement using

flip-flops, and because it is digital in nature, is very easy to interface to other digital components or

a microprocessor. This allows the frequency output by the synthesizer to be easily controlled by a

digital system. [7]

1.5 Basic ExampleSuppose the reference signal is 100 kHz, and the divider can be preset to any value between 1 and

100. The error signal produced by the comparator will only be zero when the output of the divider

is also 100 kHz. For this to be the case, the VCO must run at a frequency which is 100 kHz x the

divider count value. Thus it will produce an output of 100 kHz for a count of 1, 200 kHz for a count

of 2, 1 MHz for a count of 10 and so on. Note that only whole multiples of the reference frequency

can be obtained with the simplest integer N dividers. Fractional N dividers are readily available.

[14]

1.6 Mathematical Representation of PLLThe mathematical representation control-system representation of the loop is shown in Figure1.3.

The variable at the output is frequency. This is divided by N and subtracted from .The

difference frequency is integrated, which is shown in Laplace notation as division by s, to give

phase difference. The phase is converted to voltage in the phase detector. The ratio of voltage to

phase is expressed by .

Figure 1.3 Mathematical representation

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The phase –detector output voltage is multiplied by the loop-filter transfer function (s), and the

resulting voltage controls the frequency of the VCO. The ratio of frequency to control voltage is

given by .[13]

1.7 Practical ConsiderationsIn practice this type of frequency synthesizer cannot operate over a very wide range of frequencies,

because the comparator will have a limited bandwidth and may suffer from aliasing problems. This

would lead to false locking situations, or an inability to lock at all. In addition, it is hard to make a

high frequency VCO that operates over a very wide range. This is due to several factors, but the

primary restriction is the limited capacitance range of varactor diodes. However, in most systems

where a synthesizer is used, it is not after a huge range, but rather a finite number over some

defined range, such as a number of radio channels in a specific band [5].

Many radio applications require frequencies that are higher than can be directly input to the digital

counter. To overcome this, the entire counter could be constructed using high-speed logic such as

ECL, or more commonly, using a fast initial division stage called a prescaler which reduces the

frequency to a manageable level. Since the prescaler is part of the overall division ratio, a fixed

prescaler can cause problems designing a system with narrow channel spacing’s - typically

encountered in radio applications. This can be overcome using a dual-modulus prescaler.

Further practical aspects concern the amount of time the system can switch from channel to

channel, time to lock when first switched on, and how much noise there is in the output. All of

these are a function of the loop filter of the system, which is a low-pass filter placed between the

output of the frequency comparator and the input of the VCO. Usually the output of a frequency

comparator is in the form of short error pulses, but the input of the VCO must be a smooth noise-

free DC voltage. (Any noise on this signal naturally causes frequency modulation of the VCO.).

Heavy filtering will make the VCO slow to respond to changes, causing drift and slow response

time, but light filtering will produce noise and other problems with harmonics. Thus the design of

the filter is critical to the performance of the system and in fact the main area that a designer will

concentrate on when building a synthesizer system.[13]

17

Chapter 2Mathematical Representation of PLLs

The task of the PLLs is to maintain coherence between the input (reference) signal frequency, fi,

and the respective output frequency, fo, via phase comparison. Another feature of PLLs is the

filtering property, particularly with respect to the noise where its behavior recalls a very narrow

low-pass arrangement that is not to be realized by other means.[3]

Each PLL system is composed of four basic parts:

1. The reference generator (RG)

2. The phase detector (PD)

3. The low-pass filter FL (f) (in higher-order systems)

4. The voltage-controlled oscillator (VCO)

and works as a feedback system shown in Figure 2.1. Without any loss of generality, it may assume

that input and output signals are harmonic voltages with additional phase modulation

where φi(t) and φo(t) are slowly varying quantities.

Later it will prove that realization of the phase lock requires that input and output voltages must be

in quadrature that is, mutually shifted by π/2.

Phase detector (PD) is a nonlinear element of a different design and construction. For the present

discussion, it is assumed that the PD is a simple multiplier. In this case the corresponding output

voltage will be

where, Km is the transfer constant with the dimension [1/V]. After introduction of

eqs. (2.1) and (2.2) in the above relation,

18

(2.1)

(2.2)

(2.3)

(2.4)

Figure 2.1 Basic feedback network of PLL

In the simplest case it will assume that the low-pass filter removes the upper sideband with the

frequency ωi + ωo but leaves the lower sideband ωi − ωo without change. Evidently the VCO

tuning voltage will be

where it have introduced the so-called PD gain Kd = KmViVo of dimension [V/rad].

Note that the phase difference between the input and the output voltages is

Voltage v2(t) will change the free running frequency ωc of the VCO to

where the proportionality constant Ko is designated as the oscillator gain with the dimension [2π

Hz/V]. After integration of the above equation and introduction into relation (2.6), the phase

difference Ψ e(t) is,

19

(2.5)

(2.6)

(2.7)

(2.8)

This can be rearranged as follows:

and differentiation reveals

Where ωi−ω0 = △ω and Kd K0 = K. Note that K is indicated as the gain of the PLL with the

dimension [2πHz].

The conclusion that follows from the foregoing discussion is that the phase lock arrangement is

described with a nonlinear eq. (2.10), the solution of which for arbitrary values △ω and K is not

known. With certainty it state that for △ω/K >>1, an a periodic solution does not exist. This

conclusion testifies the phase plane arrangement (Figure. 2.2). Without an a periodic solution, the

feedback system in Figure. 1.1 cannot reach the phase stability, that is, the output frequency of the

VCO, ωo, will never be equal to the reference frequency ωi. However, the DC component in the

steering voltage v2 (t) reduces the original difference between frequencies

Figure 2.2 Plot of relation (2.10) in the phase plane for different ratios △ ωK [9,8]

20

(2.9)

(2.10)

(2.11)

2.1 Solution of the Basic PLL Equation in the Time DomainTo arrive at the solution it has to introduce some simplifications. Nevertheless, the gain more

insight into the problem.

2.1.1 Solution in the Closed FormIn the case, where △ω/K <<1, the differential eq. (2.10) has a solution after application and

separation of variables.

where, t 0 is a not-yet-defined integration constant. As long as K >△ω, the RHS will be imaginary

and with the assistance

It arrive at

and after computing tan(π/4 − Ψ e/2) the sought solution is

For the steady state, that is, for t →∞, the lhs of eq. (2.10) equals zero, with the result

21

(2.12)

(2.13)

(2.14)

(2.14)

(2.15))

(2.16))

2.1.2 Lineraized SolutionFrom the preceding analysis it conclude that the solution of the respective differential equation, in

the closed form, is very complicated even for a very simple PLL arrangement. Consequently, it

may suppose that for more sophisticated PLL systems it would be practically impossible. However,

the situation need not be so gloomy after the introduction of simplifications that are not far from

reality. In the first step it find that the time-dependent phase difference Ψe(t) at the output of the PD

in the closed PLL is small and prone to the simplification.

This assumption is supported with the reality that a lot of PDs are linear or nearly linear in the

working range .In such a case, the introduction of (2.18) into (2.10) results in the following

simplification:

where Ψ e 0 is the integration constant, that is, the phase at the start for t = 0. Further investigation

reveals that the phase difference in the steady state compensates the frequency difference

2.2 Solution of the Basic PLL Equation in the Frequency Domain

By assuming the phase difference Ψe (t), in the locked state, to be always smaller than π/2, the

result is the equality between input and output frequencies

In other words, the PLL system is permanently in the phase equilibrium. The situation being such,

it can rearrange relation (2.7) to

where the termK0 v20 shifts the VCO frequency ωo to be equal to the input frequency ωi (of (2.22)).

Evidently, in the steady state the following relation between the VCO free running frequency and

the locked frequency22

(2.17))

(2.18))

(2.19))

(2.20))

(2.21))

Combination with (1.23) reveals

where K = KdKo.

In the steady state the difference φe

is generally small. Consequently, it may apply the following linearization

and employ advantages of the Laplace transform (with a tacit assumption of the zero

initial conditions)

After rearrangement it arrive at the basic PLL transfer function Between input and PD output error.

or at

23

(2.22))

(2.23)

(2.24)

(2.25)

(2.26)

(2.27)

(2.28)

2.3 Order and Type of PLLsThe PLL system described with relations (2.29) and (2.30) is indicated as PLL of the first order

since the polynomial in the denominator is of the first order in s (K being a constant). However,

generally PLLs are much more complicated. To get better insight into the PLL properties, it will

simplify, without any loss of generality, the block diagram to that shown in figure 1.3 and introduce

the Laplace transfer functions of the individual building circuits, suitable for investigation of the

small signal properties. Investigation of the above Figure reveals that the input phase ϕi(t) is

compared with the output phase ϕo(t) in the phase detector (ring modulator, sampling circuit, etc.).

At its output voltage, vd(t), proportional to the phase difference of the respective input signals

where

the proportionality factor, Kd[V/rad], is called the phase detector gain.

Next, vd(t) passes the loop filter, F(s) (a low-pass filter attenuating “carriers” with frequencies ωi =

ωo, and ideally all undesired sidebands). Note that the useful signal v2(t) is a slowly varying “DC”

component, the output voltage of which is given by the following convolution,

where, hf(t) is the time response of the loop filter. After applying v2 (t) on the frequency control

element of the VCO, it get the output phase

With ωc being the VCO free-running frequency. The proportionality factor, Ko [2π Hz/V], is

designated as the oscillator gain. Since, in most cases, Kd and Ko are voltage-dependent, the

general mathematical model of a PLL is a nonlinear differential equation. Its linearization, justified

in small signal cases (“steady state” working modes), provides a good insight into the problem.

After reverting to the

24

(2.31)

(2.30)

(2.29)

Figure 2.3 Simplified block diagram of the PLL with individual transfer functions.

Figure 2.4 Simplified diagram of the PLL with a transfer function in the feedback path.

Whole feedback system (Figure. 2.4), it can write for the relation between the input and the output

phases in the Laplace transform notation

The ratio, Φo(s)/Φi(s), the PLL transfer function, is given by

25

(2.32)

where it have introduced the forward loop gain K = KdKo and the open loop gain G(s)

2.3.1 Order of PLLsIn the simplest case there are no filters in the forward or the feedback paths. The PLL transfer

function simplifies to

This PLL is designated as the first-order loop since the largest power of s in the polynomial of the

denominator is of the order one. Generally, the transfer functions of the loop filters F(s) are given

by a ratio of two polynomials in s. The consequence is that the denominator in H(s) is of a higher

order and speak about PLLs of the second order, third order, and so on, in accordance with the

order of the respective polynomial in the denominator of (1.35).

2.3.2 Type of PLLsIn instances in which the steady state errors are of major interest, the number of poles in the

transfer function G(s), that is, the number of integrators in the loop, is of importance. In principle,

every PLL has one integrator connected with the VCO (cf. eq. (2.33)). For the phase error at the

output of the PD it shown below

where,

After elimination of Φo(s) from the above relations, the phase error Φe(s)

26

(2.35)

(2.36)

(2.33)

(2.34)

(2.37)

Introducing the gain, G(s), which is a ratio of two polynomials

it get for the phase error

and eventually with the assistance of the Laplace limit theorem, the final value of the phase error

ϕe(t)

Note that every PLL contains at least one integrator, that is, VCO; consequently, n ≥ 1 [9, 4]

2.3.3 Steady State ErrorsInvestigations of the steady state errors in PLLs of different orders and types will proceed after

introduction of the Laplace transforms of the respective input phase steps, input frequency steps,

and input steady frequency changes into (2.43).

2.3.3.1 Phase StepsAfter introducing the Laplace transform of phase steps, △φ/s, into (2.43), it shown that the final

value is zero in all PLLs.

27

(2.38)

(2.39)

(2.40)

(2.41)

(2.42)

2.3.3.2 Frequency StepsFor the frequency steps, △ω/s, it is

Evidently in all PLLs of the second order, a frequency step results in a steady state phase error

inversely proportional to the so-called velocity error constant Kv, in agreement with the

terminology used in the feedback control systems.

In PLLs of type 2, with two integrators in the loop, the DC gain F (0) is very large, So Kv and

consequently the steady state error is negligible.[3, 4]

2.3.3.3 Frequency RampsHowever, the steady frequency change, △ω/S2, results in the so-called acceleration or dynamic

tracking error Ka

PLLs of type 3 can eliminate even the steady state error Φe3(t) for t →∞ to zero. However, PLLs of

this type are encountered exceptionally, for example, in time services, in space and satellite

devices, and so on.

Note that the frequency locked loop may be considered as 0 type PLL. [17]

2.4 Block Diagram AlgebraActual PLLs are often much more complicated than block diagrams in figures 2.3 or 2.4. For

arriving at transfer functions, H(s) and 1−H(s), by applying the rules of block diagram algebra.

Two or more blocks in series can be combined into one after multiplication of their Laplace

transform symbols shown in Figure. 2.5a. A typical example is the addition of independent sections

to the fundamental low-pass filter. In the case where two blocks are in parallel, the final

combination is provided with a mere addition (see Figure. 2.5b). Investigation of the relation (2.35)

reveals that the feedback block can be put outside of the basic loop

28

(2.43)

(2.44)

(2.45)

29

Figure 2.5 Simplification of the block diagrams of PLLs: (a) series connection; (b) parallel

Connection; (c) and (d) feedback arrangement; (e) more complicated system.

Or

In this way it arrive at the effective transfer functions, H(s) and 1 − H(s), which contain information

about the PLL filtering properties, which will be discussed later.

The approach in which a simple frequency divider or frequency multiplier is in the feedback path of

the PLL. The rearrangement is reproduced in Figure. 2.5(c) and Figure. 2.5(d).

Finally, it will consider the system containing a mixer in the feedback path.

Relation between output and input phases is

and rearrangement leads to the simplification in accordance with Figure 2.5(e).[16]

30

(2.46)

(2.47)

Chapter 3

Elements of PLL Frequency Synthesizer

The elements of frequency synthesizer consist of phase detector, low pass filter, voltage controlled

oscillator and frequency divider.

3.1 Phase Detector

The phase detector is the nucleus element of a phase locked loop. Its action enables the phase

differences in the loop to be detected and the resultant error voltage to be produced.

A phase detector provides an output voltage that is dependent on the phase difference between two

input signals. As shown in Figure 3.1, two input signals of nominally the same frequency (ω0) but

different phases(θ1∧θ2) are applied to the input ports of a hybrid coupler. The output voltages

developed across the mixer diodes can be written as

=

Figure 3.1 Circuit diagram for an analog phase detector.

Assume a square law response for the mixer diodes, and retain only the quadratic terms, the diode

currents can be written as

31

i1 (t )=k v12( t)

¿k [cos2 ( ω0+θ1 )−2cos (ω0t +θ1 ) sin (ω0t +θ2 )+sin2(ω0 t+θ2)]

i2 ( t )=−k v22(t)

¿−k [cos2 ( ω0+θ2 )−2cos (ω0t+θ2 ) sin (ω0 t+θ1 )+sin2(ω0 t+θ1)]

The negative sign on i2 accounts for the reversed diode polarity. After combining the diode currents

and low pass filtering, the output voltage can be expressed as

v0 ( t )=i1 ( t )+i2 ( t ) ⋮ LPF=kd sin (θ1−θ2 )

≈ k d(θ1−θ2)

This result shows that the output voltage of the phase detector is proportional to the sine of the

difference in phase of the two input signals. If this difference is small, then the sine function can be

approximated by its argument, so that the phase detector output is proportional to the phase

difference.[9,8]

3.1.1 Types of Phase Detector

There is a variety of different circuits that can be used as phase detectors, some that use what may

be considered as analogue techniques, while others use digital circuitry. However the most

important difference is whether the phase detector is sensitive to just phase or whether it is sensitive

to frequency and to phase. Thus phase detectors may be split into two categories:

Phase only sensitive detectors

Phase - frequency detectors [7,8]

3.1.1.1 Phase Only Sensitive Detectors

Phase detectors that are only sensitive to phase are the most straightforward form of detector. They

simply produce an output that is proportional to the phase difference between the two signals.

When the phase difference between the two incoming signals is steady, they produce a constant

voltage. When there is a frequency difference between the two signals, they produce a varying

voltage. In fact the simplest form of phase only sensitive detector is a mixer. From this it can be

seen that the output signal will be have sum and difference signals.

32

The difference frequency product is the one used to give the phase difference. It is quite possible

that the difference frequency signal will fall outside the pass-band of the loop filter. If this occurs

then no error voltage will be fed back to the Voltage Controlled Oscillator (VCO) to bring it into

lock. This means that there is a limited range over which the loop can be brought into lock, and this

is called the capture range. Once in lock the loop can generally be pulled over a much wider

frequency band.

To overcome this problem the oscillator must be steered close to the reference oscillator frequency.

This can be achieved in a number of ways. One is to reduce the tuning range of the oscillator so

that the difference product will always fall within the pass-band of the loop filter. In other instances

another tune voltage can be combined with the feedback from the loop to ensure that the oscillator

is in the correct region. This is approach is often adopted in microprocessor systems where the

correct voltage can be calculated for any given circumstance [7, 8].

3.1.1.2 Phase-Frequency Sensitive Detectors

Another form of detector is said to be phase-frequency sensitive. These circuits have the advantage

that whilst the phase difference is between +/- 180 a voltage proportional to the phase difference is

given. Beyond this the circuit limits at one of the extremes. In this way no AC component is

produced when the loop is out of lock and the output from the phase detector can pass through the

filter to bring the phase locked loop, PLL, into lock.

Detecting phase differences is very important in many applications, such as motor control, radar

and telecommunication systems, servo mechanisms, and demodulator.[7,8,9]

3.2 PLL Loop FilterThe design of the PLL, loop filter is vital to the operation of the whole phase locked loop. The

choice of the circuit values here is usually a very carefully balanced compromise between a

numbers of conflicting requirements.

The PLL filter is needed to remove any unwanted high frequency components which might pass

out of the phase detector and appear in the VCO tune line. They would then appear on the output of

the Voltage Controlled Oscillator, VCO, as spurious signals. To show how this happens take the

case when a mixer is used as a phase detector. When the loop is in lock the mixer will produce two

signals: the sum and difference frequencies. As the two signals entering the phase detector have the

33

same frequency the difference frequency is zero and a DC voltage is produced proportional to the

phase difference as expected. The sum frequency is also produced and this will fall at a point equal

to twice the frequency of the reference. If this signal is not attenuated it will reach the control

voltage input to the VCO and give rise to spurious signals.

When other types of phase detector are used similar spurious signals can be produced and the filter

is needed to remove them.

The filter also affects the ability of the loop to change frequencies quickly. If the filter has a very

low cut-off frequency then the changes in tune voltage will only take place slowly, and the VCO

will not be able to change its frequency as fast. This is because a filter with a low cut-off frequency

will only let low frequencies through and these correspond to slow changes in voltage level.

Conversely a filter with a higher cut-off frequency will enable the changes to happen faster.

However when using filters with high cut-off frequencies, care must be taken to ensure that

unwanted frequencies are not passed along the tune line with the result that spurious signal are

generated.

The loop filter also governs the stability of the loop. If the filter is not designed correctly then

oscillations can build up around the loop, and large signals will appear on the tune line. This will

result in the VCO being forced to sweep over wide bands of frequencies. The proper design of the

filter will ensure that this cannot happen under any circumstances.[5]

3.2.1 Loop Filter Type

There are three types of Loop Filter available.

Passive Loop Filter

Active Loop Filter (Type A)

Active Loop Filter (Type B)

3.2.1.1 Passive Loop Filter

Passive loop filter is generally suggested, provided that the PLL charge pump can supply a

sufficient voltage to operate the VCO tuning voltage. An advantage of Passive loop filter is the

lowest cost, lowest noise, and requires the least board area.

34

Figure 3.2 Passive loop filter

3.2.1.2 Active Loop Filter (Type A)

When an active loop filter is required, the Type A topology is suggested. Although this topology is

almost certainly fewer familiar for active filters, it is better since it allows the charge pump voltage

to be fixed in the application, giving better stimulate performance, and reducing the requirements

for input rails for the OPAMP used. As with any active filter, it has the added benefit of providing

isolation in the loop filter, such that the capacitor next to the VCO can be chosen larger, to reduce

the impact of the VCO input capacitance.

Figure 3.3 Active loop filter (Type A)

3.2.1.3 Active Loop Filter (Type B)

Active loop filter type B is generally not recommended, however, it is included because it is a more

popular topology and seems more perceptive to many people. For this type of active filter, a simple

gain stage is placed before the VCO. As with any active filter, it has the added benefit of providing

isolation in the loop filter, such that the capacitor next to the VCO can be chosen larger, to reduce

the impact of the VCO input capacitance.[5]

35

Figure 3.4 Active loop filter (Type B)

3.3 Voltage Controlled Oscillator

A voltage-controlled oscillator or VCO is an electronic oscillator designed to be controlled in

oscillation frequency by a voltage input. The frequency of oscillation is varied by the applied DC

voltage, while modulating signals may also be fed into the VCO to cause frequency modulation

(FM) or phase modulation (PM); a VCO with digital pulse output may similarly have its repetition

rate (FSK, PSK) or pulse width modulated (PWM).[9]

3.3.1 Types of VCOs

Based on the types of waveform VCOs can be normally categorized into two groups.

Harmonic Oscillators

Relaxation Oscillators

3.3.1.1 Harmonic Oscillators

These types of oscillators generate a sinusoidal waveform. They consist of an amplifier that

provides sufficient gain and a resonant circuit that feeds back signal to the input. Oscillation occurs

at the resonant frequency where a positive gain arises around the loop. Some examples of harmonic

oscillators are crystal oscillators and LC-tank oscillators. When part of the resonant circuit's

capacitance is provided by a varactor diode, the voltage applied to that diode varies the frequency.

[9]

3.3.1.2 Relaxation Oscillators

Relaxation oscillators can generate a saw tooth or triangular waveform. They are commonly used in

monolithic integrated circuits (ICs). They can provide a wide range of operational frequencies with

36

a minimal number of external components. Relaxation oscillator VCOs can have three topologies:

1) grounded-capacitor VCOs, 2) emitter-coupled VCOs, and 3) delay-based ring VCOs. The first

two of these types operate similarly. The amount of time in each state depends on the time for a

current to charge or discharge a capacitor. The delay-based ring VCO operates somewhat

differently however. For this type, the gain stages are connected in a ring. The output frequency is

then a function of the delay in each of stages.[9]

3.3.2 Comparison Between Harmonic Oscillator & Relaxation Oscillator

Harmonic oscillators VCOs have these advantages over relaxation oscillators:

Frequency stability with respect to temperature, noise, and power supply is much better for

harmonic oscillator VCOs.

They have good accuracy for frequency control since the frequency is controlled by a

crystal or tank circuit.

A disadvantage of harmonic oscillator VCOs is that they cannot be easily implemented in

monolithic ICs. Relaxation oscillator VCOs are better suited for this technology. Relaxation VCOs

are also tunable over a wider range of frequencies.

3.3.3 Control of Frequency in VCOs

A voltage-controlled capacitor is one method of making an LC oscillator vary its frequency in

response to a control voltage. Any reverse-biased semiconductor diode displays a measure of

voltage-dependent capacitance and can be used to change the frequency of an oscillator by varying

a control voltage applied to the diode. Special-purpose variable capacitance varactor diodes are

available with well-characterized wide-ranging values of capacitance. Such devices are very

convenient in the manufacture of voltage-controlled oscillators for low-frequency VCOs; other

methods of varying the frequency (such as altering the charging rate of a capacitor by means of a

voltage controlled current source) are used. See Function generator.

The frequency of a ring oscillator is controlled by varying either the supply voltage or the

capacitive loading on each stage.

37

Figure 3.5 Voltage controlled oscillator schematic

3.3.4 Voltage-Controlled Crystal Oscillators

A voltage-controlled crystal oscillator (VCXO) is used when the frequency of operation needs to

be adjusted only finely. The frequency of a voltage-controlled crystal oscillator can be varied only

by typically a few tens of parts per million (ppm), because the high Q factor of the crystals allows

"pulling" over only a small range of frequencies.

There are two reasons for using a VCXO:

To adjust the output frequency to match (or perhaps be some exact multiple of) an accurate

external reference.

Where the oscillator drives equipment that may generate radio-frequency interference,

adding a varying voltage to its control input can disperse the interference spectrum to make

it less objectionable. See spread-spectrum clock generation.

A temperature-compensated VCXO (TCVCXO) incorporates components that partially correct the

dependence on temperature of the resonant frequency of the crystal. A smaller range of voltage

control then suffices to stabilize the oscillator frequency in applications where temperature varies,

such as heat buildup inside a transmitter.[11]

3.3.5 Transfer Function for the VCO Oscillator

In order to analyze a phase locked loop system, it must model the voltage controlled oscillator in

terms of the transfer function between its control voltage and the phase of the output waveform. Let

VCO output has ω0 that is offset from its free running frequencyωc, and increment △𝝎;ω0=ωc+△ω=ωc+K 0 vc

38

Where the offset is controlled by the control voltage vc applied to the VCO.The contant K 0 is the

VCO gain factor and has dimensions of Hz/V. Figure 3.6 illustrates this VCO model [1 - 3].

Figure.3.6 A voltage controlled oscillator

it define the phase of the offset frequency of the VCO as θ0 ( t )=△ωt=k0 vc t

This can be inverted to express the output phase in terms of the control voltage as

dθ0(t )

dt=△ω=k 0 vc which can be inverted to express the output phase in terms of the control

voltage asθ0 (t )=k 0 ∫t =0

t

vc (t ) dt In the Laplace transform domain this can be written as

Θ0 (s )=k0

svc (s ) Which is the desired transfer function for the VCO.[11]

3.3.6 Applications

VCOs are used in:

Electronic jamming equipment

Function generators,

The production of electronic music, to generate variable tones,

Phase-locked loops,

Frequency synthesizers used in communication equipment.

3.3.7 A Voltage Controlled Oscillator Frequency

A VCO output frequency is stabilized or controlled with a Resonator. The lower the close-in Phase

Noise requirement, the higher the Quality Factor (Q) of the Resonator needs to be. A Resonator can

be as simple as an Inductor or as complex as a Quartz Crystal. The Table below lists some of the

most popular Resonator types with their accompanying typical Q value in ascending order.

39

A cos (ωc t+△ωt )vc

Table 3.1 Resonator types with their Quality factor

3.4 Frequency Divider

A frequency divider also called a clock divider or scaler or prescaler, is a circuit that

takes an input signal of a frequency, fin, and generates an output signal of a

frequency:

where n is an integer. Phase-locked loop frequency synthesizers make use of frequency dividers to

generate a frequency that is a multiple of a reference frequency. Frequency dividers can be

implemented for both analog and digital applications.[11]

3.4.1 Analog Dividers

Analog frequency dividers are really something special and nowadays used only at very high

frequencies. Digital dividers implemented in modern IC technologies can work up to tens of GHz.

3.4.1.1 Regenerative Frequency Divider

A regenerative frequency divider, also known as a Miller frequency divider, mixes the input signal

with the feedback signal from the mixer.

40

Figure 3.7Regenerative frequency divider

The feedback signal is fin / 2. This produces sum and difference frequencies fin / 2, 3fin / 2 at the

output of the mixer. A low pass filter removes the higher frequency and the fin / 2 frequencies is

amplified and fed back into mixer.

Steady state examination seems simple enough however startup is more complicated. In order to

establish a stable 1/2 frequency feedback, the amplifier gain at the half frequency must be greater

than unity. The phase shift must also be an integer multiple of 2pi.[11]

3.4.1.2 Injection-Locked Frequency Divider

A free-running oscillator which has a small amount of a higher-frequency signal fed to it will tend

to oscillate in step with the input signal. Such frequency dividers were essential in the development

of television.

It operates similarly to an injection locked oscillator. In an injection locked frequency divider, the

frequency of the input signal is a multiple (or fraction) of the free-running frequency of the

oscillator. While these frequency dividers tend to be lower power than broadband static (or flip-flop

based) frequency dividers, the drawback is their low locking range. The ILFD locking range is

inversely proportional to the quality factor (Q) of the oscillator tank. In integrated circuit designs,

this makes an ILFD sensitive to process variations. Care must be taken to ensure the tuning range

of the driving circuit (for example, a voltage-controlled oscillator) must fall within the input

locking range of the ILFD.[11]

3.4.2 Digital Dividers

For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal.

The least-significant output bit alternates at the same rate as the input, the next bit is the 1/2 the

rate, the third bit is 1/4 the rate, etc. An arrangement of flip-flops are a classic method for integer-n 41

division. Such division is frequency and phase coherent to the source over environmental variations

including temperature. The easiest configure ration is a series where each flip-flop is a divide-by-2.

For a series of three of these, such system would be a divide-by-8. By adding additional logic gates

to the chain of flip flops, other division ratios can be obtained. Integrated circuit logic families can

provide a single chip solution for some common division ratios.

Another popular circuit to divide a digital signal by an even integer multiple is a Johnson counter.

This is a type of shift register network that is clocked by the input signal. The last register's

complemented output is fed back to the first register's input. The output signal is derived from one

or more of the register outputs. For example, a divide-by-6 divider can be constructed with a 3-

register Johnson counter. The three valid values for each register are 000, 100, 110, 111, 011, and

001. This pattern repeats each time the network is clocked by the input signal. The output of each

register is a f/6 square wave with 60° of phase shift between registers. Additional registers can be

added to provide additional integer divisors.[12]

3.4.2.1 Mixed Signal Division

An arrangement of D flip-flops are a classic method for integer-n division. Such division is

frequency and phase coherent to the source over environmental variations including temperature.

The easiest configure ration is a series where each D flip-flop is a divide-by-2. For a series of three

of these, such system would be a divide-by-8. More complicated configure rations have been found

that generate odd factors such as a divide-by-5. Standard, classic logic chips that implement this or

similar frequency division functions include the 7456, 7457, 74292, and 74294.[13]

3.4.3 Fractional-n Dividers

A fractional-n frequency synthesizer can be constructed using two integer dividers, a divide-by-n and a divide-by-(n + 1) frequency divider. With a modulus controller, n is toggled between the two values so that the VCO alternates between one locked frequency and the other. The VCO stabilizes at a frequency that is the time average of the two locked frequencies. By varying the percentage of time the frequency divider spends at the two divider values, the frequency of the locked VCO can be selected with very fine granularity.[13]

42

Chapter 4

PLL Phase Noise

Synthesizer PLL phase noise is a particularly important parameter for any phase locked loop based

frequency synthesizer. Although key parameters like frequency stability, frequency range and

synthesizer step size, and frequency range are widely quoted in specification sheets for

synthesizers, the phase noise is equally important. The phase noise of a PLL frequency synthesizer

is important for many reasons. It affects the performance of the equipment in which the synthesizer

is used in a number of ways. For signal generators a clean source is needed for the tests in which

the generator may be used. If the frequency synthesizer is used in a radio communications system,

then it will affect the performance of the system. For a radio receiver used in a radio

communications system it will affect parameters such as reciprocal mixing and under some

conditions the noise floor. If the frequency synthesizer is used in a transmitter, then it can cause

wide-band noise to be transmitted and this could cause interference to other users. Accordingly for

any radio communications application, the level of phase noise is important. As the majority of the

phase noise is likely to be generated by the synthesizer, PLL phase noise characteristics are of great

importance. [14]

Figure 4.1 PLL response on phase noise

43

4.1 Phase Noise

Phase noise is present on all signals to some degree and it is caused by small phase (and hence

frequency) perturbations or jitter on the signal. It manifests itself as noise spreading out either side

from the main carrier

Figure 4.2 PLL phase noise

Some signal sources are better than others. Crystal oscillators are very good and have very low

levels of phase noise. Free running variable frequency oscillators normally perform well.

Unfortunately synthesizers, and especially those based around phase locked loops, do not always

fare so well unless they are well designed. If significant levels of phase noise are present on a

synthesizer used as a local oscillator in a receiver, it can adversely affect the performance of the

radio in terms of reciprocal mixing.[14]

4.2 Phase Noise in Synthesizers

Each of the components in a frequency synthesizer produces noise that will contribute to the overall

noise that appears at the output. The actual way in which the noise from any one element in the

loop contributes to the output will depend upon where it is produced. Noise generated by the VCO

will affect the output in a different way to that generated in the phase detector for example.

To see how this happens take the example of noise generated by the voltage controlled oscillator.

This will pass through the divider chain and appear at the output of the phase detector. It will then

44

have to pass through the loop filter. This will only allow through those components of the noise that

are below the loop cut-off frequency. These will appear on the error voltage and have the effect of

cancelling out the noise on the voltage controlled oscillator. As this effect will only take place

within the loop bandwidth, it will reduce the level of noise within the loop bandwidth and have no

effect on noise outside the loop bandwidth. Noise generated by the phase detector is affected in a

different way. Again only the components of the noise below the loop bandwidth will pass through

the low pass filter. This means that there will be no components outside the loop bandwidth

appearing on the tune voltage at the control terminal of the voltage controlled oscillator, and there

will be no effect on the oscillator. Those components inside the loop bandwidth will appear at the

oscillator control terminal. These will affect the oscillator and appear as phase noise on the output

of the voltage controlled oscillator. Matters are made worse by the fact that the division ratio has

the effect of multiplying the noise level. This arises because the synthesizer effectively has the

effect of multiplying the frequency of the reference. Consequently the noise level is also multiplied

by a factor of 20 log N, where N is the division ratio. Noise generated by the reference undergoes

exactly the same treatments as that generated by the phase detector. It too is multiplied by the

division ratio of the loop in the same way that the phase detector noise is. This means that even

though the reference oscillator may have a very good phase noise performance this can be degraded

significantly, especially if division ratios are high. Dividers normally do not produce a significant

noise contribution. Any noise they produce may be combined with that of the phase detector. The

combined noise of the loop at the output generally looks like that shown in Figure 2. Here it can be

seen that the noise within the loop bandwidth arises from the phase detector and the reference.

Outside the loop bandwidth it arises primarily from the voltage controlled oscillator. From this it

can be seen that optimization of the noise profile is heavily dependent upon the choice of the loop

bandwidth. It is also necessary to keep the division ratio in any loop down to reasonable levels. For

example a 150 MHz synthesizer with a 12.5 kHz step size will require a division ratio of 12000. In

turn this will degrade the phase detector and reference phase noise Figure by 81 dB inside the loop

bandwidth - a significant degradation by anyone's standards! Provided that division ratios are not

too high then a wide loop bandwidth can help keep the voltage controlled oscillator noise levels

down as well.[14]

45

Figure 4.3 Noise profile of a typical synthesizer

4.3 Effects of the Phase Noise

PLL phase noise can affect different systems in different ways. However it is important that for all

applications the phase noise on the signal is known and within the required limits. However phase

noise can give rise to a number of different problems:

Wideband transmitted noise. When PLL frequency synthesizers are used within a

transmitter, a local oscillator source with large amounts of phase noise can be radiated away

from the wanted frequency band. This is transmitted as wideband noise and can cause

interference to other users nearby.

Increase in bit error rate. For transmissions using phase modulation, the phase jitter or

phase noise can cause errors in the reception of the data. PLL phase noise in both the

transmitter and receiver can increase the occurrence of bit errors. It is therefore essential

that the PLL phase noise is kept to acceptable limits within both the transmitter and

receiver.

Reciprocal mixing. This is a problem that occurs when the phase noise from the local

oscillator signal is superimposed onto a strong off channel signal. This phase noise then

masks out the much lower level weaker signal.[10]

46

4.4 PLL Phase Noise Measurement

Some oscillators have phase noise levels that are quoted in their specifications. Any high quality

signal generator will have the level of phase noise specified, as do many high performance crystal

oscillators used as standards. Their performance is generally specified in dB c/Hz and at a given

offset from the carrier. The term dB c simply refers to the level of noise relative to the carrier, i.e. -

10 dB c means that the level is 10 lower than the carrier. The bandwidth in which the noise is

measured also has to be specified. The reason for this is that noise spreads over the frequency

spectrum. Obviously the wider bandwidth that is used, the greater the level of noise that will pass

through the filter and be measured. To prove this, just try selecting a different bandwidth on a

receiver and check what happens to the noise level. It will rise for a wider bandwidth and fall when

a narrow bandwidth is used. Technically the most convenient bandwidth to use a 1 Hz bandwidth

and so this is used. When measuring this wider bandwidth is usually used because it is difficult to

obtain 1 Hz bandwidth filters and a correction is made mathematically .Finally the level of noise

varies as different offsets from the carrier are taken. Accordingly this must be included in a

specification. A very good oscillator might have a specification of -100 dB c/Hz at 10 kHz offset .It

has already been mentioned that the level of phase noise changes as the offset from the carrier

changes and for "simple" signal sources like crystal oscillators or variable frequency oscillators the

phase noise reduces as the frequency from the main carrier is increased.[10]

4.5 VCO Phase Noise

VCO phase noise is a key parameter in the voltage controlled oscillator used for applications

including use in frequency synthesizers for radio receivers, transmitters and RF signal generators.

VCO phase noise is a key specification parameter for any VCO design as the phase noise

performance of a VCO will affect the overall performance of the system in which the oscillator is

located.

Poor levels of VCO phase noise can manifest themselves in different ways. For an analogue radio

receiver a poor performance oscillator may result in poor reciprocal mixing performance. It may

also raise the noise floor of the receiver. In a radio system relying on phase modulation, phase noise

will degrade the bit error rate performance.

47

For transmitters, a poor level of phase noise performance will result in noise being transmitted

beyond the required transmit band, causing interference to users on other frequencies. Again it can

result in poor levels of bit error rate in a radio communications system.

Additional RF signal generators will look for as "clean" a signal as possible. Phase noise if a key

parameter for the performance of the signal generator, and in turn the VCO phase noise

performance is elemental in determining areas of the overall phase noise performance.[14,10]

Figure 4.4 Phase noise for a free-running VCO and a PLL connected VCO

4.5.1 VCO Phase Noise Basics

Phase noise is present on all signal sources to a greater or lesser degree. Some forms of oscillator

are better than others, those that use higher Q circuits and have smaller tuning ranges tend to offer a

better phase noise performance, however the requirements for VCOs tend to require wide tuning

ranges, and this makes their design more challenging.

The noise performance of the oscillator is of particular importance. This is because the noise

performance of the synthesizer outside the loop is totally governed by its performance. In addition

to this its performance may influence decisions about other areas of the circuit.

The typical noise outline for a VCO is flat at large frequency offsets from the carrier. It is

determined largely by factors such as the noise Figure of the active device. The performance of this

area of the oscillator operation can be optimized by ensuring the circuit is running under the

48

optimum noise performance conditions. Another approach is to increase the power level of the

circuit so that the signal to noise ratio improves.

Closer in the noise starts to rise, initially at a rate of 20 dB per decade. The point at which this starts

to rise is determined mainly by the Q of the oscillator circuit. A high Q circuit will ensure a good

noise performance. Unfortunately VCOs have an inherently low Q because of the Q of the tuning

varactors normally employed. Performance can be improved by increasing the Q, but this often

results in the coverage of the oscillator being reduced.

Still further in towards the carrier the noise level starts to rise even faster at a rate of 30 dB per

decade. This results from flicker or 1/f noise. This can be improved by increasing the level of low

frequency feedback in the oscillator circuit. In a standard bipolar circuit a small un-bypassed

resistor in the emitter circuit can give significant improvements.

To be able to assess the performance of the whole loop it is necessary to assess the performance of

the oscillator once it has been designed and optimized. Whilst there are a number of methods of

achieving this the most successful is generally to place the oscillator into a loop having a narrow

bandwidth and then measure its performance with a spectrum analyzer. By holding the oscillator

steady this can be achieved relatively easily. However the results are only valid outside the loop

bandwidth. However a test loop is likely to have a much narrower bandwidth than the loop being

designed the noise levels in the area of interest will be unaltered.[14,10]

4.5.2 Low Phase Noise VCO Design Key Points

To ensure that a design provides the optimum VCO phase noise performance, there are a number of

key points that can be followed in the design. These will help ensure that the design is able to

provide a high level of VCO phase noise performance, although even when the design has been

realized, there is still likely to be some optimization required to provide the best performance.

High Q resonant circuit. One of the major factors in determining the VCO phase noise

performance is the Q of the resonant circuit. Broadly, the higher the Q of the oscillator

tuned circuit, the better the VCO phase noise performance. Thus inductors should be chosen

to provide the highest Q, as should the capacitors. This is particularly true of voltage

controlled oscillators, VCOs where the varactor diodes normally employed have a lower Q

than other capacitors. Typically high Q tuned circuits do not have the tuning range of lower

Q circuits. This means that when wide tuning ranges are required, it becomes more difficult 49

to obtain a high level of Q and hence the optimum phase noise. As an illustration of the

effect of having a high Q resonant circuit in an oscillator, crystal oscillators exhibit very low

levels of phase noise as a result of the fact that the crystals used in them possess very high

levels of Q.

Choice of oscillator device. It is possible to use both bipolar devices and FETs within an RF

oscillator, using the same basic circuit topologies. The bipolar transistor has a low input

impedance and is current driven, while the FET has a high input impedance and is voltage

driven. The high input impedance of the FET is able to better maintain the Q of the tuned

circuit and this should give a better level of performance in terms of the phase noise

performance where the maintenance of the Q of the tuned circuit is a key factor in the

reduction of phase noise. That said, many bipolar transistor designs are able to offer

excellent phase noise performance .Another major factor is the flicker noise generated by

the devices. Oscillators are highly non-linear circuits and as a result the flicker noise is

modulated onto the oscillation as sidebands. This manifests itself as VCO phase noise. In

general bipolar transistors offer a lower level of flicker noise and as a result oscillators

based around them often offer a superior phase noise performance.

Correct feedback level. A critical feature in any oscillator design is to ensure that the

correct level of feedback is maintained. There should be sufficient to ensure that oscillation

is maintained over the frequency range, over the envisaged temperature range and to

accommodate the gain and parameter variations between the devices used. However if the

level of feedback is too high, then the level of VCO phase noise will also be increased. Thus

the circuit should be designed to provide sufficient feedback for reliable operation and little

more.

Sufficient oscillator power output.  It is found that the noise floor of an oscillator is

reasonably constant in absolute terms despite the level of the output signal. In some designs

there can be improvements in the overall signal to noise floor level to be made by using a

high level signal and applying this directly to the mixer or other circuit where it may be

required. Accordingly some low noise circuits may use surprisingly high oscillator power

levels.

Power line rejection.  It is necessary to ensure that any supply line or other extraneous

noise is not presented to the oscillator. Supply line ripple, or other unwanted pickup can

seriously degrade the performance of the oscillator. To overcome this, good supply

smoothing and regulation is absolutely necessary. Additionally it may be advisable to place

the oscillator within a screened environment so that it does not pick up any stray noise. It is

50

worth remembering that the oscillator acts as a high gain amplifier, especially close to the

resonant frequency. Any noise picked up can be amplified and will manifest itself as VCO

phase noise.[2,10,14]

4.6 Effects of Multiplication

As noise is generated at different points around the loop it is necessary to discover what effect this

has on the output. As a result it is necessary to relate all the effects back to the VCO. Apart from

the different elements in the loop affecting the noise at the output in different ways, the effect of the

multiplication in the loop also has an effect. The effect of multiplication is very important. It is

found that the level of phase noise from some areas is increased in line with the multiplication

factor (i.e. the ratio of the final output frequency to the phase comparison frequency). In fact it is

increased by a factor of 20 log10 N where N is the multiplication factor. The VCO is unaffected by

this, but any noise from the reference and phase detector undergoes this amount of degradation.

Even very good reference signals can be a major source of noise if the multiplication factor is high.

For example a loop which has a divider set to 200 will multiply the noise of the reference and phase

detector by 46 dB. From this information it is possible to build up a picture of the performance of

the synthesizer. Generally this will look like the outline shown in Figure. 6. From this it can be seen

that the noise inside the loop bandwidth is due mainly to components like the phase detector and

reference, whilst outside the loop the VCO generates the noise. A slight hump is generally seen at

the point where the loop filter cuts off and the loop gain falls to unity. By predicting the

performance of the loop it is possible to optimize the performance or look at areas which can be

addressed to improve the performance of the whole synthesizer before the loop is even built. In

order to analyze the loop further it is necessary to look at each circuit block in turn.[10]

4.7 Reference

The noise performance of the reference follows the same outlines as those for the VCO, but the

performance is naturally far better. The reason for this is that the Q of the crystal is many orders of

magnitude higher than that of the tuned circuit in the VCO. Typically it is possible to achieve

Figure of -110 dB c/Hz at 10 Hz from the carrier and 140 dB c/Hz at 1 kHz from a crystal oven.

Figure of this order are quite satisfactory for most applications. If lower levels of reference noise

are required these can be obtain, but at a cost. In instances where large multiplication factors are

necessary a low noise reference may be the only option. However as a result of the cost they should

51

be avoided wherever possible. Plots of typical levels of phase noise are often available with crystal

ovens giving an accurate guide to the level of phase noise generated by the reference.[8]

4.8 Frequency Divider

Divider noise appears within the loop bandwidth. Fortunately the levels of noise generated within

the divider are normally quite low. If an analysis is required then it will be found that noise is

generated at different points within the divider each of which will be subject to a different

multiplication factor dependent upon where in the divider it is generated and the division ratio

employed from that point. Theoretically, the primary function of a frequency divider (÷N, where N

is an integer) is very simple. The output frequency is equal to 1/N of the input frequency, and the

phase noise of the output signal is also equal to 1/N of that of the input signal. However, it may not

be so simple, to measure the residual phase noise generated by a frequency divider. The residual

noise can be understood conceptually as the excess noise generated and added to the inside of a

device (a frequency divider or a prescaler).

Figure 4.4 Residual phase noise in a frequency divider

Most divider chains use several dividers and if an approximate analysis is to be performed it may

be more convenient to only consider the last device or devices in the chain as these will contribute

most to the noise. However the noise is generally difficult to measure and will be seen with that

generated by the phase detector.[10]

52

4.9 Phase Detector

Like the reference signal the phase detector performance is crucial in determining the noise

performance within the loop bandwidth. There are a number of different types of phase detector.

The two main categories are analogue and digital. Mixers are used to give analogue phase

detectors. If the output signal to noise ratio is to be as good as possible then it is necessary to ensure

that the input signal levels are as high as possible within the operating limits of the mixer. Typically

the signal input may be limited to around -10 dB m and the local oscillator input to +10 dB m. In

some instances higher level mixers may be used with local oscillator levels of +17 dB m or higher.

The mixer should also be chosen to have a low NTR (noise temperature ratio). As the output is DC

coupled it is necessary to have a low output load resistance to prevent a backward bias developing. This could offset the operation of the mixer and reduce its noise performance. It is possible to calculate the theoretical noise performance of the mixer under optimum conditions.

An analogue mixer is likely to give a noise level of around -153 dB c/Hz. There are a variety of

digital phase detectors which can be used. In theory these give a better noise performance than the

analogue counterpart. At best a simple OR gate type will give Figure about 10 dB better than an

analogue detector and an edge triggered type (e.g. a dual D type or similar) will give a performance

of around 5 dB better than the analogue detector. These Figure are the theoretical optimum and

should be treated as guide although they are sufficient for initial noise estimates. In practice other

factors may mean that the Figure are different. A variety of factors including power supply noise,

circuit layout etc. can degrade the performance from the ideal. If very accurate measurements are

required then results from the previous use of the circuit, or from a special test loop can provide the

required results.[17]

4.10 Loop Filter

There are a variety of parameters within the area of the loop filter which affect the noise

performance of the loop. The break points of the filter and the unity gain point of the loop

determined by the filter govern the noise profile. In terms of contributions to the noise in the loop

the major source is likely to occur if an operational amplifier is used. If this is the case a low noise

variety must be used otherwise the filter will give a large contribution to the loop phase noise

profile. This noise is often viewed as combined with that from the phase detector, appearing to

degrade its performance from the ideal.[17]

53

4.11 Plotting Performance

Having investigated the noise components from each element in the loop, it is possible to construct

a picture of how the whole loop will perform. Whilst this can performed mathematically, a simple

graphical approach quickly reveals an estimate of the performance and shows which are the major

elements which contribute to the noise. In this way some re-design can be undertaken before the

design is constructed, enabling the best option to be chosen on the drawing board. Naturally it is

likely to need some optimization once it has been built, but this method enables the design to be

made as close as possible beforehand. First it is necessary to obtain the loop response. This is

dependent upon a variety of factors including the gain around the loop and the loop filter response.

For stability the loop gain must fall at a rate of 20 dB per decade (6 dB per octave) at the unity gain

point. Provided this criterion is met a wide variety of filters can be used. Often it is useful to have

the loop response rise at a greater rate than this inside the loop bandwidth. By doing this the VCO

noise can be attenuated further. Outside the loop bandwidth a greater fall off rate can aid suppress

the unwanted reference sidebands further. From knowledge of the loop filter chosen the break

points can be calculated and with knowledge of the loop gain the total loop response can be plotted.

With the response known the components from the individual blocks in the loop can be added as

they will be affected by the loop and seen at the output. First take the VCO. Outside the loop

bandwidth its noise characteristic is unmodified. However once inside this point the action of the

loop attenuates the noise, first at a rate of 20 dB per decade, and then at a rate of 40 dB per decade.

The overall effect of this is to modify the response of the characteristic as shown in Figure. 10. It is

seen that outside the loop bandwidth the noise profile is left unmodified. Far out the noise is flat,

but further in the VCO noise raises at the rate of 20 dB per decade. Inside the loop bandwidth the

VCO noise will be attenuated first at the rate of 20 dB per decade, which in this case gives a flat

noise profile. Then as the loop gain increases at the filter break point, to 40 dB per decade this

gives a fall in the VCO noise profile of -20 dB per decade. However further in the profile of the

stand alone VCO noise rises to -30dB per decade. The action of the loop gives an overall fall of -10

dB per decade. The effects of the other significant contributions can be calculated. The reference

response can easily be deduced from the manufacturer’s Figure. Once obtained these must have the

effect of the loop multiplication factor added. Once this has been calculated the effect of the loop

can be added. Inside the loop there is no effect on the noise characteristic, however outside this

frequency it will attenuate the reference noise, first at a rate of 20 dB per decade and then after the

filter break point at 40 dB per decade. The other major contributor to the loop noise is the phase

54

detector. The effect of this is treated in the same way as the reference, having the effect of the loop

multiplication added and then being attenuated outside the loop bandwidth. Once all the individual

curves have been generated they can be combined onto a single plot to gain a full picture of the

performance of the synthesizer. When doing this it should be remembered that it is necessary to

produce the RMS sum of the components because the noise sources are not correlated. Once this

has been done then it is possible to optimize the performance by changing factors like the loop

bandwidth, multiplication factor and possibly the loop topology to obtain the best performance and

ensure that the required specifications are met. In most cases the loop bandwidth is chosen so that a

relatively smooth transition is made between the noise contributions inside and outside the loop.

This normally corresponds to lowest overall noise situation.[12]

4.12 Low Phase Noise Frequency Synthesizer Design

Phase noise in PLL frequency synthesizers if of great importance because it determines many

factors about the equipment into which it is incorporated. For receivers it determines the reciprocal

mixing performance, and in some circumstances the bit error rate. In transmitters the phase noise

performance of the frequency synthesizer determines features such as adjacent channel noise and it

contributes to the bit error rate for the whole system. Phase noise is generated at different points

around the synthesizer loop and depending upon where it is generated it affects the output in

different ways. For example, noise generated by the VCO has a different effect to that generated by

the phase detector. This illustrates that it is necessary to look at the noise performance of each

circuit block in the loop when designing the synthesizer so that the best noise performance is

obtained. Apart from ensuring that the noise from each part of the circuit is reduced to an absolute

minimum, it is the loop filter which has the most effect on the final performance of the circuit

because it determines the break frequencies where noise from different parts of the circuit start to

affect the output. To see how this happens take the example of noise from the VCO. Noise from the

oscillator is divided by the divider chain and appears at the phase detector. Here it appears as small

perturbations in the phase of the signal and emerges at the output of the phase detector. When it

comes to the loop filter only those frequencies which are below its cut-off point appear at the

control terminal of the VCO to correct or eliminate the noise. From this it can be seen that VCO

noise which is within the loop bandwidth is attenuated, but that which is outside the loop

bandwidth is left unchanged. The situation is slightly different for noise generated by the reference.

This enters the phase detector and again passes through it to the loop filter where the components

below the cut-off frequency are allowed through and appear on the control terminal of the VCO.

55

Chapter 5Charge Pump Phase Detector

Since the most popular phase detector type is both a charge-pump phase detector and a phase

frequency detector (PFD) [Motorola, 1972], the terms “charges pump PD” and “PFD,” are

sometimes used interchangeably. The PFD acts as a phase detector during lock and provides a

frequency sensitive signal to aid acquisition when the loop is out of lock. The charge pump is so

named because it is supposed to deliver a charge proportional to phase error to the loop filter. The

combination is available in IC form, consisting of logic circuitry (including signals that can drive a

charge pump) plus, in some versions., parts of the charge pump and amplifier (see Figure. 5.1),and

is widely used in large scale integration (LSI) synthesizer circuits. Since there are PFDs that are not

charge pump PDs, it will be clearer if refer to this PD as a charge pump PD or a charge pump PFD.

Since the frequency detection aspect of the circuit is important as an acquisition aid.[4]

Figure 5.1 Charge-pump phase detector.

5.1 Operation of the Charge Pump in the Linear RangeOperation of the charge pump PD is illustrated by the waveforms of Figure. 5.2.There is three

output states: positive current, negative current, and no current. The impulses shown will. In

practice, correspond to the triggering edges of waveforms. The inputs and outputs are named in a

manner consistent with operation of a simple phase locked loop (PLL) (in which a higher voltage

from the PD causes a higher frequency into the variable divider, RD for input from the PD causes a 56

higher frequency into the variable divider, CU for charge up, and CD for charge down.CU causes

positive current out and CD causes negative current out.

Figure 5.2 Charge-pump phase detector waveform with high VCO frequency

RD causes the output to change in a positive direction .unless the positive output is already

positive, in which case the pulse has no effect. Similarly, VD causes a negative transition unless the

output is already negative. These transitions may consist of turning the current on or turning it off.

The result is illustrated in the lower waveform for a case where the divider output frequency is

higher than the reference frequency. The loop filter will contain a low pass structure that will

convert the series of pluses into something more like their average value, or a voltage proportional

to the average current. Figure 5.3 is a plot of the average current output verses phase. Note that the

phase range is 720 degree and if, due to, let us say, a minute frequency difference between inputs,

the output voltage reaches an extreme, it then returns to zero. This return occurs as two input pulse

of the same type occur without an intervening pulse of the other type. However, as long as the

frequency error has the same sign, the locus will continue to traverse the same half of the output

characteristic. This is of presence of a frequency error has the correct polarity to bring the circuit

into lock.[4,11]

57

Figure 5.3 output characteristic of charge –pump phase detector

5.2 Charge Pump Phase Frequency Detector It have been already described the action of the charge pump as a linear PD. Now consider its

acquisition features. The PD has three possible output states, shown in Figure. 5.4.The name of

each state indicates the output that occurs in that state. At the occurrence of each reference pulse,

the existing state is in the direction indicated by the arrow marked R and at each divider output

pulse, the existing state is exited along a path marked D. It is evident that, if the divider output

frequency exceeds the reference frequency, the state must eventually alternate between zero and

“-“(unless the reference disappears, in which case the occupied state will be steadily

“-“).Conversely, a low divider output frequency results in the “+” state and zero state only(“+”

only, if the divider stops).

Figure 5.4 State transition diagram for phase frequency detector.

58

Figure 5.5 shows typical outputs for these two cases, and Figure.5.2 illustrates, in another manner,

the characteristic that is traced out if the reference and divider output frequencies differ only

slightly.

Consideration of Figure 5.4 leads to the conclusion that, when the VCO is free running, this type of

circuit will produce an average voltage of at least 50% of the maximum, that is, the equivalent of ±

π rad. If the final phase is within this range, the frequency must be swept through its final value

when the loop is out of lock and acquisition seems to be assured. When zero frequency error is

reached, the phase will be between -π and +π rad.

(a)

(b)

Figure 5.5 Output sequences for phase frequency detector with frequency errors: (a) f ref> f s and (b)

f s> f ref

59

If the steady state phase is zero (type-2 system the frequency will overshoot to bring the phase to its

final value.

x = F s/ Fref

Fig. 5.6 Average output of the charge pump phase frequency detector versus ratio of input frequencies. This assumes equiprobable phase difference between the inputs

If the two input frequencies are nearly identical, the output will have an average duty factor of 50%, producing 50% of maximum average output .If either input should disappear, the output becomes continuous (100% duty factor).Between these extremes, the change from 50% to 100% of maximum is linear with respect to the ratio of the low frequency to the high frequency. This is shown in Fig.5.5.

60

x = F ref /FS

1 cycle

-1 cycle

0

u1/k p

Chapter 6Analysis and Simulation Results

In Thesis work it have been analyzing the PLL frequency synthesis by using MATLAB. The

MATLAB simulation test is based on synthesis charge pump which are already described in the

previous chapter. Charge Pump is a kind of DC to DC converter that means capacitors as energy

storage elements to elements to create either a higher or lower voltage power source. By using

MATLAB software the optimizing value of the PLL have been analysis. By changing the parameters value it have been see the effect of phase noise, frequency output and Phase error.

6.1 The Simulation Block DiagramFor MATLAB simulation test it need a block diagram on charge pump phase frequency

detector. This can help us to understand the behaviors of PLL. In Figure 6.1 shown the

block diagram of synthesizer charge pump.

In this block diagram there are using some term which is

61

Figure 6.1 Block diagram for Charge Pump Synthesizer

PD: Phase detector Phe: Normalized Phase detector output Pha: Determined of the negative edge of the Phe Kp: Phase detector Gain KLF: filter DC Gain Kv: VCO Gain

Charge pump Synthesizerblock diagram gives us only four possible output results.

Phase Noise

Frequency Output

Phase error

PD output

By changing the parameters values in MATLAB code it analysis the frequency output result. Also

find the phase noise effect in the PLL. If the PLL design is not good then output frequency will

never locked because of phase error or phase noise.[15]

6.2 Math Lab Simulation Results

6.2.1 Optimizing Parameters The MATLAB simulation have been done by using the Block diagram of Charge pump

Synthesizer.The MATLAB script charge pump Synthesizer simulates a synthesizer using the

charge pump phase frequency detector (PFD).Output are shown in the Figure.

Loop with Charge-Pump Phase-Frequency Detector

Kp = 2; KLF = 100000; Kv = 1e+006;

Fp1 = 0.001 Hz; Fz = 100 Hz; Fp2 = 1000 Hz;

Fref = 10000 Hz; N goes from 800 to 1000;

Frequency from 8e+006 Hz to 1e+007 Hz;

Phase from -0.00102 cycle to -0.001 cycle;

Simulated Time 0.0098 seconds

62

(a) Output frequency

(b) PD output

63

(c) Phase error

(d) Frequency vs. Phase error

Figure 6.2 Kp = 2 (a)frequency output (b)PD output (c)Phase error (d) frequency vs. phase

In Figure 6.2 shows simulated acquisitions for a third order loop using a charge pump PD. These

were produced by MATLAB using the script charge pump Synthesizer.(a) shows the frequency

which is locked at 0.006 seconds. The effect of the wider output pulses can be seen as a saw tooth 64

appearance during the transient. The corresponding phase is shown at (c) and the phase detector

output is at (b).A change in phase polarity can be seen at 7 ms, but the phase error is too small to be

seen in (c).here the phase reverse direction when the frequency error changes sign. then the phase

reverse again at frequency 10MHz.

6.2.2 Changing the Value of K P

Some particular implementations of this circuit have been observed to perform anomalously. In one

case, when the input frequency difference became small, the output changed state when the

ineffective edges (positive transitions where negative transitions are the normal input triggers) of

the input waveforms passed. The problem was ultimately solved only by changing the IC type.

With another type, narrow pulses of the wrong polarity were observed during cycle skipping when

the input transitions were nearly coincident. This limited the maximum usable frequency because,

at high frequencies, the average pulse width during the beat note became equal to that of the

anomalous pulse. Figure 6.2 represents a switching transient where the PD remains in its linear

range. By increasing or decreasing the value of parameters of charge pump Synthesizer here can

easily see the effect of the PLL system. In script of charge pump Synthesizer change the value of

Kp. Here decreasing the value of Kp (gain of PD) but all the others parameters are remain same.

K P=1.5

In figure 6.3 (a) shows the frequency which is locked at 0.008 seconds. But in figure (b) which is

PD output. here the PD output is negative edge, because the divider output frequency is greater than

the reference frequency. Also in figure (c) shows the phase error after a certain time which is 0.007

the cycle curve goes to negative edges and cannot reaches the level 0.In frequency vs. phase curve

figure (d) shows that the frequency is reach the value of 10MHz

65

Figure 6.3 (a) frequency Output

Figure 6.3(b) PD output

66

Figure 6.3 (c) Phase error

Figure 6.3 (d) Frequency vs. phase

Figure 6.3 K p =1.5 (a)frequency output (b)PD output (c)Phase error (d) frequency vs. phase

67

K P= 10

In Figure 6.4(a) shows the frequency output .In this analysis the gain of PD has changing .If taking

the value of Kp is 10 and remain other parameters value are constant then the simulation result is

this situation which is shown in the Figure 6.4. In Figure (a) the frequency is locked time is 0.006

seconds. Phase error also reaches the 0.But the PD output it can see that the negative edges starting

at the time 0.008seconds.

(a)

68

(b)

(c)

(d)Figure 6.4 Kp=10 (a) Output frequency (b) PD output(c) Phase error (d) Frequency vs. Phase error

69

K P=60

In this section analysis the parameters behavior by increasing or decreasing the value. If increasing

the value of Kp=60 then our output sequences are different in the previous output sequences. Here

in Figure 6.5 (a) shown that at first the frequency is starting 0.8×107 to 1.5×107 and after certain

time locked at 10MHz in 0.005 seconds.

(a)

70

(b)

(c)

71

(d)Figure 6.5 Kp=60 (a) Output frequency (b) PD output(c) Phase error (d) Frequency vs. Phase error

By this analysisis the more optimizing Simulation Results when K p =2 and other all values are

remain same.

6.2.3 Changing the Value of F ref∧N0

In our MATLAB script charge pump Synthesizer, if changing the ratio of F ref

N 0 then some effect

of the PLL system have been seen.

F ref= 11250 and N 0= 900 In Figure 6.6 (a) see that the frequency is not locked in time & (c) can not reach the expected value.

Loop with Charge-Pump Phase-Frequency Detector

Kp = 2; KLF = 100000; Kv = 1e+006;

Fp1 = 0.001 Hz; Fz = 100 Hz; Fp2 = 1000 Hz;

Fref = 11250 Hz; N goes from 900 to 1000;

Frequency from 1.0125e+007 Hz to 1.125e+007 Hz;

Phase from -0.00100563 cycle to -0.001 cycle;

Simulated Time 0.0098 seconds

72

(a) (b)

(c) (d)Figure 6.6 F ref= 11250 and N0= 900 (a) Output frequency (b) PD output

(c) Phase error (d) Frequency vs. Phase error

F ref=8750∧N 0=700

If taking the ratio in this type then frequency is locked at 0.006 seconds. phase error also zero at

0.006seconds.

73

(a) (b)

(c) (d)Figure 6.7 F ref=8750∧N 0=700 (a) Output frequency (b) PD output(c) Phase error

(d) Frequency vs. Phase error

So this is the more optimizing curves when F ref=10000 and No=800 and other values are

remain same.

6.2.4 Changing the Pole LocationFP1=0 .01 Hz∧FP2=1000 Hz

Here taking the Filter first pole Fp1=0.01 in Hz and Filter second pole Fp2 = 1000 in Hz. The

frequency is overshoot sometimes and after sometimes its totally locked at 0.006 seconds. In PD

output positive edge side is at 0.007seconds then negative edge. Also in Phase error Figure shown

that the response of the phase error signal overshoot at 0 to 0.002 seconds but in at 0.007 its phase

error signal becomes 0.74

(a) (b)

(c) (d)Figure 6.8 Changing the pole location FP 1=0 . 01 Hz∧FP2=1000 Hz (a) Output frequency

(b) PD output(c) Phase error (d) Frequency vs. Phase error

FP 1=0.001 Hz∧F P2=100000 Hz

If changing the pole location which means changing the script charge pump Synthesizer in first

pole and second pole. In Figure 6.9 (a) shown that the frequency is not locked properly. The

transient response of phase error Figure(d) is 0 in 0.006seconds.In frequency vs. phase Figure(c)

shown that the frequency starts in 8MHz ,its reaches the 12MHz but in after certain time its finally

reaches 10MHz.PD output Figure(b) is also shows positive and negative edge curve.

75

(a) (b)

(c) (d)Figure 6.9 Changing the pole location FP 1=0 .001 Hz∧FP2=100000 Hz (a) Output frequency (b)

PD output(c) Phase error (d) Frequency vs. Phase error

6.2.5 Changing the Filter Zero

Fz = 50; Filter zero in HzIf changing the filter zero which means changing the script charge pump Synthesizer.In Figure

6.10(a) shows the frequency that does not locked in time,(b)PD output is only positive edges. In

Figure (c) shows the frequency starts in 8 MHz but doesn’t reach 10 MHz properly, (d) phase error

is not zero.

76

(a) (b)

(c) (d)Figure 6.10 Changing the filter zero Fz = 50 (a) Output frequency (b) PD output(c) Phase error

(d) Frequency vs. Phase error

So this is the more optimizing curves when F p1 =0.001 and F p2 =1000 and other values are

remain same.

6.2.6 Loop Filter CharacteristicsIn PLL block diagram, loop filters one of the elements. In this section shows the loop filter

magnitude and phase curve (Low pass filter).

If changing the pole location which means change the value of first pole and second pole.

77

Fp1=0.001Hz and Fp2=1000Hz

This is more optimizing low pass filter.

Figure 6.11 loop filter characteristics - Fp1=0.001Hz and Fp2=1000Hz magnitude and phase curve

Set first pole Fp1=0.01Hz

Figure 6.12 (a) low pass filter in set of first pole 0.01Hz

78

Set first pole Fp1=5Hz

Figure 6.12 (b) low pass filter in set of first pole 5 Hz

Second PoleFp2=800

Figure 6.13(a) low pass filter in set of second pole 800.

79

Second PoleFp2=1000

Figure 6.13 (b) low pass filter in set of second pole 1000.

So the more optimizing curves when Fp1 = 0.001, Filter first pole in Hz And Fz = 100,

Filter zero in Hz Fp2 = 1000, Filter second pole in Hz Fz = 100 and other values are remain

same

Chapter 7Conclusion

In this thesis paper actually discussing about the basic concepts of PLL frequency

synthesizer, basic equation of PLL Also doing a MATLAB simulation test, here discussing

the effect of phase noise, frequency output, PD output; also see the changing parameters

how they effect in the PLL system. Here not doing any practical design or hardware of PLL

frequency Synthesizer but in our simulation part analyzing the PLL system in many ways,

also showing their characteristics.

In this Thesis paper using a MATLAB PLL model.

Here trying to optimize the performance of the PLL by changing parameter values.

80

By using K p=2 ,F ref=10000, No=800 and F z=100, Fp1=0.001, Fp2=1000 values get

the more optimizing locking time will be 0.006ms which is the desired locking time.

In this Thesis analysis the effects shown phase noise, frequency output, phase error and

phase detector parameters in the performance.

The Goal is to minimize phase noise and lock time, and stabilize the phase error

performance for the PLL model.

Also analyzed the behavior of each sub blocks such as VCO, Phase detector, loop filter

etc.

Hopefully this paper helps the student’s lots to understand the PLL frequency synthesizer .

References

1. M. Gardner, Phase-Lock Techniques. New York: Wiley, 1966, 1979.

2. W.F. Egan, Frequency Synthesis by Phase Lock. 1981, New York: John Wiley, 2000.

3. W.C. Lindsey and C.M. Chie, eds Phase-Locked Loops. New York: IEEE Press, 1985.

4. V. Manassewtsch, Frequency Synthesizers: Theory and Design. 1st ed. New York: John

Wiley & Sons, 1975, last ed. 1990.

5. W.F. Egan, Phase-Lock Basics. John Wiley & Sons, 1999.

81

6. R. Best, Phase-Locked Loops: Design, Simulation, and Applications. New York: McGraw-

Hill, 1999.

7. C.J. Savant Jr., Basic Feedback Control System Design. New York, Toronto, London:

McGraw-Hill, 1958.

8. “Fractional-N Synthesizers,” (Design Feature), Microwaves and RF, August 1999.

9. Microwave and RF Wireless Systems, by David M. Pozar.Wiley (2000).

10. “Phase locked loops for high frequency receivers and transmitters,” by Mike Curtin and

Paul O’Brien. Analog Dialogue Volume 33, 1999.

11. Phase-locked Loops, by Roland E. Best. McGraw-Hill (1993).

12. “Phase Noise Reference” (Application Note), Applied Radio Labs.

13. H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E. Liu, E. Malavasi,

A.Sangiovanni-Vincentelli, and I. Vassiliou. A Top-Down Constraint-Driven Methodology

for Analog Integrated Circuits. Kluwer Academic Publishers, 1997.

14. http://en.wikipedia.org/wiki/PLL

15. http://www.radio-electronics.com › PLL

Appendex MATLAB Simulation Code%TIME RESPONSE & PHASE PLANE PLOT

%CHARGE-PUMP PHASE-FREQUENCY DETECTOR

clear;

% MODIFIES PARAMETERS BELOW & GO

%*****************************

clear

Fref = 10000; % Reference frequency in Hz

N1 = 1000; % divide number during simulation

N0 = 800; % initial divide number

PNL = -.001; % radian final phase, Pha

82

Kp = 2; % PD gain, U/Cycle (U = v, a, etc.)

KLF = 1e5; % Filter DC gain

Fp1 = .001; % Filter first pole in Hz

Fz = 100; % Filter zero in Hz

Fp2 = 1000; % Filter second pole in Hz

Kv = 1e6; % VCO gain, Hz/U

Tend = .0098; % Length of simulation. Student Matlab Fref*Tend ² 1k (v3.5) or 8k (v4) or 16k

(v5)

Expand = 1; % 1: allow, 0: disallow expansion of graphs (no questions to user if 0)

truncatePh = 1; % % Pha displays: 0 = multicycle 1 = mod 1 cycle

Punits = 1; % Plot Phase Units: 0 = radians 1 = cycles 2 = degrees

Funits = 1; % Plot Frequency Units: 0 = radians/sec 1 = Hz

% Available Outputs

% op=1: Phase Plane = Freq. vs. Pha

% op=2: Phase Plane + Phase Error vs. Time

% op=3: Frequency + PD Output vs. Time

% op=4: All of above = 4 plots

op = 4; % Choose Output

ACC = 1e-8; % allowed error in phase change of each divider cycle

reports = 8; % number of time reports during simulation

show = 0; % 1 = TRUE, 0 = FALSE monitor information

%******************************

FNL = N1*Fref; % finalfrequency

F0 = N0*Fref; % initial frequency

K = Kp*KLF*Kv;

Pha0 = PNL+(F0 - FNL)/K; % initial phase

Tref = 1/Fref;

fprintf('\nLoop with Charge-Pump Phase-Frequency Detector');

fprintf('\nKp = %g; KLF = %g; Kv = %g;',Kp,KLF,Kv);

fprintf('\nFp1 = %g Hz; Fz = %g Hz; Fp2 = %g Hz;',Fp1,Fz,Fp2);

fprintf('\nFref = %g Hz; N goes from %g to %g; ',Fref, N0, N1);

fprintf('\nFrequency from %g Hz to %g Hz;', F0,FNL);

fprintf('\nPhase from %g cycle to %g cycle;', Pha0,PNL);

fprintf('\nSimulated Time %g seconds\n',Tend);

83

twopi = 2*pi;

wp1 = twopi * Fp1;

wp2 = twopi * Fp2; % add additional poles below this line & add names to p below

wz = twopi * Fz;

p = [-wp1,-wp2]; % form a vector of open-loop poles

z = [-wz]; % form a vector of open-loop zeros

Kx = wp1*wp2*K/wz;

if reports

Treport = Tend/reports;

else

Treport = 2*Tend;

end

%Polynominals for open loop gain:

[N,Df] = zp2tf(z,p,Kx); % convert zeros, poles, and gain factor to open-loop numerator and

denominator.

sd = size(Df); % array size; sd(2) = number of columns = number of poles

D = Df; D(sd(2)+1) = 0; % multiply denominator by s by shifiting left (adding 0 to right)

[a,b,c,d] = tf2ss(N,D); % elements of dynamic matrix equation

[af,bf,cf,df] = tf2ss(N,Df);

clf; % clear previous graphs; for v.3.5, clg #########

% Initial Conditions

x0 = zeros(size(Df)); % zero initial conditions for phase and derivatives

xf0 = x0(1:length(x0) - 1); % zero initial conditions for frequency and derivative

yywas = 0; % prior divider phase (cycles), initally zero

ygoal = 1; % divider phase target during iterations, usually 1

TT(1) = 0; % time at PD transition

TP(1) = 0; % time when phase is determined (not reference time)

Pha(1) = Pha0; % start at initial phase

if Pha0>0, % compute state at end of Late pulse

u1 = [1 1]; % Phe is 1 during pulse

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Tinit = Pha0*Tref/2; % start at mid pulse, approximately average phase

[Phi, Gamma] = C2D(a,b,Tinit); % compute change from mid pulse

x = ltitr(Phi,Gamma,u1'); % phase state at mid pulse and end

x0 = x(2,:)'; % initial state for next phase computation

[Phif, Gammaf] = C2D(af,bf,Tinit);

xf = ltitr(Phif,Gammaf,u1'); % initial freqeuncy state

Phe(1) = 0; % after pulse

Tpartial = 0; % partial time for divider period (when computed in 2 segments)

TTr = (1-Pha0)*Tref; % time of next reference

T = Tref; % start next iteration with T estimated as divider period

else, % set variables for computation of state at end of early pulse

Phe(1) = -1; % during Early pulse

TTr = -Pha0*Tref; % next reference

end % if Pha0

FF(1) = F0; % FF(j) & PHE(j) occur with TT(j)

F1(1) = F0; % F1(i) & PHA(i) occur with TP(i)

i = 1; % reference period index

j = 1; % divider period index

skipT = -1; %ineffective divider outputs (-1 needed in Pha formula)

RepInt = Treport;

% BEGIN SIMULATION

while TT(j)<Tend, % while time is less than simulation time

if Phe(j) > -1, % not in Early pulse

%%%%%%%%%%%%%% Monitor Information

if show,

where = 1;

fprintf('\nwhere=1 i=%g j=%g Phe=%g TT=%g',i,j,Phe(j),TT(j));

fprintf(' yywas=%g',yywas);

end;

%%%%%%%%%%%%%%

u1(1) = Phe(j) - Pha0; % input to sampler at start of period = held value

u1(2) = u1(1); % constant Hold output -> same at beginning and end of period

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T = Tref - Tpartial; % start at steady-state period less what has already been

computed

y = 0; % just to make loop start

while abs(y-ygoal)>ACC, % ONLY ITERATIVE COMPUTATION OF

STATE

[Phi, Gamma] = C2D(a,b,T); % Matrics for use in solution

x = ltitr(Phi,Gamma,u1',x0); % state variable solution (for phase) at

each value of t

yy = c*x'; % corresponding outputs (d is null for polynominals above)

y = (yy(2) - yywas + (T+Tpartial)*F0)/N1 + ygoal -1;

% yy(2)-yywas is added to T*F0 to give phase change at divider input.

% 1-ygoal has already occurred and must be subtracted to give new

change.

T = T*ygoal/y; % adjust T until yÅygoal

end; % iteration;

TT(j+1) = T + TT(j); % Time of transition

end % if Phe(j)>-1

if Phe(j) == 1, % END OF LATE PULSE HAS BEEN COMPUTED @ TT(j+1)

%%%%%%%%%%%%%%

if show,

where = 2;

fprintf('\nwhere=2 i=%g j=%g Phe=%g TT=%g',i,j,Phe(j),TT(j));

fprintf(' yywas=%g',yywas);

end;

%%%%%%%%%%%%%%

i = i+1; % increment reference cycle

j = j+1; % increment transition number

TP(i) = TT(j); % phase determined at end of late pulse

yywas = yy(2); % divider phase at start of next divider cycle

TTr = TTr + Tref*(1+floor((TT(j)-TTr)*Fref)); % Next reference time

[Phif, Gammaf] = C2D(af,bf,T); % for use in frequency solution

xf = ltitr(Phif,Gammaf,u1',xf0); % for use in frequency solution

x0 = x(2,:)'; % set initial x for next computation

xf0 = xf(2,:)'; % set initial xf for next computation

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yyf = cf*xf'; % frequency less offset

Pha(i) = Pha0 + TP(i)*Fref - i - skipT; % change = (ref - divider) periods

if truncatePh,

Pha(i) = Pha(i) - floor(Pha(i));

end % if truncatePh

F1(i) = yyf(2) + F0; % frequency out

Phe(j) = 0; % at end of late pulse

Tpartial = 0; % starting new divider cycle

ygoal = 1; % whole divider cycle time yet to be found

else, % was not in Late pulse

if Phe(j) == 0, % AFTER PULSE, COMPUTE START OF NEXT PULSE

%%%%%%%%%%%%%%

if show,

where = 3;

fprintf('\nwhere=3 i=%g j=%g Phe=%g TT=%g',i,j,Phe(j),TT(j));

fprintf(' yywas=%g y-1=%g TTj+1=%g',yywas,y-1,TT(j+1));

end;

%%%%%%%%%%%%%%

j = j+1; % for next pulse transition

if TT(j) < TTr, % EARLY PULSE STARTED AT TT(j)

%%%%%%%%%%%%%%

if show,

where = 4;

fprintf('\nwhere=4 i=%g j-1=%g Phe=%g TT=%g',i,j-1,Phe(j-1),TT(j-1));

fprintf(' yywas=%g',yywas);

end;

%%%%%%%%%%%%%%

i = i+1;

TP(i) = TT(j);

Pha(i) = Pha0 + TP(i)*Fref - i - skipT; % change = (ref -

divider) periods

if truncatePh,

Pha(i) = Pha(i) - floor(Pha(i)) - 1;

87

end % if truncatePh

yywas = yy(2); % for use in computing next point

% Compute frequency at start of Early Pulse

[Phif, Gammaf] = C2D(af,bf,T); % for use in

frequency solution

xf = ltitr(Phif,Gammaf,u1',xf0); % for use in

frequency solution

yyf = cf*xf'; % frequency less offset

FF(j) = yyf(2) + F0; % frequency out

F1(i) = FF(j);

x0 = x(2,:)'; % set initial x for next computation

xf0 = xf(2,:)'; % set initial xf for next computation

Phe(j) = -1; % during Early pulse

Tpartial = 0; % starting new divider cycle

ygoal = 1;

else, % if TT(j) ³ TTr % IN LATE PULSE; DEFINED ITS START

%%%%%%%%%%%%%%

if show,

where = 5;

fprintf('\nwhere=5 i=%g j-1=%g Phe=%g TT=%g',i,j-1,Phe(j-1),TT(j-1));

fprintf(' yywas=%g',yywas);

end;

%%%%%%%%%%%%%%

TT(j) = TTr; % pulse starts at reference time

T = TTr-TT(j-1); % divider count time from last transition

[Phi, Gamma] = C2D(a,b,T); % solution matrix at T

x = ltitr(Phi,Gamma,u1',x0); % at TTr, existing input and

initial state

yy = c*x'; % to use in getting ygoal below

[Phif, Gammaf] = C2D(af,bf,T); % for later frequency

computation

xf = ltitr(Phif,Gammaf,u1',xf0); % at TTr

x0 = x(2,:)'; % set initial x for next computation

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xf0 = xf(2,:)'; % set initial xf for next computation

Phe(j) = 1; % during Late Pulse

Tpartial = Tpartial + T; % divider cycle has gone on for this

time

ygoal = 1 - (yy(2) - yywas + Tpartial*F0)/N1; % phase

change for rest of Ö cycle

end % if TT(j)<TTr

end % if Phe == 0

if Phe(j) == -1, % within Early pulse; compute state at its end

%%%%%%%%%%%%%%

if show,

where = 6;

fprintf('\nwhere=6 i=%g j=%g Phe=%g TT=%g',i,j,Phe(j),TT(j));

fprintf(' yywas=%g',yywas);

end;

%%%%%%%%%%%%%%

T = TTr - TT(j); % Early pulse from prior transition to reference time

Tpartial = T; % this much time has gone by in the count

if j==1, % compute change from midpulse initially

T = T/2;

end;

j = j+1;

TT(j) = TTr; % transion at reference time

[Phi, Gamma] = C2D(a,b,T); % values for use in solution eqution [see

manual]

u1(1) = -1 - Pha0; % initial input to sampler

u1(2) = u1(1); % same at end; constant Hold output

x = ltitr(Phi,Gamma,u1',x0); % solutions at period start and end

yy = c*x'; % corresponding outputs (d is null for polynomials above)

% If more than a partial divider cycle occurs before TTr, remove any

whole

% cycles so next computed time will be after TTr (after Early pulse)

y = (yy(2)-yywas + T*F0)/N1;

if j==2, % T was set to T/2 above

89

y = 2*y; % 2 times computed y during whole early

pulse

end;

yywas = yywas + N1*floor(y);

[Phif, Gammaf] = C2D(af,bf,T); % for use in frequency solution

xf = ltitr(Phif,Gammaf,u1',xf0); % for use in frequency solution

x0 = x(2,:)'; % set initial x for next iteration as current x

xf0 = xf(2,:)'; % set initial x for next iteration as current x

Phe(j) = 0; % at pulse end

skipT = skipT + floor(y); % change number of ineffective divider

outputs

ygoal = 1 - y + floor(y); % phase change still to be found

end ; % if Phe == -1

TTr = TTr + Tref; % next reference time

end % if Phe == 1

% Now compute frequency corresponding to time of pulse transition

yyf = cf*xf'; % frequency less offset

FF(j) = yyf(2) + F0; % frequency out

%%%%%%%%%%%%%%

if show,

where = 7;

fprintf('\nwhere=7 i=%g j=%g Phe=%g TT=%g',i,j,Phe(j),TT(j));

fprintf(' yywas=%g i=%g\n',yywas,i);

end;

%%%%%%%%%%%%%%

if TT(j)>Treport

fprintf('%g seconds\n',TT(j));

Treport = Treport + RepInt;

end % if report

end % while TT(j) < Tend

% END SIMULATION. The rest is plotting.

if Punits == 1,

Pscale = 1;

90

elseif Punits == 2,

Pscale = 360;

else,

Pscale = 2*pi;

end % if Punits

if Funits == 1,

Fscale = 1;

else

Fscale = 2*pi;

end % if Funits

imin = 1; jmin = 1; imax = i; jmax = j; % initial indeces for plots

while (imin>0) & (imax>0) % plot; then allow expansion by user

Tmax = -9; Fmax = -9; Pmax = -9; % code that axes ranges are not yet set

if (op == 2)|(op == 4), % selecting phase error vs. time

if op == 2,

subplot (212),

else,

subplot (223),

end % if op==2 (where to put plot)

plot(TP(imin:imax),Pscale*Pha(imin:imax),'g')

title('Pha, Phase Error')

grid

xlabel('seconds')

if Punits == 1, % Set display of phase units

ylabel('cycles');

elseif Punits == 2,

ylabel('degrees');

else,

ylabel('radians');

end % if Punits

v = axis; Tmin = v(1); Tmax = v(2); Pmin = v(3); Pmax = v(4); % to be used

below for common limits

axis([Tmin Tmax Pmin Pmax]) % set axes limits

end % if (2)|(4)

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if (op == 3)|(op == 4),

if op == 3, % selecting frequency vs. time

subplot(211);

else,

subplot(222);

end % if op==3 (where to put plot)

plot(TT(jmin:jmax),Fscale*FF(jmin:jmax),'b')

title('Frequency Out')

grid

xlabel('seconds');

if Funits == 1, % Set display of frequency units

ylabel('Hz');

else,

ylabel('radians / second');

end % if Funits

v = axis; % get axes limits

Fmin = v(3); Fmax = v(4); % set frequency axis limits

if Tmax == -9, % if time axis limits not yet set

Tmin = v(1); Tmax = v(2); % set time axis limits

end

axis([Tmin Tmax Fmin Fmax]) % set axes limits

if op == 3, % selecting PD output vs. time

subplot(212);

else,

subplot(224);

end % if op==3

mx = length(Phe);

for ii = 1:mx-1 % create new data points to make display stepped

T(2*ii-1) = TT(ii);

T(2*ii) = TT(ii+1);

Ph(2*ii-1) = Phe(ii);

Ph(2*ii) = Phe(ii);

end; %ii

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plot(T(2*jmin-1:2*jmax-2),Ph(2*jmin-1:2*jmax-2));

title('Phe, PD Output/(Kp cycle)')

grid

xlabel('seconds')

if Tmax ~= -9, % if time axis limits have been set

axis([Tmin Tmax -1.1 1.1]) % set time and Phe axes limits

else

axis([-inf inf -1.1 1.1]) % set Phe limits only

end

end % if (3)|(4)

if op ~= 3, % selecting phase-plane plot

if op==1,

subplot(111),

elseif op==2,

subplot(211),

elseif op==4,

subplot(221),

end % if op==1 (where to put plot)

plot(Pscale*Pha(imin:imax),Fscale*F1(imin:imax),'r')

title('Phase Plane, Freq. vs. Pha')

grid

if Punits == 1, % Set display of phase units

xlabel('phase error (cycles)');

elseif Punits == 2,

xlabel('phase error (degrees)');

else,

xlabel('phase error (radians)');

end % if Punits

if Funits == 1, % Set display of frequency units

ylabel('freq (Hz)');

else,

ylabel('freq (rad/sec)');

end % if Funits

93

v = axis; % vector of axes limits

if Pmax == -9, % if phase axis limits not yet set

Pmin = v(1); Pmax = v(2); % set phase axis limits

end

if Fmax == -9, % if freq axis limits not yet set

Fmin = v(3);Fmax = v(4); % set phase axis limits

end

axis([Pmin Pmax Fmin Fmax]) % set axes limits

end % if op~=3

pmax = 100; pmin = 0; doAgain = Expand;

fprintf('\n');

% allow user to expand graphs by limiting range of plotted data

while doAgain % set start values

pmin0 = input('To expand, enter start time as % (<100) of maximum (return =

no change; <0 to quit) ');

if ~isempty(pmin0) % to retain value if user hits return

pmin = pmin0;

imin = floor(pmin*i/100)+1; jmin = floor(pmin*j/100)+1;

end

if imin<i % if imin is too high, repeat input

doAgain = 0;

end

end % doAgain for min

doAgain = Expand;

while doAgain, % set end values

pmax0 = input('To expand enter stop time as % (<100) of maximum (return = no

change; <0 to quit) ');

if ~isempty(pmax0) % to retain value if user hits return

pmax = pmax0;

imax = floor(pmax*i/100); jmax = floor(pmax*j/100);

end

if (imin >= imax) & (imax > 0),

disp(' Maximum must be greater than minimum and

94

less than 100 (%)')

end

if ((imin < imax) & (imax <= i)) | imax < 0 % if max not in range, repeat input

doAgain = 0;

end

end % doAgain for max

imin = imin * Expand; % end display loop if Expand == 0

end % imax, imin > 0 (display loop)

95

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