Design ofNUMERICALLY CONTROLLED

OSCILLATORusing VHDL

A project report

Submitted in partial fulfillment of the requirement for the award ofPost Graduate Diploma in Embedded System & VLSI Design

(PGDEVD) of theCentre for Development of Advanced Computing (CDAC)(Dept. of IT, Ministry of Communication & Information Technology)

Govt. of India

PGDEVD(Batch XVII)

(Aug 09 – Jan 10)

By:Arvind Kumar Pandey

Vaibhav AggarwalVijay Kumar

Centre for Development of Advanced Computing (CDAC)B-30 & C-56, Sector 62, Noida - 201307

ISO 9001:2008

(2009-2010)

Centre for Development of Advanced Computing (CDAC)Dept. of IT, Ministry of Communication

&Information Technology

Govt. of India

CERTIFICATE

This is to certify that the project work entitled “DESIGN OF

NUMERICALLY CONTROLLED OSCILLATOR USING VHDL”

submitted by ARVIND KUMAR PANDEY, VAIBHAV AGGARWAL AND

VIJAY KUMAR is an authentic work carried out by them. Their work has

been found satisfactory for the partial fulfillment of the PGDEVD.

(Project guide)

______________

(MR. VINOD SHARMA)

ACKNOWLEDGEMENT

It is my duty to record my sincere thanks

and deep sense of gratitude to my respected teacher

and Project Co-ordinator

MR. VINOD SHARMA

for his valuable guidance, interest

and constant encouragement for the

fulfillment of the project.

I am immensely thankful to Mr. Ravi Payal & Mr. Sanjeev Shah for his help and kind cooperation time to time at his busiest.

I am deeply indebted to all faculty members, of PGDEVD, for their kind cooperation & advices given to me time to time.

Post Graduate Diploma in Embedded System & VLSI DesignPGDEVDBatch – XVII (Aug 09 – Jan 10) Centre for Development of Advanced Computing (CDAC), NoidaMinistry of Communication & Information Technology, Govt. of India

DATE: 14-JAN-2010 Arvind Kumar Pandey

Vaibhav Aggarwal Vijay Kumar

ABSTRACT

Introduction to our project “Numerically Controlled Oscillator” would require the introduction of OSCILLATORS. Oscillators are used in radio circuits to produce radio and audio frequency energy, generally with a sine wave output, though the waveform can be many shapes such as a square wave or saw tooth. The sinusoidal waveform may be AC or DC. Oscillators used in radio frequency circuits are always very low power devices, in contrast to AC generators in a power station. Nevertheless, the AC power generator and the electronic oscillator are related, in that they both produce sinusoidal electrical energy. Unlike the AC generator though, the electronic oscillator can produce output on frequencies measured in tens of megahertz. Special oscillators can produce output at microwave frequencies A numerically controlled oscillator (NCO) is an electronic system for synthesizing a range of frequencies from a fixed time base. Unlike a phase-locked loop-based analog frequency synthesizer, it is capable of synthesizing a very wide range of precise frequency ratios. Numerically Controlled Oscillators (NCO), also called Direct Digital Synthesizers (DDS), is a powerful technique used in the generation of radio frequency signals for use in a variety of applications from radio receivers to signals generators and many more. A conventional numerically controlled oscillator (NCO) uses time domain amplitude samples to generate a sinusoidal waveform whose frequency is controlled by a digital control word in the period of a single clock cycle. An NCO's output frequency can change instantly without the acquisition and lock time delays associated with conventional phase-locked loop synthesizers. The NCO's output frequency is controlled by an input count/integer value. The architecture inside an NCO core basically contains a phase accumulator and a phase-to-amplitude converter (PAC). Most PACs use two or more lookup tables and some associated logic to provide the phase-to-amplitude conversion. For saw-tooth wave generation we uses the logic of a counter and for the generation of Sine / Cosine wave we use Rom (which stores the values of Sine and Cos). Depending on the input count that we send to this block, they will pick values from the ROM, which in turn is our Sine / Cosine wave. In our project we have done coding for the above mentioned logic to generate a saw tooth as well as a sine wave..

Contents

S.No.Chapter Page No.

1. INTRODUCTION………………………………………………………..….1

2. BLOCK DIAGRAM…...……...……..………………………………………4

3. WORKING OF BLOCK DIAGRAM…………………………………......22

4. VHDL CODE…..…………..………....…………………………………….25

5. SYNTHESIS REPORT……………………………………………...……..29

6. FUTURE SCOPE………………….…..…………………………………...42

7. CONCLUSION..…………………………………………………….….......45

8. BIBLIOGRAPHY...……...……………………………………………........46

9. LIST OF FIGURES………………………………………………………...47

Numerically Controlled Oscillator

3.1 Principle Of Operation:

As the name suggests this form of synthesis generates the waveform directly using numerical / digital techniques. This is different to the way in which the more familiar indirect synthesizers that use a phase locked loop as the basis of their operation.

A direct digital synthesizer operates by storing the points of a waveform in digital format, and then recalling them to generate the waveform. The rate at which the synthesizer completes one waveform then governs the frequency. The overall block diagram is shown below, but before looking at the details operation of the synthesizer it is necessary to look at the basic concept behind the system. The operation can be envisaged more easily by looking at the way that phase progresses over the course of one cycle of the waveform. This can be envisaged as the phase progressing around a circle. As the phase advances around the circle, this corresponds to advances in the waveform. The synthesizer operates by storing various points in the waveform in digital form and then recalling them to generate the waveform. Its operation can be explained in more detail by considering the phase advances around a circle as shown in Figure below.

Fig.- The Theory Of NCO

As the phase advances around the circle this corresponds to advances in the waveform, i.e. the greater the number corresponding to the phase, the greater

the point is along the waveform. By successively advancing the number corresponding to the phase it is possible to move further along the waveform cycle.

BLOCK DIAGRAM:

Fig.- The Block Diagram Of NCO

Fig.- The OUTPUT at Different stages Of NCO

A direct digital synthesizer can be implemented from a phase register, phase accumulator, sine look-up table (phase-to-amplitude converter) . A NCO can produce a required frequency sine wave predefine by the user. The frequency depends on three variables; the reference-clock frequency (f clk), the frequency control word, (M) into the phase register and an n-bit phase accumulator.

This section will discuss on the functionality and operation of each blocks.

1) Phase Accumulator

The digital implementation does have a repetitive angular phase range of 0 to 360 degrees is no difference from a continuous time sinusoidal signals. During the NCO implementation, the phase accumulator has a counter carry function that allows it to act as a phase wheel

Understanding the use of this basic function better, try to imagine the sine-wave oscillation as a vector rotating around a phase circle and phase wheel itself has many designated points. Each designated point corresponds to the equivalent point on a cycle of a sine wave. Visualize that as the vector rotates around the wheel, the Sine of the angle will generates a corresponding output sine wave. When rotating at a constant speed, one revolution of the vector around the phase wheel is equivalent to one complete cycle of the output sine wave. The contents of the phase accumulator correspond to the points on the cycle of the output sine wave. The phase accumulator provides the equally spaced angular values accompanying the vector’s linear rotation around the phase wheel.

The PA is a modulo-M counter, each times it receives a clock pulse it will stored its increment number. The magnitude of the increment is determined by the frequency tuning word and it effectively sets how many points to skip around the phase wheel and this word forms the phase step size between reference-clock updates. The larger the jump size, the faster the phase accumulator overflows and completes one full round of the phase wheel is equivalent to a sine-wave cycle. The resolution of the PA (n-bits) represented by the number of discrete phase points contained in the wheel whereby it determines the tuning resolution of the NCO. For example, for an n = 8-bit phase accumulator, M will have a value of 0000 0001, which would cause the phase accumulator to overflow after incrementing of 2^8 reference-clock cycles If the value of M is changed to 0111 1111 (2^7), phase accumulator will overflow after 2 reference-clock cycles (the minimum required by Nyquist). Therefore giving an example if n=32, and M=1. The phase accumulator steps through each and every of the 2^32 possible outputs before it overflows. The corresponding output sine-wave frequency is equal to the clock frequency divided by 2^32. If M=2, then the phase accumulator register "rolls over" twice as fast, and the output frequency is doubled .The tuning word in the phase register, M determines the speed of overflowing and the amount of phase accumulator is incremented each clock cycle. This relationship can be seen in the basic tuning equation for NCO architecture

Any change to the value of M results in immediate and phase-continuous changes in the output frequency. In a NCO, no loop settling time is incurred as in the case of a PLL. As the output frequency is increased, the number of samples per cycle decreases. Since, sampling theory, dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a NCO is however, Fclk/2 for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output. When generating a constant frequency, the output of the PA increases linearly, so the analog waveform, it generates is inherently a ramp.

2) Phase-to-Amplitude Converter (ROM/ LUT)

In this thesis, to make the output of the PA useful, the signal converts digital phase input from the accumulator to output amplitude. This output represents the phase of the wave as well as an address to a word, which is the corresponding amplitude of the phase in the LUT. The digital phase information is used to address the ROM and

eg if a 12 bit ROM is used, only 10 most significant accumulator bits are used. The remaining 2 bits provide added frequency resolution and minimize the effects of quantization of the phase to amplitude conversion.

A ROM pointer are implemented which points to the memory location in ROM that corresponds to the appropriate magnitude for its corresponding phase angle to meet the input requirements of the ROM block,. After each clock cycle, the appropriate magnitude of the ROM output is assigned to create a complete sine wave.

The output frequency of this NCO implementation is dependent on 1.) Frequency reference clock and 2.) Sinewave step size that is programmed into the ROM. Despite that DDS system lacks of tuning flexibility, the jitter, analog output fidelity, and AC performance of this architecture can consider good, The output frequency cannot be amend by changing the tuning word as it is a variable input, the only way to affect the output frequency is by changing the frequency of the reference clock, by reprogramming the ROM as shown in equation below

This equation is known as DDS "tuning equation." The frequency resolution of the system equals Fclk/2^n. A sine wave can be expressed generally as a(t) = sin(ùt) which not easy to generate and is non-linear in nature. But by rotating the phase angle through a fixed angle for each unit of time, the angular information can be made linear. The angular rate depends on ω = 2πf, the frequency of the signal, where ω is the angular frequency.

The phase of a sine wave is linear, and for that one period it depends on few parameters which are a reference clock period, phase rotation Δp clock and the frequency ƒclock. The formula can be determined by:

Where, Δp equals to the change in phase of sine wave, Δt is the small change in time and ω is the angular frequency of wave. To find ω in Equation 2, phase rotation Δp is divided by time Δt .

The overflowing phase accumulator clocked together with clock frequency ƒclock will generates the phase value sequence.

The Sine and Cosine block implements a sine and/or cosine wave in fixed point using a lookup table method that exploits quarter wave symmetry. The user defines the number of lookup table points in the Number of data points for lookup table parameter. The block implementation is most efficient when you specify the lookup table data points to be (2^n) +1, where n is an integer.

Phase accumulator result Theoretically the resolution frequency is output freq / n bits = 50 MHz / 256 = 195312.5 Hz, which means that each 110011 in binary is equivalent to 195312.5 Hz. And with tuning word of 51 meaning it skips the wheel of 51 at each clock pulse see Figure 4.4A. In this case the phase wheel will take 5 points to hit 255 for the PA to overflow which make up a sine wave. Figure 4.4B below show the random point which I self select to form a sine, it is not meant to be actual scaling. The PA therefore needed 51 accumulation steps. In turn of overflow, it will take 51 / 5 = approximately 11 times, actual overflowing is 10.2 times. The output frequency will be 195312.5 x 5 x 11 = approximately more than 10Mhz

Phase wheel

Phase accumulator overflow

But the thesis design in such a way that it adds 256 Hz at each clock pulse instead of adding the resolution frequency of 195312.5Hz as shown above. The tuning word here is also 51, in order to show the comparison and the design concept difference.

The system resolution frequency becomes 50 MHz / 195312.5 = 256Hz. You can see from the phase wheel that at each clock pulse, the PA will accumulate 110011 bit in which each 110011 bit represents only 256Hz. It will therefore need a total number of 195313 accumulation steps to make up output of 10MHZ.

LUT Result The output of the PA serves as the address of the LUT. Each time the PA overflows, the LUT outputs sampled values of the sine wave

LUT output amplitude form

FLOW CHART

OUTPUT (DIGITAL SINE WAVE)

VHDL CODE FOR GENERATION OF SAW TOOTH WAVEFORMlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity counter8 isport( clk,rst,en : in std_logic;

offset: in std_logic_vector(2 downto 0);

sum : out std_logic_vector(2 downto 0);co : out std_logic);

end counter8;architecture counter8_a of counter8 issignal count : std_logic_vector(2 downto 0);beginprocess( rst,clk)beginif rst = '1' thencount <= "000";elsif clk = '1' and clk'event thenif en = '1' thencount <= count+1;end if;end if;end process;sum <= count;co <= '1' when count =7 and en = '1' else '0';end counter8_a;

VHDL CODE FOR TEST BENCH

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter8_t2 isend counter8_t2;architecture counter8_t2_a of counter8_t2 issignal clk : std_logic:='1';signal rst : std_logic;signal en : std_logic;signal offset:std_logic_vector(2 downto 0):="000";signal sum : std_logic_vector(2 downto 0);signal co : std_logic;

component counter8port(clk,rst,en : in std_logic;

offset:in std_logic_vector(2 downto 0);sum : out std_logic_vector(2 downto 0); co : out std_logic);

end component;beginu1: counter8 port map(clk,rst,en,offset,sum,co);

clk <= not clk after 5 ns;processbeginrst <='1';en <='0';wait for 5 ns;rst<='0';en<='1';wait for 500 ns;end process;end counter8_t2_a;

SYNTHESIS USING XILINX

TECHNOLOGY SCHEMATIC

VHDL CODE FOR GENERATION OF SINE WAVE

library ieee;USE ieee.std_logic_1164.all;USE IEEE.numeric_std.ALL;use ieee.std_logic_unsigned.all;

entity nco3 IS-- Declarationsport ( clk : in std_logic;

reset : in std_logic;din : in signed(7 downto 0);dout : out signed(3 downto 0));

end nco3 ;

-- hds interface_endARCHITECTURE behavior OF nco3 IStype vectype is array (0 to 15) of signed(3 downto 0);-- ROM cosromconstant cosrom : vectype := (0 => "0000",1 => "0001",2 => "0010",3 => "0011",4 => "0100",5 => "0101",6 => "0110",7 => "0111",8 => "1000",9 => "1001",10 => "1010",

11 => "1011",12 => "1100",13 => "1101",14 => "1110",15 => "1111");

signal dtemp : unsigned(9 downto 0);signal din_buf : signed(9 downto 0);signal dtemp1 : integer;constant offset : unsigned(9 downto 0) := "0001000000";

begin

process(CLK, RESET)beginif (RESET='1') thendout <= (others => '0');din_buf <= (others => '0');dtemp <= (others => '0');dtemp1 <= 0;elsif rising_edge(CLK) thendin_buf <= din(7)&din(7)&din;dtemp <= dtemp + unsigned(din_buf) + offset;dtemp1 <= to_integer(dtemp(3 downto 0));if (dtemp1 >= 0) and (dtemp1 < 15) thendout <= cosrom(dtemp1);elsif (dtemp1 >= 257) and (dtemp1 < 513) thendout <= -cosrom(512-dtemp1);elsif (dtemp1 >= 513) and (dtemp1 < 769) thendout <= -cosrom(dtemp1-512);elsedout <= cosrom(1024-dtemp1);end if;end if;end process;END behavior;

VHDL CODE FOR TEST BENCH

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;USE IEEE.numeric_std.ALL;

entity nco3_tb isend nco3_tb;

architecture nco3_tb_a of nco3_tb issignal clk : std_logic:='1';signal reset : std_logic;signal din : signed(7 downto 0):="11110011";signal dout : signed(3 downto 0);

component nco3port ( clk : in std_logic;

reset : in std_logic;din : in signed(11 downto 0);dout : out signed(7 downto 0));

end component;beginu1: nco3port map(clk,reset,din,dout);clk <= not clk after 5 ns;processbeginreset <='1';wait for 5 ns;reset<='0';wait for 500 ns;end process;end nco3_tb_a;

SYNTHESIS USING XILINXRTL SCHEMATIC

TECHNOLOGY SCHEMATIC

SYNTHESIS REPORT

======================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : nco3.ngrTop Level Output File Name : nco3Output Format : NGCOptimization Goal : SpeedKeep Hierarchy : NO

Design Statistics# IOs : 14

Macro Statistics :# ROMs : 1# 16x4-bit ROM : 1# Registers : 4# 10-bit register : 2# 4-bit register : 2# Adders/Subtractors : 2# 10-bit adder : 2

Cell Usage :# BELS : 11# GND : 1# LUT2_L : 4# MUXCY : 3# XORCY : 3# FlipFlops/Latches : 16# FDC : 16# Clock Buffers : 1

# BUFGP : 1# IO Buffers : 9# IBUF : 5# OBUF : 4=========================================================================

Device utilization summary:---------------------------

Selected Device : 2s50etq144-7

Number of Slices: 9 out of 768 1% Number of Slice Flip Flops: 16 out of 1536 1% Number of 4 input LUTs: 4 out of 1536 0% Number of bonded IOBs: 14 out of 102 13% Number of GCLKs: 1 out of 4 25%

=========================================================================TIMING REPORT

Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 16 |-----------------------------------+------------------------+-------+

Timing Summary:---------------Speed Grade: -7

Minimum period: 4.131ns (Maximum Frequency: 242.072MHz) Minimum input arrival time before clock: 2.245ns Maximum output required time after clock: 6.140ns Maximum combinational path delay: No path found

Timing Detail:--------------All values displayed in nanoseconds (ns)

=========================================================================Timing constraint: Default period analysis for Clock 'clk' Clock period: 4.131ns (frequency: 242.072MHz) Total number of paths / destination ports: 34 / 12-------------------------------------------------------------------------

Delay: 4.131ns (Levels of Logic = 5) Source: dtemp_0 (FF) Destination: dtemp_3 (FF) Source Clock: clk rising Destination Clock: clk rising

Data Path: dtemp_0 to dtemp_3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:C->Q 2 0.886 1.035 dtemp_0 (dtemp_0) LUT2_L:I1->LO 2 0.418 0.000 nco3__n0010<0>lut (N4) MUXCY:S->O 1 0.461 0.000 nco3__n0010<0>cy (nco3__n0010<0>_cyo) MUXCY:CI->O 1 0.052 0.000 nco3__n0010<1>cy (nco3__n0010<1>_cyo) MUXCY:CI->O 0 0.052 0.000 nco3__n0010<2>cy (nco3__n0010<2>_cyo) XORCY:CI->O 1 0.579 0.000 nco3__n0010<3>_xor (_n0010<3>) FDC:D 0.648 dtemp_3 ---------------------------------------- Total 4.131ns (3.096ns logic, 1.035ns route) (74.9% logic, 25.1% route)

=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 4 / 4-------------------------------------------------------------------------Offset: 2.245ns (Levels of Logic = 1) Source: din<0> (PAD) Destination: din_buf_0 (FF) Destination Clock: clk rising

Data Path: din<0> to din_buf_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 0.769 0.828 din_0_IBUF (din_0_IBUF) FDC:D 0.648 din_buf_0 ---------------------------------------- Total 2.245ns (1.417ns logic, 0.828ns route) (63.1% logic, 36.9% route)

=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 4 / 4-------------------------------------------------------------------------Offset: 6.140ns (Levels of Logic = 1) Source: dout_3 (FF) Destination: dout<3> (PAD) Source Clock: clk rising

Data Path: dout_3 to dout<3> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:C->Q 1 0.886 0.828 dout_3 (dout_3) OBUF:I->O 4.426 dout_3_OBUF (dout<3>) ---------------------------------------- Total 6.140ns (5.312ns logic, 0.828ns route) (86.5% logic, 13.5% route)

=========================================================================CPU : 3.50 / 3.86 s | Elapsed : 3.00 / 4.00 s--> Total memory usage is 85156 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 10 ( 0 filtered)Number of infos : 0 ( 0 filtered)

APPLICATIONS

• Digital radios and modems

• Software-defined radios (SDR)

• Digital down/up converters for cellular and PCS base stations

• Waveform synthesis in digital phase locked loops

• Generating injection frequencies for analog mixers

ADVANTAGES

NCO architecture which has a digital control interface can facilitates an environment where systems can be optimized in turn of minutes and remotely controlled, under processor control.

NCO able to have complete digital control such as sub degree phase tuning capability and micro hertz tuning resolution of the output frequency.

NCO phase continuous frequency hops come with no analog-related loop settling time anomalies or over/undershoot NCO enable extremely fast “hopping speed” in tuning output frequency or phase

With NCO digital architecture, the need for manual system tuning, tweaking associated with component, aging and temperature drift in analog synthesizer solutions can be eliminated

FUTURE SCOPE

NCO based function generators are just beginning to appear in the market. These function generators offer substantial performance improvements, at reduced costs, over conventional analog function generators. As the cost of ASICs, RAMs and DACs decline, while their speed and resolution increase, expect to see NCO based function generators soon replace their analog counterparts.

CONCLUSSION

…….. likh le

BIBLIOGRAPHY

1. J. Bhasker, VHDL PRIMER, Third Edition, Prentice Hall of India, PHI LearningPrivate Limited, New Delhi.2. M. Morris Mano, Digital Design, Third Edition, Prentice Hallmof India.3. M. Morris Mano, Computer System Architecture, Third Edition, Prentice Hall of India

Private Limited.4. Charles H. Roth Jr., Digital System Design Using VHDL, PWS Publication Company5. Digital Circuits, Aanand Kumar, Prentice Hall of India.6. http://www.vhdl.org/vi/comp.lang.vhdl/ 7. http://www.asic-world.com/vhdl/tutorial.html 8. http://www.asic-world.com/digital/tutorial.html 9. http://en.wikipedia.org/wiki/Calculator

10. http://www.velocityreviews.com/forums/f18-vhdl.html 11. http://www.labbookpages.co.uk/fpgas/modules.html http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.htm