final presentation winter 2010 performed by: tomer michaeli 052792769 liav cohen 301242509...
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Final PresentationFinal PresentationWinter 2010Winter 2010
Performed by:Performed by:Tomer Michaeli 052792769Tomer Michaeli 052792769Liav Cohen 301242509Liav Cohen 301242509
Supervisor: Shlomo Beer GingoldSupervisor: Shlomo Beer GingoldIn collaboration with:In collaboration with:
characterization of synchronizerscharacterization of synchronizers and metastabilityand metastability
Project subject
Direct measurements of synchronization Circuits and comparison to results on
chip [5].
Project goals
Learn the direct measurement method. Building and improving of a measurement
system for synchronization to characterize performance of synchronizers.
Comparison to measurements results on chip [5]
Achievements Learning the measurement system. Learning the chip characteristics and its GUI. Learning a technique to get and save
scope’s measurements. Measuring synchronizer metastability Analyzing the results Comparing to results on chip.
Theoretical background Many Globally Asynchronous Locally
Synchronous (GALS) systems are susceptible to failure because of a Tsetup / Thold violation.
In order to prevent that we use synchronizers A common way of implementation is with N
cascaded FF’s which have the target system’s clock
Theoretical background - cont. A schematic figure of the system:
Theoretical background - cont. The main index which defines the system reliability is
Mean Time Between Failures (MTBF):
While – Fc and Fd are the receiver and sender system
frequencies, respectively. is a parameter related to the synchronizer input. is the resolution time constant S is the predetermined time for metastbility
resolution and defined as N is the number of cascaded FF’s and .
S
τ
C D W
e(1) MTBF=
F F T
WT
( 1) CS N T 1C
C
TF
Theoretical background - cont.
pdt
t
sut htWT
Theoretical background - cont. As technology improves, the frequency scaling
reduces the MTBF
The parameter in equation (1) is predominant since its effect on MTBF is exponential.
To maintain high MTBF, the factor has to lessen, and that was the common assumption.
Theoretical background - cont. An article, which was published recently, contradicts
this assumption [2]
In the project we will examine those results
Project environment
Signal generator
Test Chip 65nm
FPGA board
DLP socket (PC) MUX socket
DSO80204B Agilent oscilloscope
Project Environment-cont.The test environment is composed by the FPGA board that generates control And data signals for the 65nm Synchronizer test chip.The FPGA board is controlled through USB (from PC) using a special DLPSocket and a dedicated software.
DLP chip
USB cable (from PC)
Control and data Signals to/from TC
Top level design
Fd [Hz]
Fc [Hz]
synchronizerDSO80204B
Scope
Input
TRIGGERData
PCCh1-Ch2
Searching for metastability
Fd (data)1/Fd [ns]
Fc (clock)
1/Fc [ns]
Synchronizer output
The frequency of the synchronizer output is (Fc-Fd) [Hz] Considerations in choosing the frequencies:
The frequencies Fc,Fd should be high. Choosing the difference (Fc-Fd) to be low, increases the
chance for metastablity ,but decreases the cases to measure.
)Fc-Fd] (Hz[
Measurements Measurements were performed at Vdd=1.1V and room temperature 2 DATA frequencies 3.125 [MHz] and 6.245
[MHz] were measured and clock frequency 6.25 [MHz]
Measurement period time: T=200 [sec] for each delay value.
Measurements were executed on 3 different chips
Results analyzing by MATLAB
Measurements- JITTER Calculating the measurements noise for a
square signal with frequency=6.25 [MHz]:
Noise measurement ~ 50 [psec]
2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.50
2000
4000
6000
8000
10000
12000
14000
16000
18000
[nsec]
sam
ples
jitter histogram
noise
Top level design
Fd [Hz]
Fc [Hz]
synchronizer
clock (Input)
Data (TRIGGER)
PC
3.125MHz \ 6.245MHz
6.25MHz
Choosing one of the synchronization circuits :-regular FF -synchronizer 1-synchronizer 2
F_data=(Fc-Fd)[Hz]
Calculating the delay between clock rising to data rising by the scope
Getting the measurements values from scope to PC by VEE program
Measurements Calculating ,by the scope , the delay between the DATA signal (synchronizer output) and the clock signal (Ch1-Ch2), which mean thedelay between clock rising to the datastabilizing
Measurements
Getting the measurements values from the scope to PC by VEE program (with GPIB connection):
0 1 2 3 4 5 6 7 8 9 10
x 105
8
9
10
11
12
13
14
15
16
Trace S/N
nsec
Computed Intertrace delay vs. Trace S/N
Measurements Creating histogram for N samples.
1M samples histogram
Measurements Calculate number of measurements up to delay S [sec] (‘reversed distribution function’).
8 9 10 11 12 13 14 15 160
2
4
6
8
10
12
14log(counts>delay) vs. delay [nsec]
log
(cou
nts>
dela
y)
delay [nsec]
ln #(> S)
Measurments Using the equation:
after some math:
Drawing the graph for equation (3) which its slope is and finding .
Calculating :
S
τ
C D W
T e(2) MTBF= =
#(>S) F ×F ×T
C D W
XY ba
1(3) ln #(>S) = - (S) + ln F ×F ×T ×T
τ
1
b_graph
WC D
eT =
F ×F ×T
WT
Measurements Graphs for a regular FF with Frequencies Fc=6.25
MHz and Fd=3.125 MHz and its parameter Varying slope-calculating para’ for 2 segments.
8 9 10 11 12 13 14 15 160
2
4
6
8
10
12
14
X: 13.92Y: 10.68
log(counts>delay) vs. delay [nsec]
log
(cou
nts>
dela
y)
delay [nsec]
X: 14.94Y: 3.466
X: 15.05Y: 2.485
X: 14.08Y: 9.985
12 13 14 15 16 17 18 190
100
200
300
400
500
600
700
800
900
1000
X: 14.02Y: 235.1
TAU vs. delay
TA
U [
psec
]
delay[nsec]
X: 14.98Y: 111.3
Slope=1
LD (long delay)
SD (short delay)
SD
LD
Results Similar graphs were made for synchronizer 1
circuit and for synchronizer 2 circuit [5] on 3 different chips.
The synchronization parameters and were calculated from the graphs.
WT
Results – cont.[p
sec]
[pse
c]
Results-cont. results on/off chip:
Previous results
168
135 160
[pse
c]
Conclusions The test result for is in the same order of
magnitude as the on chip results The structure of the synchronizer effects
much on the value of . As opposed to the previous measurements,
we get the highest value of for regular FF circuit and the lowest value for synchronizer 2 circuit (XOR feedback FF).
Conclusions A measurement noise distorted some of the
results additional tests on chips should be made in
order to get more statistics
References 1. Yaron Semiat and Ran Ginosar, ‘Timing Measurements of Synchronization
Circuits’ , Technion, Haifa, 2003.2. Shlomo Beer Gingold, ‘Test Chip (Sinc_test_chip)’, Technion, Haifa.3. Salomon beer ,Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin and
Avinoam Kolodny, 'The Devolution of synchronizers', Technion, Haifa, 2010.4. Lindsay Kleeman & Antonio Cantoni, 'Metastable Behavior in Digital
Systems' , University of Newcastle, New South Wales, 1987.5. Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin and
Avinoam Kolodny, 'An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm' , Technion, Haifa.
6. DLP Design, 'DLP-USB245M-G USB to FIFO Parallel Inetrface Module', 1605 Roma Lane, Allen TX 75013.
7. 'Xilinx University Program Virtex-ll Pro Development System', UG069 , March 8,2005