final presentation fast ethernet card with fpga project num. 0622 students: alex shpiner
DESCRIPTION
- PowerPoint PPT PresentationTRANSCRIPT
21.12.03
הטכניון - מכון טכנולוגי לישראל
המעבדה למערכות ספרתיות מהירותהפקולטה להנדסת חשמל
Final PresentationFinal Presentation
Fast Ethernet Card with FPGAFast Ethernet Card with FPGAProject num. 0622Project num. 0622
Students:Students: Alex ShpinerAlex Shpiner
Eyal AzranEyal Azran
Supervisor:Supervisor: Boaz MizrahiBoaz Mizrahi
FeaturesFeatures Transmitting and Receiving Ethernet framesTransmitting and Receiving Ethernet frames
MAC and PHY configuration controlMAC and PHY configuration control
Driver Software for controlling card interfaceDriver Software for controlling card interface
Full control by the driver of the MAC features:Full control by the driver of the MAC features:
Full/Half DuplexFull/Half Duplex
10/100 Mb/sec 10/100 Mb/sec
MAC address configurationMAC address configuration
64 bit Multicast Filter64 bit Multicast Filter
The work flow
Time line
VHDL studying
Developing the algorithms
Synthesis & Debug
Writing the code
Simulations
March to April 2003May 2003
June to August 2003Sep. to Oct. 2003November 2003
CIF – CPU Interface UnitCIF – CPU Interface Unit
CIFPLX
• Passing information (data, control signals) from PLX to all other entities.• Decode the address given from PLX and passing the data to the addressed unit.
Configuration UnitsConfiguration Units
• GNR – General Configurations Configures MAC and PHY’s pins
• MCF – MAC Configuration Configures MAC's Internal configuration registers
GNR
MCF
CIF MAC
PHY
Transmitting and Transmitting and ReceivingReceiving
TRN
RCV
ARB
• TRN – Transmitting unit• RCV – Receiving unit• The arbitration algorithm will be overviewed in the next slides
CIF
MAC
Testing UnitsTesting Units
CIFTRN
RCVPLX
MAC
PCT CIT TRT
• Used during debugging• Checks the correctness of the protocols.• Filling the internal register upon signals on checked bus.• Internal registers are read through CIF.• Have addresses on memory map.
The arbitration module – The arbitration module – The ProblemThe Problem
I want to send mail to my boyfriend!
I want to download the latest exercise in HEDVA!!
I want to send mail to my boyfriend!
The arbitration module – The arbitration module – The ProblemThe Problem
I want to download the latest exercise in HEDVA!!
Problem - there is only one bus from FPGA to MAC!
I want to send mail to my boyfriend!
The arbitration module – The arbitration module – The ProblemThe Problem
The arbitration module – The arbitration module – The SolutionThe Solution
ARBTRN RCV
request
done
grant
done
request
grant
Algorithm is based on Preemptive Round Robin
Differential quantum
Early finish option
RCV has higher priority
Design considerationsDesign considerations TRN quantum
RCV quantum
TRN FIFO size
RCV FIFO size
All calculations can be found in the project book.
Future versions may include…
• Frame processing
DecodingEncryptionCompression
• Ping reply in hardware
Future versions may include…
• Frame processing
DecodingEncryptionCompression
• Ping reply in hardware
• Frames filter in hardware
Future versions may include…
• Frame processing
DecodingEncryptionCompression
• Ping reply in hardware
• Frames filter in hardware
• And so on…