final cmos course file1
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COURSE FILE
Syllabus & Scheme
RAJIV GANDHI PROUDYOGIKI VISHWAVIDYALAYA, BHOPAL
PROGRAMME: Electronics and Communication Engineering
COURSE: EC-802 CMOS Circuit Design
Category of course
Course Title Course
code
Credit-4C Theory paper (ES)
DC-23 CMOS Circuit Design
EC-802 L
3
T
1
P
2
Max. Marks-100
Min. Marks: 35
Duration: 3 hrs.
Course Contents
Unit I
Single-Stage Amplifier: Basic Concepts, Common Source Stage, Source Follower,
Common-Gate Stage, Cascode Stage.
Frequency Response of Amplifiers: General Consideration, Common-Source Stage, Source
Followers, Common-Gate Stage, Cascode Stage, Differential Pair.
Unit II
Differential Amplifier: Single-Ended and Differential Operation, Basic Differential Pair,
Common-Mode Response, Differential Pair with MOS Loads, Gilbert Cell.
Feedback Amplifier: General Consideration, Feedback Topologies, Effect of Loading,
Effect of Feedback on Noise.
Switched-Capacitor Circuits: General Consideration, Sampling Switches, Switched-
Capacitor Amplifier, Switched-Capacitor Integrator, Switched-Capacitor Common-Mode
Feedback.
Unit III
Oscillator: General Consideration, Ring Oscillator, Voltage Controlled Oscillator,
Mathematical Model of VCOs.
Phase-Locked Loops: Simple PLL, Charge-Pump PLLs, Non ideal Effects in PLLs,
Delayed-Locked Loops.
Unit IV
Sequential Circuit Design: Introduction, Sequencing Static Circuit, Circuit Design of
Latches and Flip-Flops, Static Sequencing Element Methodology.
Array Subsystem: Introduction, SRAM, DRAM, Read-Only Memory, Serial Access
Memories, Content-Addressable Memory, Programmable Logic Arrays.
Unit V
Datapath Subsystems: Introduction, Addition/Subtraction, One/Zero Detector, Comparators,
Counters, Boolean Logic Operation, Coding, Shifters, Multiplication, Division, Parallel-
Prefix Computations.
References:
1. B. Razavi: Design of Analog CMOS Integrated Circuits, TMH Publication.
2. Weste, Harris and Banerjee: CMOS VLSI Design, Pearson Education
3. J. M. Rabaey, Digital Integrated Circuits, PHI Learning.
4. R. Jacob Baker: CMOS-Circuit Design, Layout and Simulation, Wiley.
5. A. A. Raj and T. Latha: VLSI Design, PHI Learning.
List of Experiments:
Practicals should be performed using any Electronic Design Automation (EDA) - eg.
Microwind / Cadence / Sylvaco / Tanner silicon HiPer / Xilinx ISE 9i or any similar
software.
1. Design and simulation of: (a) Common source amplifier (b) Source follower amplifier
(c) Common gate amplifier (d) Cascode amplifier.
2. Estimation of frequency response of: (a) Common source amplifier (b) Source follower
amplifier.
(c ) Common gate amplifier (d) Cascode amplifier.
3. Design and simulation of differential amplifier.
4. Design and simulation of feedback amplifier.
5. Design and simulation of oscillators: (a) Ring Oscillator (b) L-C Oscillator (c) Voltage
controlled Oscillator.
6. Design and simulation of: (a) Adder (b) Subtractor (c) One/zero detectors (d) Comparator
(e) Counter (f) Multiplier (g) Divider.
Academic calendar
Time Table
Lecture Plan
LECTURE PLAN
Format No. EC/12/13
Issue 01
Page No: 12 / 1
Department Electronics & communication Session : 2012-2013
Name of Teacher Er. PRADEEP RAGHUWANSHI Semester Even
Subject CMOS Circuit Design Sub. Code EC-802
TIME SCHEDULE : Total expected periods: 50, Extra periods (if required)
Day Mon Tue Wed Thu Fri Sat Max.
available
No. of
Periods - - - - - - -
Lect. Topics to be covered Date of
Completion Remarks
1. Unit I: Single-Stage Amplifier: Basic Concepts.
2. Common Source Stage, Source Follower.
3. Common-Gate Stage, Cascode Stage.
4. Frequency Response of Amplifiers: General Consideration, Common-Source Stage.
5. Source Followers, Common-Gate Stage.
6. Cascode Stage, Differential Pair.
7. Numerical
8. Unit II: Differential Amplifier: Single-Ended and Differential Operation.
9. Basic Differential Pair, Common-Mode Response.
10. Differential Pair with MOS Loads, Gilbert Cell.
11. Feedback Amplifier: General Consideration, Feedback Topologies.
12. Continue this topic…..
13. Effect of Loading, Effect of Feedback on Noise.
14. Switched-Capacitor Circuits: General Consideration, Sampling Switches.
15. Switched-Capacitor Amplifier, Switched-Capacitor Integrator.
16.
Switched-Capacitor Common-Mode Feedback.
Numerical
17. Unit III: Oscillator: General Consideration, Ring Oscillator.
18. Voltage Controlled Oscillator, Mathematical Model of VCOs.
19. Phase-Locked Loops: Simple PLL.
20. Charge-Pump PLLs
21. Non ideal Effects in PLLs
22.
Delayed-Locked Loops.
Numerical
23. Unit IV: Sequential Circuit Design: Introduction,
Sequencing Static Circuit.
24. Circuit Design of Latches and Flip-Flops.
25. Static Sequencing Element Methodology.
26. Array Subsystem: Introduction, SRAM.
27. DRAM
28. Read-Only Memory
29. Serial Access Memories
30. Content-Addressable Memory
31. Programmable Logic Arrays. Numerical
32. Unit V: Datapath Subsystems: Introduction.
33. Addition/Subtraction.
34. One/Zero Detector.
35. Comparators.
36. Counters.
37. Boolean Logic Operation.
38. Coding(Coder)
39. Shifters.
40. Multiplication(Multiplier), Division
41. Parallel-Prefix Computations.
42. Numerical.
Prepared By : A.P. Pradeep Raghuwanshi Approved By (HOD):
Name of Reference books
Name of reference books:-
Sl. No. Author Name of the book Publication
1. B. Razavi
Design of Analog
CMOS Integrated
Circuits
TMH Publication
2. Weste, Harris and
Banerjee
CMOS VLSI
Design Pearson Education
3. J. M. Rabaey Digital Integrated
Circuits PHI Learning
4. R. Jacob Baker
CMOS-Circuit
Design, Layout and
Simulation
Wiley
5. A. A. Raj and T.
Latha VLSI Design PHI Learning
Tutorials
TUTORIAL CMOS CIRCUIT DESIGN
UNIT I Single-Stage Amplifier:
UNIT I. Frequency Response of Amplifiers
UNIT II Differential Amplifier
FIG. 4.39
FIG. 4.40
FIG. 4.41
FIG. 4.42
FIG 4.43
FIG.4.44
FIG.4.44
Mid semester question
Papers
B.E. (Eighth Semester) MID SEM EXAMINATION, March., 2012
(Electronics & Communication Engg. Branch)
CMOS CIRCUIT DESIGN [EC-802]
Time: Two hours, Max. Marks: 50, Pass Marks: 18
Note: Attempt any five questions .All questions carry equal marks.
Unit - I
Q1. Draw the analog design octagon and explain how the trade of between various
parameters is obtained?
Q2. Discuss the single-stage common –source amplifier and also derive the equation for its
voltage gain.
Q3. Discuss the single-stage common –gate amplifier and also derive the equation for its
voltage gain.
Q4. Discuss the single-stage Cascode amplifier and also derive the equation for its voltage
gain.
Q5. Discuss the single-stage Source Follower amplifier and also derive the equation for its
voltage gain.
Q6. Discuss the single-stage Differential Pair amplifier and also derive the equation for its
voltage gain.
B.E. (Eighth Semester) PUT EXAMINATION, April., 2012
(Electronics & Communication Engg. Branch)
CMOS CIRCUIT DESIGN [EC-802]
Time: Three hours, Max. Marks: 100, Pass Marks: 35
Note: Attempt any five questions .All questions carry equal marks.
Q1 (a) Draw the analog design octagon and explain how the trade of between
various parameters is obtained?
(b). Discuss the single-stage Cascode amplifier and also derive the equation for its
voltage gain
Or
Q2 (a) Discuss the single-stage Cascode amplifier and also derive the equation for its
voltage gain.
(b). Discuss the single-stage Differential Pair amplifier and also derive the
equation for its voltage gain.
Q3. (a) Explain how Gilbert cell can be used in differential amplifier. Also draw neat
circuit diagram of Gilbert cell.
(b) Discuss how the feedback circuits in amplifier help in:
(i) Gain desensitization
(ii) Impedance modification
Or
Q4. (a) Draw a basic switched–capacitor amplifier and explain its operation. How is it
different from conventional amplifier?
(b) Explain how Differential Pair with MOS Loads can be used in differential
amplifier. Also draw neat c ircuit diagram of Differential Pair with MOS Loads.
Q5. (a) Explain why a single common source (CS) stage does not oscillate if it is
placed in unity gain loop.
(b) Draw a differential implementation of ring oscillator. Explain how it works.
Also calculate the maximum voltage swing of each stage.
Or
Q6. (a) Draw the basic block diagram of phase locked loop (PLL) and explain its
operation with neat waveform.
(b) Explain how a master slave D flip-flop can be used a phase/frequency
detector. What are its limitations?
Q7. (a) Draw and explain the architecture of 4 x 6 MOS NAND ROM with suitable
example and compare it with MOS NOR ROM with respect to:
(i) Layout area
(ii) Voltage swing
(iii) Propagation delay
(b) Discuss the operation of one transistor dynamic cell. Explain the read write and
refresh operations with the help of path diagram and associated waveforms.
Or
Q8. (a) Discuss the architecture of a 3-input, 2 output PLA. Implement the following
function through the above PLA device:
f0 = x1 + x
f1 = x0x1x2 +x2+x0x1
(b) Discuss in detail Content Addressable Memory (CAM) and its applications.
Q9. (a) Draw the transistor level circuit diagram of a positive edge triggered D flip-
flop with synchronous set and reset control signals and explain its operation.
(b) A parity generator is to be implemented for data path subsystem. Draw its
conventional implementation using XOR gate. Also explain its CMOS dynamic version.
Or
Q10. (a) List various types of adders used in data path sub- systems. Explain with
block diagram carry select adder. How does it increase the speed of operation?
(b) List various binary multiplication algorithms. Discuss Wallace-tree
Multiplication algorithm with appropriate example.
University question papers
Class-Notes
LECTURE NOTES OF CMOS CIRCUIT DESIGN(EC-802)
Attendance