FC Video Controller

Performed by:Kapshitz TsachyGrinkrug Michael

Instructor:Alex Gurevich

Cooperated with:Elbit Systems Ltd.

Technion - Israel institute of technology, department of Electrical Engineering

High speed digital systems laboratory

Abstract

Input: Fiber Channel

Frames that include Audio-Visual containers

Controller Configuration

Output: Video objects in

resolution of pixels (pixel per clock)

Ancillary objects in resolution of DWords (except the last one)

Status

Toplevelblockdiagram Data to CRC calc. [31:0]

f/2

f

Data

[31:0

]

Conta

iner_

Data

[31:0

]D

ata

[31:0

]

CO

M_W

RX

[7:0

]

RX

[15:8

]

RC

LK

CO

M_D

ET

BC

Valid

_C

ont_

Data

_R

eady

C O N TA IN E RC O N TR O LLE R

FR A M EC O N TR O LLE R

IN PU T U N ITN

ew

_C

onta

iner

val

f /2 Clock

BC

Video Index configuration

StatusInterface

Container_Conf_Register

Container_Status_Register

Fram e_Conf_Register

Fram e_Status_Register

Conf_Stat

ConfigureInterface

R [7:0

]

G [7:0

]

B [7:0

]

val

new

_cont

res

c lk_high

CRCGener

ator

CRC

Start_End_CRC

new

end

new

_fielda

nc_re

ad

obj_

read

F

f/2

Input Unit

Combines input words into Dwords

comma signal is passed together with the comma DWord

Generates clk_low clock:clk_low = rclk/2

Input_Unit

IU_Logic IU_LOAD_FSM

rx_d

ata

[15:

0]

com

_det

rclk

gbl_

rst

ld [1:0]

iu_f

c_da

ta

[31:

0]clk

_low

iu_f

c_co

mm

a

Frame Controller

Fram e HeaderAnalyzer

FSM

Sequence FollowerFSM

fc_data[31:0]

fc_comma

fc_newcont

Suspender

fc_cc_data[31:0]

Fram e Controller

fc_check_seq

fc_seq_det

iu_fc_data[31:0]

iu_fc_comma

Frame fie ldsComparator

fc_CS_set_EOF

fc_aux_data(CRC bus)

fc_CS_set_CRC

conf_CRC

conf_EO F

conf_ven_unique

conf_did

conf_video

conf_SO F

Byte_fillextract

fc_byte_fill# fc_valid_4cont

fc_cc_bcfc_cc_val

fc_cc_newcont

fc_fr_status_rdyRSFFfc_st_rd_rst

R

S

fc_CS_set_SOF

fc_CS_set_RCTL

fc_CS_set_DID

fc_CS_set_TYPE

fc_CS_set_SEQ

ended_well

fc_load_bf

(to CRC generator)

Start_End_CRC

Parses Frame Headers

Passes through only legal frames:

SOFDIDRCTL

TYPESEQEOF

CRC is calculated by an external unit and the result is compared

Container Controller

Parses Container Header

TypeIndexSize

Extracts ancillary and video objects

Outputs the data through separate interfaces

HeaderAnalyzer

A ligner_Anc

data

[31:

0]

valid bc

new

_con

tain

er

data

[31:

0]

valid bc

new

_con

tain

er

data

[41:

0]

RD

RE

Q

get_ index

index[15:0]

extr

act[2

:0]

Index Table

size

/ of

fset

[2:0

]

Conf_Stat interface

block

resolution

entry[2:0]

index[15:0]

res

set

clr

new

_con

tain

er

data

[31:

0]

obj_

be[3

:0]

obj_

split

[3:0

]

anc_

be[3

:0]

anc_

split

[3:0

]

anc_

cut

Anc_FIFO Obj_FIFO

Aligner_Obj

data

[41:

0]

RD

RE

Q

Dat

a [3

1:0]

val

BC

R [7

:0]

G [7

:0]

B [7

:0]

val

new

_con

t

res

new

end

n ew

_fie

ld

anc_read

obj_read

new

_con

tain

er

ObjectsExtractors

FIFO size calculation

FS - video Frame Size (in pixels)

F1 - Fibre Channel frequency

F2 - Aligner frequency (in pixels)

SZ1 - FIFO size in case of 1 byte per pixel resolution

SZ3 - FIFO size in case of 3 byte per pixel resolution

SZ - FIFO size in general case = MAX(SZ1, SZ3)

SZ1 =

SZ3 =

The typical video frame rate is 30 fps => overall byte throughput is: 30xFS 14.5 MHz

Thus, synthesizing for clk_high higher than this value and choosing a sufficient FIFO size, the Controller will manage to process the protocol.

12

212

F

FFFS

12

23123

F

FFFS

Example

Let's take some typical values: FS = 910 x 525 =

477750 480KB F1 = 53 MHz F2 = 25 MHz

SZ = MAX(365074, 419159) = 419159 ~ 420KB

For Apex20KE-1X: FS = 480KB F1 = 53 MHz F2 = 41 MHz

SZ ~ 290KB

2526

2728

2930

3132

3334

3536

3738

3940 SZ3

SZ1

0

50,000

100,000

150,000

200,000

250,000

300,000

350,000

400,000

450,000

1 / 3 Bytes pixels

clk_high frequency

FIFO size [Bytes]

SZ3 SZ1

FIFO size vs. clk_high frequency

‘Real life’ solution

In order to implement the above using the conventional FPGA’s, external FIFO can be used 5 parallel 9x128KB 2 pipelined 80x64KB

Manufactures: Cypress IDT

FC - below FIFO

FC - above FIFO

External

FIFO

Testing Process

FC

G ide l P R O C 20K P C I

Mem

ory

M ultiP o rt a M u ltiP o rt b

rclk

clk_high

TESTDATA[31:0]

OBJOUT[31:0]

ANCREAD[31:0]

ANCFLAGS[7:0]

ANCOUT[31:0]

OBJREAD[31:0]

LINE[15:0]

BankB

BankA

Configuration

32M B

32M B

test_bus[63:0]

F=lclk F=lclk

F= clk

1

2

3 3 3

4 4

0

SW

AV containers are generated using a SW program, randomizing size and other parameters

The containers are divided into FC frames, randomizing their size and adding frame headers

Expected output files are generated for ancillary and video data separately

This methodology enabled sufficient test case coverage