fault injection in mixed-signal environment using behavioral fault modeling in verilog-a
DESCRIPTION
Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A. Sharif University of Technology Department of Computer Engineering Dependable System Lab [DSL] . Seyed Nematollah Ahmadian , Seyed Ghassem Miremadi Behavioral Modeling and Simulation (BMAS) Conf. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/1.jpg)
Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A
SeyedNematollahAhmadian,SeyedGhassemMiremadi
BehavioralModelingandSimulation(BMAS)Conf.September2010
SharifUniversityofTechnologyDepartmentofComputerEngineering
DependableSystemLab[DSL]
1
![Page 2: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/2.jpg)
Outline
Dependability MixedSignalFlow BehavioralFaultModeling FaultModels
SingleEventTransient/Upset(SET/SEU) PowerLineDisturbance(PLD) ElectroMagneticInterference(EMI)
Results
2
![Page 3: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/3.jpg)
DependabilityandReliability
DependabilityandReliability Notjustwords!
Aneffectivetechniquefortheexperimentaldependabilityevaluation
Weproposeasimulation-basedfaultinjectionmethodinmixed-signalenvironment.
3
![Page 4: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/4.jpg)
PreviousFaultInjectionTools
Levelofabstraction
HDL Circuit HDL CircuitDoes not include enough details For accurate modeling
Too slow, too old. cannot include verification method like
testbenches, etc.
solution:Mixed-signal fault injection
4
![Page 5: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/5.jpg)
Flow
FaultinjectionandsimulationisperformedinMixed-Signalenvironment Performance/Accuracytradeoff
MoreaccuratethanRTLsimulationFasterthanSPICEsimulation
FaultinjectiononSoCswithanalogcoresPLLs,DLLs,SRAMs,…
5
![Page 6: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/6.jpg)
Flow
SPICEsimulationnearthefaultsite: accuratefaultsimulation
HDLSimulation(elsewhere) Motive:Mostofthefaultmanifestthemselvesasanderror
outsidethefaultsite HDLsimulationprovidesenoughaccuracytocontinuesimulation.
Originaltestbenches/verificationscriptsareintact Fastersimulation.CancompensatefortheSPICEsimulation
penalty.
6
![Page 7: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/7.jpg)
FaultModeling
Wedevelopfaultmodelsinbehavioralmodelinglanguages(suchasVerilog-A) Easymodeling Reducedevelopmenttime Accuratesimulations Accesstointernalnodes/structureoftransistor/electricalelement
7
![Page 8: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/8.jpg)
Tool-chainarchitecture
Mixed-signalthree-levelofabstraction
FaultsareembeddedinsideVerilog-Amodel. ResultedfaultmodelsareinsertedtoCircuitasanexternalcomponent
Design Under Test Unit Under TestConverted to SPICE
Replaced device modelWith
Fault Injection
Unit under test
FaultyCell/
device
HDL level Circuit Level Gate Level
Verilog/VHDLModelSim 6.5 SE
SPICE netlistSynopsys hsim
Verilog-A modelSynopsys hsim
8
![Page 9: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/9.jpg)
Faultmodels
Behavioralfaultmodeling SingleEventTransients/Upset(SET/SEU) Electro-MagneticInterference(EMI) PowerLineDisturbance(PLD)
Ourflowsupportsotherfaultmodelsaswell.
9
![Page 10: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/10.jpg)
SETFaultModeling
Cause:hittingahigh-powerparticleintotransistorsdiffusionarea.
Effect:transientcurrentspikeondiffusion,singleeventtransientandupset.
10
![Page 11: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/11.jpg)
Electro-MagneticInterferenceModeling
EMorRFinducedinterference
ModeledasaContinues-waveRFIsuperimposedonspecificnodes. Input Clock …
11
![Page 12: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/12.jpg)
PowerLineDisturbanceModeling
CommonPLDs: Powersupplynoise Overshoot,Undershoot
GroundBouncing
12
![Page 13: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/13.jpg)
Flow:Initialization/Injection
13
![Page 14: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/14.jpg)
Flow:Simulation/Evaluation
14
![Page 15: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/15.jpg)
ExperimentalSetup
Weusedthefollowing3rdpartytoolsandIPs: HDLSimulator:ModelSim6.5SE SpiceSimulator:SynopsysHSIM2008.09 Process:TSMC0.25μm
Ourfaultcharacteristics: SET:Q=10pc,withTO=TB=10ns,Randominjection,Twoexponentialmodel
EMI:100MHzCWRFsignal,Vpeak=0.5V,100nspulseenvelope,Randominjection
PLD:100nsduration,Voltageshortage(from2.5Vto0V)onVDDline,Randominjection
15
![Page 16: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/16.jpg)
ResultsofSystemFailures
Counter FSM ALU SRAM UART AVERAGE0
10
20
30
40
50
60
70
80
90
100
PLDEMISET
16
![Page 17: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A](https://reader034.vdocuments.site/reader034/viewer/2022042822/56815e4f550346895dccc989/html5/thumbnails/17.jpg)
Thankyou!
Questions?
Thankyouforyourattention.
17