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1 Fast Algorithms for Thermal Analysis of 3-D VLSI Chips Fast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder GSRA: Baohua Wang The University of Michigan Ann Arbor, MI 48109-2122 International Symposium on Circuits and Systems Earlier Generation 3-D System Integration In Mission Critical (Space and Military) Applications High Performance and Light Weight are Paramount Examples of Earlier Generation 3-D Wafer Scale Integration Harris Semicon- ductors 3-D Memory Module Jet Propulsion Laboratory Advanced Flight Computer (AFC) Raytheon Aladdin Parallel Processors to the Night Vision Electronic Sensors Directorate (NVESD) Texas Instru- ments High density 1.2 Giga bit solid state recorder

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Page 1: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

1

Fast Algorithms for Thermal Analysis of 3-D VLSI ChipsFast Algorithms for Thermal Analysis of 3-D VLSI Chips

Prof. Pinaki MazumderGSRA: Baohua Wang

The University of MichiganAnn Arbor, MI 48109-2122

International Symposium on Circuits and Systems

Earlier Generation 3-D System Integration

In Mission Critical (Space and Military) ApplicationsHigh Performance and Light Weight are Paramount

Examples of Earlier Generation 3-D Wafer Scale Integration

Harris Semicon-ductors 3-D Memory Module

Jet Propulsion Laboratory Advanced Flight Computer (AFC)

Raytheon AladdinParallel Processorsto the Night Vision

Electronic Sensors Directorate (NVESD)

Texas Instru-ments High density 1.2 Giga bit solid state recorder

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3-D VLSI Chip: Problems and Challenges

1. Degradation of Reliability due to Thermal Rundowns

2. Identification of Hot Spots in Active Layers in 3-D Chips

3. Avoidance of Hot Spots by Thermal-aware Block Placement

4. Fast computation of Thermal maps due to power dissipationin multiple active layers of transistors and interconnects

5. Development of appropriate Heat Sinking Technology

Goal: To Design Commercial High-Performance, Low-Power Hand-Held Systems

N+/P+ N+/P+

N+/P+ N+/P+

VIA

ActiveDevice

substrate

V-IC

I/O device

Key Requirement: Thermal Engine havingHigh Accuracy v. Low Computation Time

3-D VLSI System on a Multi-Active Layered Chip (Advanced SoC)

Problems and Challenges

Thermal Problem Definition Time Variant Thermal Equation

Boundary Condition:

Steady-State Thermal Analysis

T: temperature [K], k: thermal conductivity [W/(mK)], g:power density [W/m3],: thermal diffusivity[m2/s], h: heat transfer coefficient.

=k/pc: p: density [kg/m3] and c:specific heat [J].

2 , , ,1 1

, , , , , ,, , , ,

T x y z tT x y z t g x y z t

x y z x y z t

, , ,, , , , , , ,

T x y z tk x y z hT x y z t f x y z

ini

/ V2

Poisson’s Eqn.

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Equivalent Thermal Network Approach Modeling Procedure for Circuit Network Method

Electric Current (I) Heat flow (Q); Voltage (V) Temperature (T); Electrical Resistance (R) Thermal Resistance (); Electrical Conductivity (G) Thermal Conductivity (

Model Order Reduction for the Resulting Equivalent Thermal Network using Krylov subspace method, Arnoldi algorithm, or PVL

Vz2

1 2.: 2, ,

2

2:

, , , , , , , ,

m m

dVElec C i G V V V

dt m x y z

i G V

TThermal c g k T

dtT V c C g x y z t i k x y z G

Chip Structure Equiv. Circuit Node Circuit System v. Thermal System

Thermal Analysis Methods

Two most efficient approaches:

Reduced Order Modeling of Equivalent Thermal Network for Chip Structures

Free Space Green’s Function Method

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Free-Space Green’s Function Approach Temperature can be obtained by spatial and temporal

convolution of heat sources with Green’s function since in reality the present type of thermal analysis leads to a linear system

Green’s function is the response of original system to Dirac Delta source, i.e., the transfer function of the original system

can be represented by

0

, , , , , , | ', ', ', ', ', ', ' ' 't

T x y z t G x y z t x y z g x y z dx dy dz d

2 1 1', ', ',

GG x x y y z z t

t

, , , | ', ', ',G x y z t x y z

, | ', , | ', , | ',G x t x G y t y G z t z

Free-Space Green’s Function Approach

First use Fourier Transform in the spatial domain, then Laplace Transform in the time domain:

Using image method further to account for the effect of heat insulation at z=0, it can be obtained that

| ', exp '2

se sG x x s x x

as

| ', exp '2

se sG y y s y y

as

| ', exp ' exp '2

se s sG z z s z z z z

a as

Page 5: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

5

Free-Space Green’s Function Approach

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The Framework for Free-Space Green’s Function Approach

Evaluation of time-domain free-space Green’s Function

Evaluation of Convolution Integral: Approximation of Error Function

Problems: Cannot handle Multiple active layer heterogeneous

heat conduction materials. In reality, it uses time-domain free-space Green’s

function to analyze the equilibrium states

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The Proposed Approach Based on Layered Green’s Function in Multilayer 3-D VLSI Difficulties

Multi-layered Green’s function itself is more complex than free space Green’s function

How to reduce the speed penalty of evaluating Green’s function itself

How to ensure the fast evaluation of temperature distribution when specific functions and transforms are presented.

Layered Green’s Function in Thermal Problem Thermal Problem Description

K is only function of z. The x-y plane can be assumed as infinite. Thus cylindrical coordinate system can be used

Hankel transform for further simplification. J0 :

zero-order Bessel function Spectral domain representation:

Mapping the infinite layered 3-D space into a 1-D infinite long rod.

Page 7: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

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Solution Using Transmission Line Analogies

Analogies

Evaluation of Layered Green’s Function Evaluation of transmission line impedance Z(s)

From Z(s) obtain Green’s function by taking inverse Hankel transform

Green’s Function FormulationOf Temperature Distribution v.Transmission Line Equation

Proposed Semi-analytical Green’s Function for 3-D VLSI Chips

Properties and Merits Leads to fast evaluation of Green’s Function

Leads to fast evaluation of temperature distribution

Does not incur sampling overhead of Green’s Function for interpolation

Considers both far-field and near-field calculations

Page 8: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

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Problems using Interpolation Method Evaluation of Z(s) and Green’s Function: Interpolation method

Given specific (zs, zt), Obtain Z(S), function of complex frequency S, and Evaluate G(, Z(S)) and Construct library of G(, Z(S)) by sampling with respect to (s, t) and .

Problems:

How to decide the number of sampling points and the position of the sampling points.

Use of Fast Hankel transform method to calculate G(, Z(S)) from Z(S) is still time-consuming if sampling points are too large.

Temperature evaluation is costly since numerical integration might involve too many space partitions.

ZR0

zs zt

lZcZL

Proposed Semi-analytical Green’s Function for 3-D VLSI Chips Analytical reformulation of Z(S) for (s, t) in the same

layer

Two parts broken into: Independent of (s, t),

Independent of transmission line properties: Kernel

V1

I1

V21

I21 I22

Iin

V3

I 3 I4

V4

ZL

ZR

0

zs z

t

lZc

ZL

ZR

V22

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Proposed Semi-analytical Green’s Function for 3-D VLSI Chips Analytical reformulation of Z(S) for (s, t) in multiple

layers

Two parts broken into: Independent of (s, t)

Independent of transmission line properties: Kernel

V1

I1

V22

I21

I22

I in

V3

I3

ZL1

ZR n

zs

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Ln-1Zc1Z

L1

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ZRn

Ln

zt

L2

Zcn

Zcn-1

Zc2

V4

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V5

I5

V21

Proposed Semi-analytical Green’s Function for 3-D VLSI Chips

Summary for Formulations

Formulations separate the items which are dependent on positions of source and target points from the intrinsic transmission line impedance properties at different sections.

It avoids sampling of Z(S) with respect to (s, t) since the transmission impedance properties between different sections can be pre-characterized, either entirely analytically or approximately analytically.

Then combine with Kernels to get the complete impedance representation

Page 10: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

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Proposed Semi-analytical Green’s Function for 3-D VLSI Chips

The object is to pursue fast thermal simulationSpatial convolution with Green’s function to obtain temperature distribution

The spatial convolution is usually done by numerical integration of Green’s function.

Problems Accuracy is related to number of spatial partitions.

Large number of partitions increase the computation time.

The effect of self heating cannot be considered accurately due to the singularity of Green’s function at that point.

dxdydzzyxdenszyxzyxGT ),,(',',',,

Proposed Semi-analytical Green’s Function for 3-D VLSI Chips Moments matching technique leads to analytical

temperature evaluation procedure.

Representing transmission line impedance by

and with exponential functions using modified Prony’s algorithm, which is usually used in statistics for estimating the distribution of data.

Inverse Hankel Transform can be done analytically.

sBij sDij

Page 11: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

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Proposed Semi-analytical Green’s Function for 3-D VLSI Chips

We have introduced weighted coefficients to account for the square-root decreasing rate of Bessel function w.r.t. to the radius in order to improve the accuracy in specific regions during the moments matching procedure by using modified Prony’s algorithm. For instance, near/far field can be discriminated.

To improve accuracy, the weighted version of modified Prony’s algorithm, known as pre-conditioned modified Prony’s algorithm, is designed.

The modification is made for the B-matrix as given below

Proposed Semi-analytical Green’s Function for 3-D VLSI Chips Temperature Evaluation

Superposition principle for such a linear system

Simple implication of integration than general numerical integration

Page 12: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

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Proposed Semi-analytical Green’s Function for 3-D VLSI Chips

Validation of Semi-analytical Green’s function

Proposed Semi-analytical Green’s Function for 3-D VLSI Chips Validation of Semi-analytical Green’s function

Page 13: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

13

Proposed Semi-analytical Green’sFunction for 3-D VLSI Chips

Thermal Simulation Results

Proposed Semi-analytical Green’s Function for 3-D VLSI Chips

Discussion Semi-analytical Green’s Function is space-

efficient without incurring sampling overhead of Green’s Function

Thermal analysis using semi-analytical Green’s Function is time-efficient.

Self-heating effect due to singularity of Green’s Function is addressed by semi-analytical Green’s Function.

Page 14: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

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Proposed Semi-analytical Green’s Function for 3-D VLSI Chips

Conclusion and Future Work Fast thermal analysis approach using Green’s

Function is proposed.

The thermal analysis approach is shown to be efficient.

Efficient semi-analytical Green’s Function technique is proposed. This is shown to be accurate vis a vis conventional numerical techniques.

Page 15: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Multivariate Normal Distribution Based Statistical Timing Analysis Using

Global Projection and Local Expansion

Prof. Pinaki MazumderUniversity of MichiganAnn Arbor, MI 48109

VLSI Design, January 3-7, 2005GSRA: Baohua Wang

05/18/01 V4.3

Page 16: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

There is no branch of mathematics, however abstract, which may not some day be applied to phenomena of the real world. --- Nikolai Lobatchevsky, N. Rose Mathematical Maxims and Minims

To create a good philosophy you should renounce metaphysics but be a good mathematician. - Bertrand Russell

Solutions to Sub-90 nm VLSI ProblemsInvolve Advanced Mathematics

Page 17: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Manufacturing Challenges at Sub-90 nm

Advancement by Device Shrinking Technology Node (nm)

0%

10%

20%

30%

40%

250 180 130 90 65

Leff

w, h,

Tox, Vth

3/m

ean

• Process Variations– Lithography: Lgate (±15%)– Doping: Vth (±30%), Leff (±15%)– Gate oxide: Tox (±4%)– Metal definition: line size (±20%)

• Circuit Operation– Power supply: Vdd (±10%)

– Crosstalk noise: Td / Td (>50%)

– Temperature fluctuation

Courtesy: Intel Web Site

Courtesy: Intel Web SiteCourtesy: Duane Boning & Sani Nassif

Page 18: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

N+/P+ N+/P+

N+/P+ N+/P+

VIA

ActiveDevice

substrate

V-IC

I/O device

2-D Lateral IntegrationExample: DEC EV Microprocessor

500 Million transistors

Goal: 3.5 billion transistors

3-D Vertical Integration

Multiple Active Layers

Future Goal: 200 Active Layers

Trends in Chip Integration Technology

Page 19: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Environmental and Operating Conditional Variations

Accurate Estimation of Full-ChipIR-drop at Sub 1 V Supply Voltage

Thermal Distribution in a 3-D Chip by LayeredGreen’s Functions

Formidable Mathematical Challenges

0 20 40 60 80 100x µm

0

20

40

60

80

100

yµ m

( )

( )

ThermalPlot onThird layer

ThermalPlot onFirst layer

Wang and Mazumder, ISCAS 2004,Fast Thermal Analysis via Semi-analyticGreen’s function in Multi-layer Materials

N+/P+ N+/P+

N+/P+ N+/P+

VIA

ActiveDevice

substrate

V-IC

I/O device

0 20 40 60 80 100x µm

0

20

40

60

80

100

ym

( )

()

Page 20: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Layered Green’s Function in 3-D Thermal Modeling

• Thermal Equation in Cylindrical coordinate system

• Apply Hankel transform

• Map the infinite layered 3-D space into a 1-D infinite long rod.

V1

I1

V22

I21

I22

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V3

I3

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ZR n

zs

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zt

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Page 21: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Green’s Function based ThermalMapping in a 3-D VLSI Chip

• Obtain Green’s function values and then the steady statetemperature profile on each layer

Moment MatchingBy Modified Prony’sAlgorithm

Page 22: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Thermal Modeling for 3-D VLSI Chip

0 20 40 60 80 100x µm

0

20

40

60

80

100

y m

( )

( )

0 20 40 60 80 100x µm

0

20

40

60

80

100

yµm

( )

()

0

10

20

30

40

50

60

70

80

30 50 70 90 110

Mobility

V-thresh

S/D Res.

On Circuit Parameters

• Mobility Degradation• Threshold Voltage Shift• Source/Drain Sheet

Resistance Variation

Pre-computed Green’s Function

Thermal Maps: Layer 1 and Layer 3

Page 23: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Principal Component Analysis (PCA)

BSIM 4.0 has 184 model parameters; however, usingPCA it has been found that only 21 Independent ProcessParameters account for 82% of variance for the original correlated parameter sets.

Dominant parameters are: Leff (20.5%), Tox (19.1%), K1, Bias coefficient (16.0%), U0, Mobility of PMOS (13.3%), and Weff of NMOS (12.8%).

CMOS Manufacturing Tolerances

PCA is used for selecting the basis function in Global Projection of Global Variables

Page 24: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Gate Delay Scattering

• Global Sources of variations Xg: Leff, Vdd, Tempr.• Global Sensitivities are M

• Local Gate Delay Variation, XM

lM

lM

jg

n

j

jMMM XXD

1

Canonical Gate Delay Model:

Data Source: Li Zheng Zhang, et al., University of Wisconsin

Page 25: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Canonical Delay Models at Fan-in and Fan-out Nodes

Fan-in Node Delay Model:

Fan-out Node Delay Model:

p

q

r

]),( cov

),( cov[),( Cov

),(Cov

1

jqr

jpr

jgq

jpr

jgp

n

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XA

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Ap

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p

r

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jps

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pspprpsplit

XA

A

DADA

Page 26: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

? AAA ,

BBB ,

MAMAE ,

MBMBF ,

),min(),min( , FEFEX

),max(),max( , FEFEY

Propagation of Covariance Through Gated Network

?

Derivation of Sum, Min and Max Values from Input Variables and Gate Model

Question:

How to DeriveThe OutputCovarianceby propagatingArrival timesFrom inputsTo output?

Page 27: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Multivariate Normal DistributionExisting techniques:

Can Handle Only Bi-variate Normal Distributions Difficult to compute covariance of

Min/Max of more than 2 Variables

Objectives of Wang-Mazumder’s Paper:To handle multiple input gatesTo improve accuracy (using Global Projection)To improve speed of analysis by unifying

smaller gates into a multi-input larger block To handle re-convergence paths problem

(using Local Expansion)To develop mathematical framework for generalclass of circuits using k-normal multivariate statistics

Page 28: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Theory of Covariance• Generalized Siegel’s formula

Cov [Xm, X(i)] = Σj Cov (Xm, Xj) P (Xj = X(i)) X(i) , the i-th order statistics of X = (X1 …,Xn)

Example: Az1, arrival time at path 1,Az2, arrival time at path 2…

Cov (Y, Max(Az1, Az2,…))=Cov (Az1, Y) P (Az1 is the max) +Cov (Az2, Y) P (Az2 is the max) +…

z1

2

There is no branch of mathematics, however abstract, which may not some day be applied to phenomena of the real world. --- Nikolai Lobatchevsky, N. Rose Mathematical Maxims and Minims

Page 29: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Theory of Moments• Mean/variance of the Min/Max of arrival times using

derived recursive moment functions.

Matrix.on /CorrelatiCovariance theis where,)2(||

]5.0exp[),,(with

....)()( :nDitributio Normal-k Standard the

ofMoment th - theHere,

1

1

1112

2

BB

XBXxx

dxdxxxxm

w

n

T

kBk

k

b

a

b

ak

wwR

k

k

Page 30: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Theory of Moments

• Mean/Variance formulasf Min or Max function

Page 31: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

The General SSTA Algorithm

• Block-based statistical static timing analysis– Breadth-first traversal of timing graph– Applying statistical summation and min/max

operations

s

a

b

c

d

e

f

g

tt

c

f

ea

dbg

Block-basedApproach:Breadth-firstSearch on theTiming Graph

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)(),(

)),),...,,()

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pn

j

jqrqrp

qrp

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pp

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,,ASA

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p

Cov((

by given is Expansion Local

TCov

arbitrary and between Covariance

Cov(Cov(T(

:Cov ofvector a as given is Projection Global

Expansion Local ;Projection Global T

where ,T

:tuple-4 a by given is , by denoted

, node aat Time Arrival

Page 32: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Property of Local Set

• Each node can be at most in one local set.• Merge multiple local sets when arrival times

meet at one node. • Add a multiple fan-out node to its parents’

local set, or create a new local set.• The total number of elements in all the local

sets doesn’t exceed the maximum number of nodes in one BFT level, space ~O(N/d).

• Local expansion is defined as the covariance structure of a local set.

Set Theoretic Model for Identifying Re-convergent Paths

Page 33: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Flow Chart of the SSTA algorithmInitial Local Sets & BF traversal

Update signal arrival times and covariance to node q

Compute μ and σ of SA at q usingp-normal moment functions

Compute q’s global projection

Establish q’s local set and its localexpansion using Siegel’s formula

Next Node? Yes

ENDNo

Page 34: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

g

f

e

Compute covariance between arrival times at cf, df using global projection

Record covariance of arrival times along df and dg

Record covariance of arrival times along ce and cfApply Siegel’s formulaand record covariancesbetween arrival times at node f, ce, dg

Merge c and d’s local setse, f, g, sinceULSf = c,e,d,gMFf = c, dSFf = Φ

s

a

b

c

d

Create Local Set for dd

Create Local Set for cc

Add e to c’s local setc, e

Add g to d’s local setd, g

ULSp = Ui=1..kLSip – SFp – MFp

LSp = ULSp U p if ULSp is non-empty or pis a multiple fan-out node

Example

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Experimental Results• ISCAS 85 benchmark to verify the algorithm

50% global, 50% local variations, respectively

• Average error of mean 0.2%, error of σ 2.9%

Speed up Achieved is between 6 and 4,500 for circuits up to 2,000 gates while accuracy is between 0.1% and 0.2%.

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Conclusion• Global Projection handles global variations

which cause correlations across the chip• General moments, mean/variance, covariance

formulas for k-normal distribution• Local Expansion handles correlation from local

variations due to re-convergent paths• Development of a fast Statistical Timing

Analysis Tool that utilizes Multivariate Normal Distributions

To create a good philosophy you should renounce metaphysics but be a good mathematician.

- Bertrand Russell

Page 37: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Can we Solve the Manufacturing Problem by Adopting Novel Nanotechnologies?

Self-assembled Quantum Dot structures are intrinsically more Robust because of their collective neuromorphic computation

Alternate Robust Solution?

2 n

Edge Extraction

mAI

mABmAA

pFC

1

010

141

010

000

000

000

1

IntrinsicallyRobust inPresence Of ManyFaults

Page 38: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

1. Summation of arrival time with gate delay2. Evaluate covariance of arrival times at fan-ins3. Compute the Mean/Variance of Max/Min operation

of arrival times4. Calculate the Global Projection of the results

of Min/Max into the basis using Siegel’s formula

Global Projection• Independent normal V.V.’s as a ‘basis’,

derived by Principal Component Analysis• Project timing variables onto the basis X=(X1,

X2,…, Xn): Ar = arX, Aq = aqX, Dg = dgX Ar+Dg = (ar+dg)X Cov(Ar, Aq )=Cov(arXXTag

T)

s

a

b

c

d

e

f

g

t

1. Summation of arrival time with gate delay2. Evaluate covariance of arrival times at fan-ins3. Compute the Mean/Variance of Max/Min operation

of arrival times4. Calculate the Global Projection of the results

of Min/Max into the basis using Siegel’s formula

Page 39: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

xc must be considered intoCovariance of arrival times atnode t

Correlation by Local Variations• Independent local variations can cause

path delay correlation due to re-convergent paths

s

a

b

c

d

Gate c has local variation xc

xc is independent of any other gate delays.Similarly Gates b, d, …

Covariance of arrival times at path scf and path sbdf only requires global projection

t

e

f

g

t

c

f

ea

dbg

s t

Page 40: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Properties of Local Set• Each node can be at most in one local set.• Merge multiple local sets when arrival

times meet at one node. • Add a multiple fan-out node to its parents’

local set, or create a new local set.• The total number of elements in all the

local sets doesn’t exceed the maximum number of nodes in one BFT level, space ~O(N/d).

• Local expansion is defined as the covariance structure of a local set.

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Local Expansion• Using local expansion

– Local set, LS: for each node a in its local set, there at least is another node which shares one multiple fanout node with a.

LSp = ULSp U p, if ULSp is non-empty or p is a multiple fan-out node

ULSp = Ui=1..kLSip – SFp – MFpSFp the set of nodes only fan out to p.MFp the set of multiple fan-out nodes which

has p as their last visited fan-out node.• Local expansion is defined as the

covariance structure of a local set.

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Some Theoretical Results• Lemma 1: for two nodes where no shared

paths from primary inputs, covariance of arrival times at the two nodes equals to the inner product of their two global projections

Cov (Afc, Afd )= Cov (afcXXTafdT)

a e

s

b

c

df

g

t

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Some Theoretical Results

• Lemma 3: In the breadth-first traversal of timing graph, if a re-convergent node is visited, then those of its fan-in nodes in the re-convergent paths must already be in the same local set.

a e

s

b

c

df

g

t

a e

s

b

c

df

g

t

Local set e, f, g

Page 44: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Experimental Results• Moments and mean/variance formulas are

verified using MATLAB

Page 45: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

General Framework of SSTA• Basic operations required in Statistical

Static Timing Analyzer (SSTA)– Sum and Min/Max

• Normal distribution approximations of timing

Block-basedApproach:Breadth-firstSearch on theTiming Graph

t

c

f

ea

dbg

s

a

b

c

dt

Page 46: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

t

c

f

ea

dbg

Page 47: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 1

Interconnect Modeling using Modeling using Differential Quadrature Method

Prof. P. Mazumder and Q. Xu

12/14/99 12/16/99 1

Why modeling interconnects Chip size and operating speed increasing

S t hi (SOC)System-on-a-chip (SOC)

Multi-chip module (MCM)

GHz signals

2

Interconnect effects interconnection delay dominates

crosstalk, dispersion, attenuation and reflection

Page 48: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 2

How to model interconnects

1. TEM or quasi-TEM assumptions

2 Parameter extraction of metal interconnect

3

2. Parameter extraction of metal interconnect

3. Multiport models of interconnects

4. Incorporation of multiport into simulator frame

Basis of interconnect modeling Telegrapher’s equations

Ti d iTime-domain

s-domain

4

Common goal: time-domain model ready to be incorporated into SPICE frame

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P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 3

Existing modeling methods Finite difference

l d l t lumped elements

MCspecial cases

AWE reduced order

5

ReductionKrylov subspace

DQM

Finite difference method

6

SPICE early version

Short interconnect

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P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 4

Method of Characteristics Basis: uniform interconnect terminals

Most useful for lossless interconnect

7

Asymptotic waveform evaluation Pade approximation

Recursive convolution turn convolution to time linear operation

8

Stability problem right half plane poles

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P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 5

Quadrature method Integral

9

Differential quadrature method Derivative

10

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P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 6

Determination of DQM coefficient Select test functions u(x) to fit

PDQ: Power functions

CDQ: Chebyshev polynomials

11

HDQ: Harmonic functions

DQM operator Operator

Accuracy example: derivative of f(x)=(sin x)2

average squared error

12

Page 53: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 7

Discretization of interconnect DQM operation Single line example: step 1

L’=360nH/m, C’=100pF/m

G’ 0 01S/ R’ 0Ω/ G’=0.01S/m, R’=50Ω/m

d’=0.08m

normalize parameters L=dL’, C=dC’, G=dG’, R=dR’

let 5 grid points equally space

5th order HDQ operator

13

014.6726.10584.7443.4571.1

571.1221.2363.5221.2651.0

651.0142.30142.3651.0

651.0221.2363.5221.2571.1

571.1443.4584.710.7266.014-

A

Discretized model---single line Single line

Single line example: Step 2

),(

),(

),(

),(

),(

0000

0000

0000

0000

0000

),(

),(

),(

),(

),(

5

4

3

2

1

5

4

3

2

1

sxI

sxI

sxI

sxI

sxI

RsL

RsL

RsL

RsL

RsL

sxV

sxV

sxV

sxV

sxV

A

),(0000),( 10 sxVGsCsxI

14

with equations at mid-point removed

(adding boundary conditions)

),(

),(

),(

),(

),(

0000

0000

0000

0000

0000

),(

),(

),(

),(

),(

5

4

3

2

1

5

4

3

2

0

sxV

sxV

sxV

sxV

sxV

GsC

GsC

GsC

GsC

GsC

sxI

sxI

sxI

sxI

sxI

A

Page 54: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 8

Compact model---single line Eliminate internal variables Single line example: step 3

eliminate V(x2,s), V(x3,s), V(x s) I(x s) I(x s) I(x s)

ABCD model

V(x4,s), I(x2,s), I(x3,s), I(x4,s)

A, B, C, D, y11, y12, y13, and y14 are rational approximation

15

Admittance (Y) model order of

denominator/numerator is 2*N-4 (N: DQM order)

6

16

610

6610

...

...

n n

n

ps

q

sbsbb

sasaa

Companion model---single line Take inverse Laplace transform

Apply recursive convolution Apply recursive convolution

Single line example: step 4

companion model

add boundary conditions

or incorporate into simulator frame

time-stepping

16

transient results

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P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 9

Discretized model---multi-line Multiconductor line

17

Companion model---multi-line Eliminate internal variables

T k i L l t f Take inverse Laplace transform

Apply recursive convolution

18

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P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 10

DQM application: step by step Preparation

T l h ’ tiTelegrapher’s equations

DQ coefficient matrices: PDQ, CDQ, HDQ

Select a kind of DQM

Discretization of Telegrapher’s equations

Compact s-domain models

19

Companion models

Incorporation into MNA or simulator frame

Transient simulation results

Two different incorporations Discretized model

i d l companion model

20

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P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 11

Example 1---frequency response A of ABCD matrix

E f 9th d DQM Error of 9th order DQM

Error of 15th order DQM

21

Example 2---single line Frequency response

T i t Transient response

22

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P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 12

Example 3---coupled line Transient response

23

Example 4---nonuniform line Two coupled line

T i t Transient responses

Running time on Ultra-1HSPICE 3.6s

7th-order DQM 0.95s

9th-order DQM 1.2s

24

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P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 13

Example 5---nonuniform line Three coupled line

T i t Transient response

Running time on Ultra-1HSPICE 5.527s

9th-order DQM 1.56s

25

Comparison of existing methods

26

fair

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P. Mazumder and Q. Xu 3/7/2013

Interconnect Modeling using Differential Quadrature Method 14

Conclusions Derivative of a function can be approximated by

a weighted linear sum of all the function valuesa weighted linear sum of all the function values at every mesh point. DQM a simple direct numerical technique

less sample points needs (1/10 of FD grid points)

considerable accuracy

hi h ffi i

27

high efficiency

a general formulation of such kind of methods

applicable to both uniform and nonuniform line

Page 61: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Compact Finite Difference Compact Finite Difference Quadrature Method and Its Numerical Dispersion Numerical Dispersion

Presented by: Prof Pinaki MazumderPresented by: Prof. Pinaki Mazumder

GSRA: Q. Xu

University of Michigan, EECS Dept., y g p

1301 Beal Ave

Ann Arbor, MI 48109 USA

12/14/99 3/30/2004 1/17

n1

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Slide 1

n1 UMEECSndrgrp, 5/23/2003

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Topicsp

General Finite Difference Quadrature Method General Finite Difference Quadrature Method

Compact FDQ method

Numerical dispersion analysis Numerical dispersion analysis

Resolution heuristic

2/17

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FDQ Method FormulationFDQ Method Formulation

0 Ni+2i+1ii-1... ...i+1+1/2i+1/2i-1/2

General Approximation framework for FDQ

0 Ni 2i 1ii 1... ...i 1 1/2i 1/2i 1/2

Integer grid points and half grid points

Finite difference of integer grid points1N

Finite differences of half grid points

1

0 2/11 )(')()(N

j jijijii xfwaxxfxf

Finite differences of half grid points

N

j jijijii xfwaxxfxf02/12/1 )(')()(

3/17Finite differences

Quadratures:Summations of weighted derivative

Page 65: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Matrix RepresentationMatrix Representation

General Approximation framework for FDQpp Q

1

0 2/11 )(')()(N

j jijii xfaxxfxf

2/11

2/1

22221

11211

12

01

'

'

N

N

f

f

aaa

aaa

xff

ff

2/1211 'NNNNNNN faaaff

Determine the coefficients by using testing functions

Accuracy: O(ΔxN-1)

4/17

Accuracy: O(Δx )

Page 66: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Application to Transmission LinesApplication to Transmission Lines

S-domain Telegrapher’s equationg p q

Voltage grid points: integers x i=0 NVGsCI

IRsLV

)('

)('

Voltage grid points: integers xi, i=0..N

Current grid points: halves xi+1/2, i=0..N-1

Approximation framework

N 1

N

j jkjkk

N

j jkjkk

sxIbxsxIsxI

sxVaxsxVsxV

02/12/1

1

1 2/11

),('),(),(

),('),(),(

5/17

Page 67: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Matrix RepresentationMatrix Representation

Discrete Telegrapher’s equations Discrete Telegrapher s equations

N

N

I

I

aaa

aaa

RsLV

V

2/11

2/1

22221

11211

1

0

...

...

)(11

11

NNNNNN

VbbbI

Iaaa

RsL

V

2/121

11

)(

11

......

N

N

V

V

bbb

bbb

GsCI

I

1

0

11110

00100

2/1

0

...

...

)(11

11

NNNNNN VbbbI 2111

6/17

Page 68: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Original FDQ SchemeOriginal FDQ Scheme

N

N

I

I

aaa

aaa

RsLV

V

2/11

2/1

22221

11211

1

0

...

...

)(11

11

NNNNN

N

N

N

NNNNNN

V

V

V

bbb

bbb

bbb

GsC

I

I

I

IaaaV

1

0

21

11110

00100

2/1

0

2/121

...

...

)(

11

11

11

)(

11

......

Matrices A and B are dense

NN bbaa 000111 ......

NNNNNN bb

B

aa

A

01

Problem: dense matrices, computationally expensive

7/17

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Dense Matrices: Computationally ExpensiveDense Matrices: Computationally Expensive

NN bbaa 000111 ......

NNN

N

NNN

N

bb

bb

B

aa

aa

A

0

000

1

111 ......

Suitable for small scale problems (< 3~5 wavelengths) N~10

E i f l l bl Expensive for larger scale problems N~100

8/17

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Solution: Compact FDQ SchemeSolution: Compact FDQ Scheme

Compact approximation framework for FDQp pp Q A Sliding window with length of n for central grid points

2/)1(

2/)1( 2/11 )(')()(n

nj jijii xfcxxfxf

0 Ni+2i+1ii-1... ...i+1+1/2i+1/2i-1/2

For boundary grid points use the original FDQ schemes

9/17

For boundary grid points, use the original FDQ schemes

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Improvement: Keep Large Matrices SparseImprovement: Keep Large Matrices Sparse

Use a scheme with fixed bandwidth

XXXXX

XXXX

XXX

XXXX

XXX

XXXXX

XXXXX

XXXXX

B

XXXX

XXXXX

XXXXX

A ..............................

Result in sparse diagonal matrices

XXX

XXXX

XXXXX

XXX

XXXX

10/17

Result in sparse diagonal matrices

Page 72: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

Formulation of Compact FDQ SchemesFormulation of Compact FDQ Schemes

FDQ4 (4th order accuracy)

Q ( th )

)](')(')('[

)()(

11

2/12/1

iii

ii

xafxbfxafx

xfxf

FDQ6 (6th order accuracy)

)](')(')(')(')('[

)()( 2/12/1

ii

xafxbfxcfxbfxafx

xfxf

FDQ8 (8th order accuracy)

)]()()()()([ 2112 iiiii xafxbfxcfxbfxafx

11/17

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How Accurate: Fourier Analysis for N i l Di iNumerical Dispersion

Assume a wave )(),( kxtjetxf

FD2

Plug in and simplify, compare the wave-numbers

)(')()( 2/12/1 iii xxfxfxf

LHS is numerical dispersion caused by discretization

kx

xk

2/

)2/sin(

LHS is numerical dispersion caused by discretization

Normalized wavenumber of FD2: )2/sin( xk

12/17

2/

)(

xk

Page 74: Fast Algorithms for Thermal Analysis of 3-D VLSI Chipsweb.eecs.umich.edu/~mazum/CMOS EDA.pdfFast Algorithms for Thermal Analysis of 3-D VLSI Chips Prof. Pinaki Mazumder ... reality

On Numerical Dispersion: FDQ4 etcOn Numerical Dispersion: FDQ4, etc

FDQ4

Plug in wave

)(')(')(')()( 112/12/1 iiiii xafxbfxafxfxf)(),( kxtjetxf

Normalized wave number of FDQ4:

))cos(2(2/

)2/sin(bxkak

x

xk

Normalized wave-number of FDQ4:

))cos(2(2/

)2/sin(

bxkaxk

xk

13/17

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Comparison of Numerical DispersionComparison of Numerical Dispersion

Idea normalized wave number = 1

Number of cells per wavelength needed given phase Number of cells per wavelength needed given phase accuracy

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Numerical Results: 1Numerical Results: 1

L=360nH/m, C=100pf/mR 1 kOh /R=1 kOhm/mfmax=14 GHzλmin=1.2 cmλmin 1.2 cm

Phase error: 1% Numbers of cells:

FD2: 64 FDQ4: 23 FDQ6: 17

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Numerical Results: 2Numerical Results: 2

Phase error: 0.1%

Numbers of cells FD2: 204

FDQ4: 41

FDQ6: 27

Heuristics for resolution: 1% phase error is OK

0.1% is good

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SummarySummary

Modified FDQ method to reduce the matrix density and Q ytherefore computational expense

Accuracy comparison by using Fourier analysis

Heuristic for Number of cells per wavelength neededSuggested resolutions at 1% of phase error, CPW:

FD2: 12 8 FD2: 12.8

FDQ4: 4.6

FDQ6: 3.5

FDQ8: 3.1

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