farhan mohamed ali (w2-1) jigar vora (w2-2) sonali kapoor (w2-3) avni jhunjhunwala (w2-4)

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1 Farhan Mohamed Ali (W2- 1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 11 MAD MAC 525 19 th April, 2006 Top-Level LVS W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

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Presentation 11 MAD MAC 525. Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4). W2. Design Manager: Zack Menegakis. 19 th April, 2006 Top-Level LVS. Project Objective: - PowerPoint PPT Presentation

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Page 1: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Farhan Mohamed Ali (W2-1)Jigar Vora (W2-2)Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4)

Presentation 11

MAD MAC 525

19th April, 2006Top-Level LVS

W2

Project Objective:Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics.

Design Manager: Zack Menegakis

Page 2: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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MAD MAC 525 Status: Project chosen Specifications defined Architecture

Design Behavioral Verilog Testbenches Verilog : Gate Level Design Floor plan Schematics and Analog Verifications Layout of basic gates and small modules Top level layouts, Extractions, LVS, Simulations Full Chip Layout completed and LVSed

To be done Simulations and full chip verification

Page 3: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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RegArray A RegArray B RegArray C

Multiplier Exp Calc Align

Adder/SubtractorControlLogic

&Sign

Dtrmin

Normalize

Round

Ovf Checker

Leading 0 Anticipator

10 10 10

5

55

1435225

4

36

14

101

5

5

Input Input Input

Output

16 16 16

16RegY

15

1

1

1

Block Diagram

Page 4: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Multiplier Layout with pipelining

Page 5: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Simulations Compared

Page 6: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Full Chip Layout

Exponent

AlignZero

Adder

MultiplierNormalize

Round

Ovf

Page 7: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Design Specifications

• Register-to-register delay (worst case)= 2.25ns• Long buses are all buffered (not tested yet)• Estimated clocking speed = 400MHz• Height by width = 193.86 um * 301.545 um• Area = 58,458 um^2• Aspect ratio = 1:1.55• Total Transistor density = 0.22

Page 8: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Layer Masks - Poly

Page 9: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Layer Masks – Metal 1

Page 10: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Layer Masks – Metal 2

Page 11: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Layer Masks – Metal 3

Page 12: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Layer Masks – Metal 4

Page 13: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Schematic Power: mW (350Mhz)

Layout Power: mW

Schematic Delay

Layout Delay

Multiplier -w/ pipeline

2.97??

N/A??

3.38n1.9n

N/A2.25n

Exponents 1.608 2.21 1.01n 1.2n

Align 0.094 0.113 480p 637p

Adder 8.48 9.73 1.34n 1.7n

Leading 0 0.232 0.857 506p 551p

Normalize 1.458 1.546 407p 437p

Round 0.631 1.21 864p 986p

OvfCheck 0.13 0.19 453p 475p

Registers ?? ?? 179p 193p

Total ?? ?? - -

Page 14: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Area:um2

Transistor Count

TransistorDensity

Multiplier-w/ pipeline

20388 4496 0.22

Exponents 5,163 738 0.14

Align 3,995 500 0.13

Adder 13,202 3174 0.24

Leading 0 1,253 364 0.29

Normalize 3,190 942 0.3

Round 1,802 494 0.28

OvfCheck 200 70 0.35

Registers, etc N/A 1948 N/A

Total 58,458 12,730 0.22

Page 15: Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3)  Avni Jhunjhunwala (W2-4)

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Questions??