fan7888 3 half-bridge gate-drive ic - farnell element14 · 2012-03-27 · 13 lo2 low-side gate...

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC

FAN7888 • Rev. 1.0.0

May 2008

FAN78883 Half-Bridge Gate-Drive ICFeatures

Floating Channel for Bootstrap Operation to +200V Typically 350mA/650mA Sourcing/Sinking Current Driving Capability for All Channels3 Half-Bridge Gate DriverExtended Allowable Negative VS Swing to -9.8V for Signal Propagation at VBS=15VMatched Propagation Delay Time Maximum 50ns3.3V and 5V Input Logic CompatibleBuilt-in Shoot-Through Prevention Circuit for All Channels with Typically 270ns Dead TimeBuilt-in Common Mode dv/dt Noise Canceling CircuitBuilt-in UVLO Functions for All Channels

Applications3-Phase Motor Inverter Driver

DescriptionThe FAN7888 is a monolithic three half-bridge gate-driveIC designed for high-voltage, high-speed driving MOS-FETs and IGBTs operating up to +200V.

Fairchild’s high-voltage process and common-modenoise canceling technique provide stable operation ofhigh-side drivers under high-dv/dt noise circumstances.

An advanced level-shift circuit allows high-side gatedriver operation up to VS = -9.8V (typical) for VBS =15V.

The UVLO circuits prevent malfunction when VDD andVBS are lower than the specified threshold voltage.

Output drivers typically source/sink 350mA/650mA,respectively, which is suitable for three-phase half-bridgeapplications in motor drive systems.

Ordering Information

All packages are lead free per JEDEC: J-STD-020B standard.

20-SOIC

Part Number Package Operating Temperature Range Packing MethodFAN7888M

20-SOIC -40°C to +125°CTube

FAN7888MX Tape & Reel

LHouse

Chinese

http://www.fairchildsemi.com/ms/FA/FAN7888SC.pdf

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7888 • Rev.1.0.0 2

FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC

Typical Application Circuit

Figure 1. 3-Phase BLDC Motor Drive Application

Internal Block Diagram

Figure 2. Functional Block Diagram

U

VW

UU

UL

VU

VL

WU

WL

Up to 200V

+15V

Q4 Q6 Q2

Q1 Q3 Q5

Q1Q3Q5

Q4Q6Q2

3-Phase Inverter

GND

LO3

LIN1

VDD

VS1

HO1

VB1HIN1

VS2

HO2

VB2

VS3

HO3

VB3

HIN2

HIN3

LIN2

LIN3

LO2

LO1

20

19

18

17

16

15

14

13

12

1

2

3

4

5

6

7

8

9

10

VS1

VS3

VS2 VS2

VS3

VS1

FAN

7888

3-Phase BLDC MotorController

IU

IV

IW

11

FAN7888 Rev.00

UVLO

RRS

Q

DELAY

DR

IVERD

RIVER

W Phase Driver

V Phase Driver

U Phase Driver

LO2

VS2

HO2

VB2

LO3

VS3

HO3

VB3

UHIN

ULIN

VDD

VHIN

VDD

WLIN

VDD_UVLO

HIN1

HIN2

HIN3

LIN1

LIN2

LIN3VLIN

WHIN

SCHMITT TRIGGER INPUT

SHOOT-THOUGHPREVENTION

CONTROL LOGIC

UVLO

VDD

VDD

LO1

GND

VS1

HO1

VB1

NOISECANCELLER

PULSE

GEN

ERA

TOR

FAN7888 Rev.01


FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC

Pin Configuration

Figure 3. Pin Configuration (Top View)

Pin Definitions Pin # Name Description

1 HIN1 Logic input 1 for high-side gate 1 driver

2 LIN1 Logic input 1 for low-side gate 1 driver





7 LO3 Low-side gate driver 3 output

8 VS3 High-side driver 3 floating supply offset voltage

9 HO3 High-side driver 3 gate driver output

10 VB3 High-side driver 3 floating supply voltage

11 GND Ground

12 VDD Logic and all low-side gate drivers power supply voltage









GND

LO3

FAN

7888

LIN1

VDD

VS1

HO1

VB1HIN1

HIN2

HIN3

LIN2

LIN3

LO2

LO1

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

VS2

HO2

VB2

VS3

HO3

VB3

FAN7888 Rev.00


FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC

Absolute Maximum RatingsStresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. Theabsolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.

Notes: 1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.3. Do not exceed PD under any circumstances.

Recommended Operating ConditionsThe Recommended Operating Conditions table defines the conditions for actual device operation. Recommendedoperating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does notrecommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. UnitVB High-side Floating Supply Voltage of VB1,2,3 -0.3 225.0 V

VS High-side Floating Supply Offset Voltage of VS1,2,3 VB1,2,3-25 VB1,2,3+0.3 V

VHO1,2,3 High-side Floating Output Voltage VS1,2,3-0.3 VB1,2,3+0.3 V

VDD Low-side and Logic-fixed Supply Voltage -0.3 25.0 V

VLO1,2,3 Low-side Output Voltage -0.3 VDD+0.3 V

VIN Logic Input Voltage (HIN1,2,3 and LIN1,2,3) -0.3 VDD+0.3 V

dVS/dt Allowable Offset Voltage Slew Rate 50 V/ns

PD Power Dissipation(1)(2)(3) 1.8 W

θJA Thermal Resistance, Junction-to-ambient 80 °C/W

TJ Junction Temperature +150 °C

TS Storage Temperature -55 +150 °C

Symbol Parameter Min. Max. UnitVB1,2,3 High-side Floating Supply Voltage VS1,2,3+10 VS1,2,3+20 V

VS1,2,3 High-side Floating Supply Offset Voltage 6-VDD 200 V

VDD Supply Voltage 10 20 V

VHO1,2,3 High-side Output Voltage VS1,2,3 VB1,2,3 V

VLO1,2,3 Low-side Output Voltage GND VDD V

VIN Logic Input Voltage (HIN1,2,3 and LIN1,2,3) GND VDD V

TA Ambient Temperature -40 +125 °C


FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC

Electrical CharacteristicsVBIAS (VDD, VBS1,2,3) = 15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced toGND. The VO and IO parameters are referenced to GND and VS1,2,3 and are applicable to the respective outputsLO1,2,3 and HO1,2,3.

Note:

4. This parameter is guaranteed by design.

Symbol Characteristics Condition Min. Typ. Max. UnitLOW SIDE POWER SUPPLY SECTION

IQDD Quiescent VDD Supply Current VLIN1,2,3=0V or 5V 160 350 µA

IPDD1,2,3Operating VDD Supply Current for each Channel fLIN1,2,3=20kHz, rms Value 500 900 µA

VDDUV+VDD Supply Under-Voltage Positive-going Threshold VDD=Sweep, VBS=15V 7.2 8.2 9.0 V

VDDUV-VDD Supply Under-Voltage Negative-going Threshold VDD=Sweep, VBS=15V 6.8 7.8 8.5 V

VDDHYSVDD Supply Under-Voltage Lockout Hysteresis VDD=Sweep, VBS=15V 0.4 V

BOOTSTRAPPED POWER SUPPLY SECTION

IQBS1,2,3Quiescent VBS Supply Current for each Channel VHIN1,2,3=0V or 5V 50 120 µA

IPBS1,2,3Operating VBS Supply Current for each Channel fHIN1,2,3=20kHz, rms Value 400 800 µA

VBSUV+VBS Supply Under-Voltage Positive-going Threshold VDD=15V, VBS=Sweep 7.2 8.2 9.0 V

VBSUV-VBS Supply Under-Voltage Negative-going Threshold VDD=15V, VBS=Sweep 6.8 7.8 8.5 V

VBSHYSVBS Supply Under-Voltage Lockout Hysteresis VDD=15V, VBS=Sweep 0.4 V

ILK Offset Supply Leakage Current VB1,2,3=VS1.2.3=200V 10 µA

GATE DRIVER OUTPUT SECTIONVOH High-level Output Voltage, VBIAS-VO IO=20mA 1.0 V

VOL Low-level Output Voltage, VO IO=20mA 0.6 V

IO+ Output HIGH Short-circuit Pulsed Current(4) VO=0V, VIN=5V with PW<10µs 250 350 mA

IO- Output LOW Short-circuit Pulsed Current(4) VO=15V, VIN=0V with PW<10µs 500 650 mA

VSAllowable Negative VS Pin Voltage for IN Signal Propagation to HO

-9.8 -7.0 V

LOGIC INPUT SECTION (HIN, LIN)VIH Logic "1" Input Voltage 2.5 V

VIL Logic "0" Input Voltage 1.0 V

IIN+ Logic "1" Input Bias Current VIN=5V 25 50 µA

IIN- Logic "0" Input Bias Current(4) VIN=0V 2.0 µA

RIN Input Pull-down Resistance 100 200 300 KΩ


FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC

Dynamic Electrical CharacteristicsTA=25°C, VBIAS (VDD, VBS1,2,3) = 15.0V, VS1,2,3 = GND, CLoad = 1000pF unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. UnittON Turn-on Propagation Delay VS1,2,3=0V 130 220 ns

tOFF Turn-off Propagation Delay VS1,2,3=0V 150 240 ns

tR Turn-on Rise Time 50 120 ns

tF Turn-off Fall Time 30 80 ns

MT1 Turn-on Delay Matching I tON(H) -tOFF(L) I 50 ns

MT2 Turn-off Delay Matching I tOFF(H) -tON(L) I 50 ns

DT Dead Time 100 270 440 ns

MDT Dead-time Matching I tDT1 -tDT2 I 60 ns


FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC

Typical Characteristics

Figure 4. Turn-on Propagation Delay vs. Temp. Figure 5. Turn-off Propagation Delay vs. Temp.

Figure 6. Turn-on Rise Time vs. Temp. Figure 7. Turn-off Fall Time vs. Temp.

Figure 8. Turn-on Delay Matching vs. Temp. Figure 9. Turn-off Delay Matching vs. Temp.

-40 -20 0 20 40 60 80 100 1200

50

100

150

200

250

t ON [n

s]

Temperature [°C]-40 -20 0 20 40 60 80 100 1200

50

100

150

200

250

300

t OFF

[ns]

Temperature [°C]

-40 -20 0 20 40 60 80 100 1200

20

40

60

80

100

120

t R [n

s]

Temperature [°C]-40 -20 0 20 40 60 80 100 1200

20

40

60

80

100

t F [n

s]

Temperature [°C]

-40 -20 0 20 40 60 80 100 1200

10

20

30

40

50

MT1

[ns]

Temperature [°C]-40 -20 0 20 40 60 80 100 1200

10

20

30

40

50

MT2

[ns]

Temperature [°C]

FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7888 • Rev. 1.0.0 8

Typical Characteristics (Continued)

Figure 10. Dead Time vs. Temp. Figure 11. Dead-Time Matching vs. Temp.

Figure 12. Quiescent VDD Supply Current vs. Temp.

Figure 13. Quiescent VBS Supply Current vs. Temp.

Figure 14. Operating VDD Supply Current vs. Temp. Figure 15. Operating VBS Supply Current vs. Temp.

-40 -20 0 20 40 60 80 100 120100

200

300

400

500

DT

[ns]

Temperature [°C]-40 -20 0 20 40 60 80 100 1200

10

20

30

40

50

60

MD

T [n

s]

Temperature [°C]

-40 -20 0 20 40 60 80 100 1200

50

100

150

200

250

300

350

I QD

D [μA]

Temperature [°C]-40 -20 0 20 40 60 80 100 1200

20

40

60

80

100

120

I Q

BS [μA]

Temperature [°C]

-40 -20 0 20 40 60 80 100 1200

200

400

600

800

1000

I PDD [μA]

Temperature [°C]-40 -20 0 20 40 60 80 100 1200

200

400

600

800

1000

I PBS [

μA]

Temperature [°C]

FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC



Figure 16. VDD UVLO+ vs. Temp. Figure 17. VDD UVLO- vs. Temp.

Figure 18. VBS UVLO+ vs. Temp. Figure 19. VBS UVLO- vs. Temp.

Figure 20. High-Level Output Voltage vs. Temp. Figure 21. Low-Level Output Voltage vs. Temp.

-40 -20 0 20 40 60 80 100 1207.0

7.5

8.0

8.5

9.0

V DD

UV

+ [V]

Temperature [°C]-40 -20 0 20 40 60 80 100 120

7.0

7.5

8.0

8.5

9.0

V DD

UV

- [V]

Temperature [°C]

-40 -20 0 20 40 60 80 100 1207.0

7.5

8.0

8.5

9.0

V BS

UV

+ [V]

Temperature [°C]-40 -20 0 20 40 60 80 100 120

7.0

7.5

8.0

8.5

9.0

V

BSU

V- [V

]

Temperature [°C]

-40 -20 0 20 40 60 80 100 1200.0

0.2

0.4

0.6

0.8

1.0

VO

H [V

]

Temperature [°C]-40 -20 0 20 40 60 80 100 120

0.00

0.15

0.30

0.45

0.60

V OL [V

]

Temperature [°C]

FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC



Figure 22. Logic High Input Voltage vs. Temp. Figure 23. Logic Low Input Voltage vs. Temp.

Figure 24. Logic Input High Bias Current vs. Temp. Figure 25. Allowable Negative VS Voltage vs. Temp.

Figure 26. Input Pull-down Resistance vs. Temp.

-40 -20 0 20 40 60 80 100 1200.0

0.5

1.0

1.5

2.0

2.5

3.0

V IH [V

]

Temperature [°C]-40 -20 0 20 40 60 80 100 120

0.0

0.5

1.0

1.5

2.0

2.5

3.0

VIL [V

]

Temperature [°C]

-40 -20 0 20 40 60 80 100 1200

10

20

30

40

50

I IN+ [

μA]

Temperature [°C]-40 -20 0 20 40 60 80 100 120

-12

-11

-10

-9

-8

-7

V S

[V]

Temperature [°C]

-40 -20 0 20 40 60 80 100 1200

100

200

300

400

500

RIN

[kΩ]

Temperature [°C]


FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC

Application Information

1. Protection Function

1.1 Under-Voltage Lockout (UVLO)

The high- and low-side drivers include under-voltagelockout (UVLO) protection circuitry for each channel thatmonitors the supply voltage (VDD) and bootstrap capaci-tor voltage (VBS1,2,3) independently. It can be designedprevent malfunction when VDD and VBS1,2,3 are lowerthan the specified threshold voltage. The UVLO hystere-sis prevent chattering during power supply transitions.

1.2 Shoot-Through Prevention FunctionThe FAN7888 has shoot-through prevention circuitrymonitoring the high- and low-side control inputs. It canbe designed to prevent outputs of high and low side fromturning on at same time, as shown Figure 27 and 28.

Figure 27. Waveforms for Shoot-Through Prevention

Figure 28. Waveforms for Shoot-Through Prevention

2. Operational NotesThe FAN7888 is a three half-bridge gate driver withinternal typically 120ns dead-time for the three-phaseBrushless DC (BLDC) motor drive system, as shown inFigure 1.

Figure 29 shows a switching sequence of 120° electricalcommutation for a three-phase BLDC motor drive system.

The waveforms are idealized: they assumed that thegenerated back EMF waveforms are trapezoidal with flattops of sufficient width to produce constant torque whenthe line currents are perfectly rectangular 120° electricaldegrees with the switching sequence as shown in Figure29. The operating waveforms of the wey-connectionreveal that repeat every 60 electrical degrees, with each60° segment being “commutated” to another phase, asshown in Figure 29.

After DT

HIN1,2,3/LIN1,2,3

LO1,2,3/HO1,2,3

HO1,2,3/LO1,2,3

After DT

Shoot-Through Prevent

LIN1,2,3/HIN1,2,3

FAN7888 Rev.00

After DT

Shoot-Through Prevent

HIN1,2,3/LIN1,2,3

LO1,2,3/HO1,2,3

HO1,2,3/LO1,2,3

LIN1,2,3/HIN1,2,3

FAN7888 Rev.00

FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC


Application Information (Continued)

Figure 29. 120° Commutation Operation Waveforms for 3-Phase BLDC Motor Application

Switching Time Definitions

Figure 30. Switching Time Definition

Q1 (HIN1) Q3 (HIN2)Q2 (LIN3)Q6 (LIN2)

Q5 (HIN3)Q5 (HIN3)Q4 (LIN1)

-30 0 30 60 90 120 150 180 210 240 270 300 330 Elec o

HIN / HO1,2,3

LIN / LO1,2,3

Input / Output

IU

IV

IW

Phase Current

VS1

VS2

VS3

Phase Voltage

Current Flow Direction U V W U V W U V W U V W U V W U V W

Phase Back EMF

50% 50%

tON(H) tR tOFF(H) tF

HIN1,2,3/LIN1,2,3

HO1,2,3

10%

90%

10%

90%

10%

90%

10%

90%

tON(L) tOFF(L)

MT1 MT2

LO1,2,3


FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC

Mechanical Dimensions.

Figure 31. 20-Lead Small Outline Package (SOIC)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any mannerwithout notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify orobtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:http://www.fairchildsemi.com/packaging/

pdip8_dim.pdf

0.10 C

C

A

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, VARIATION AC, ISSUE E

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

E) LANDPATTERN STANDARD: SOIC127P1030X265-20L

PIN ONE

INDICATOR

0.25

1 10

BC AM

20 11

B

X 45°

8°0°

SEATING PLANE

GAGE PLANE

DETAIL ASCALE: 2:1

SEATING PLANE

LAND PATTERN RECOMMENDATION

F) DRAWING FILENAME: MKT-M20BREV3

0.651.27

2.25

9.50

13.0012.60

11.43

7.607.40

10.6510.00

0.510.35

1.27

2.65 MAX

0.300.10

0.330.20

0.750.25

(R0.10)

(R0.10)

1.270.40

(1.40)

0.25

D) CONFORMS TO ASME Y14.5M-1994

MKT-M20BREV3

FAN

7888 — 3 H

alf-Bridge G

ate-Drive IC


fan7888 3 half-bridge gate-drive ic - farnell element14 · 2012-03-27 · 13 lo2 low-side gate...

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