famaf - leccion clase vhdl 10
TRANSCRIPT
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CURSO VHDL LECCIÓN 10
• Lección 10: PACKAGES AND COMPONENTS– 10_1 – PACKAGES AND COMPONENTS – 10_2 – ESTILO DE DISEÑO #1– 10_3 – ESTILO DE DISEÑO #2 – 10_4 – ESTILO DE CODIFICACIÓN
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10_1 PACKAGES y COMPONENTS 1/1
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10_2 PACKAGE 1/5
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10_2 PACKAGE 2/5• Ejemplo 10.1Simple Package
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10_2 PACKAGE 3/5• Ejemplo 10.2 Package Con Funcion
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10_2 PACKAGE 4/5• Ejemplo 10.2 Package Con Funcion
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10_2 PACKAGE 5/5• Ejemplo 10.2 Package Con Funcion
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10_3 COMPONENT 1/16• Declaración de COMPONENT
• Instanciación de COMPONENT
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10_3 COMPONENT 2/16
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10_3 COMPONENT 3/16
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10_3 COMPONENT 4/16
• Ejemplo 10.3 Componentes declarados en el código principal (main code)
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10_3 COMPONENT 5/16
• Ejemplo 10.3 Componentes declarados en el código principal (main code)
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10_3 COMPONENT 6/16
• Ejemplo 10.3 Componentes declarados en el código principal (main code)
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10_3 COMPONENT 7/16
• Ejemplo 10.3 Componentes declarados en el código principal (main code)
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10_3 COMPONENT 8/16
• Ejemplo 10.3 Componentes declarados en el código principal (main code)
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10_3 COMPONENT 9/16
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10_3 COMPONENT 10/16
• Ejemplo 10.4 Componentes declarados en un PACKAGE
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10_3 COMPONENT 11/16
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10_3 COMPONENT 12/16
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10_3 COMPONENT 13/16
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10_3 COMPONENT 14/16
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10_3 COMPONENT 15/16
• ----------------------------------------------------------------- --1• LIBRARY IEEE; --2• USE IEEE.STD_LOGIC_1164.ALL; --3• USE WORK.my_components.ALL; --4• ------------------------------------------------------------------------• ENTITY project IS --5• PORT(a,b,c,d: IN STD_LOGIC; --6• x,y: OUT STD_LOGIC); --7• END project; --8
• ------------------------------------------------------------------ --9
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10_3 COMPONENT 16/16
• ARCHITECTURE estructura OF project IS• SIGNAL w: STD_LOGIC;• BEGIN• U1: inverter PORT MAP (b,w);• U2: nand_2 PORT MAP (a,b,x);• U3: nand_3 PORT MAP (w,c,d,y);• END estructura;