fabrication of a chmosfet with a combination of p-carbon ...fabrication of a chmosfet with a...

Fabrication of a CHMOSFET with a

Combination of P-Carbon Nanotube and an

Enhanced NMOS

Uzoma I. Oduah University Of Lagos/Physics Department, Lagos, Nigeria

Email: [email protected], [email protected]

Abstract—This study focuses on the fabrication of a

Complementary Heterostructure Metal Oxide

Semiconductor Field Effect Transistor (CHMOSFET) by

combining a P-carbon nanotube with NMOS on a single

chip to achieve miniaturized size below 0.1 micron and

improved functionalities. The technology of conventional

MOSFET and Nanotechnology is applied in this research.

Consequently, the P-carbon nanotube acts as a PMOS while

the conventional NMOS with a heavily doped polysilicon

gate and a thick oxide is embedded on the same chip.

Although it is possible to fabricate both a P and N carbon

nanotube to form a complementary pair, and also a PMOS

and NMOS to form a complementary pair, however this

research chooses to form a heterostructure with improved

functionalities. The enhanced features include a reduction in

risk of sensitivity to input voltage fluctuations. It creates a

better system of managing the valley current towards

demarcating the On and Off modes of the device. It limits

cryogenic operations. Also it enhances a better control of the

effect of extreme sensitivity of tunneling current width of

potential barriers.

Index Terms—carbon nanotube, nanotechnology,

heterostructure, MOSFET

I. INTRODUCTION

In this research the efficiency and size of the

complementary metal oxide semiconductor field effect

transistor has been improved. The advantages of applying

the P-Carbon Nanotube are merged with the conventional

NMOSFET to form a heterostructure targeted at

eliminating the effect of degradation associated with N-

Carbon nanotube. Carbon nanotubes offer unique

electronic structure as it can be rolled up to form a hollow

cylinder with the circumference expressed in order of its

chiral vector [1]-[3]. Its crystallographic equivalent of

two dimensional grapheme tubes can be expressed as

follows:

Ĉh = nâ1 + mâ2 (1)

where n and m are integers, and â1 and â2 are the unit

vectors of the hexagonal lattice as shown in Fig. 1a and

Fig. 1b.

Manuscript received November 12, 2013; revised February 8, 2014

Figure 1a. Hexagonal lattice of a carbon nanotube

Figure. 1b. Hexagonal atomic structure of grapheme showing the chiral vector Ĉh

The properties of the carbon nanotube are determined

by the chiral angle and its corresponding diameter of the

circumference [4]-[6]. So, the nanotube diameter dt and

the chiral angle can be expressed given the integers (n,

m) as follows:

(2)

where the chiral angle is expressed as:

(3)

A carbon nanotube described by (n, m) can be

classified as: Zig-zag if either n = 0 or m = 0

Armchair if n = m

Chiral if n m

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International Journal of Materials Science and Engineering Vol. 2, No. 2 December 2014

©2014 Engineering and Technology Publishingdoi: 10.12720/ijmse.2.2.126-130

Since the Carbon Nanotube Field Effect Transistor

(CNTFET) utilizes a single carbon nanotube or an array

of carbon nanotubes as the channel material instead of the

inversion layer created by silicon in the conventional

CMOS, the drain current can be determined from Fermi-

Dirac probabilities distributions as follows:

(4)

(5)

where NS = Source charges from density of positive

velocity states.

ND = Drain charges from density of negative

velocity states.

D(E) = Density of states at the channel.

While USF and UDF are terms expressed by:

(6)

USF = EF – qVSC

UDF = EF – qVSC – qVDS

where VSC is the self consistent voltage and VDS is the

drain source voltage.

The drain current IDS is described by the following:

(7)

where k = Boltzmann’s constant

ħ = Planck’s constant

T = Temperature

F0 = Fermi-Dirac integral of order 0

It has been observed that the n-CNTFET suffers

degradation when exposed to oxygen [7]-[12]. Although

attempts has been made in the fabrication to prolong the

lifetime by using different polymers and by covering the

top gate, it still presents a challenge concerning its

reliability. The multi-channeled CNFETs last longer as

the multiple channels can function even when some

channels break down.

Part of the major considerations in the fabrication of a

complementary MOSFET is that the n-channel and the p-

channel devices must be electrically equivalent.

Consequently, the magnitude of the threshold voltages

must be equal and the n-channel and p-channel

conduction parameters must be equal. However, since the

electron mobility µn and holes mobility µp are not equal,

the design of complementary heterostructure requires

precision engineering of the device to achieve a match

between the NMOS and the P-CNTFET.

In an NMOSFET, the ideal current - voltage

characteristics at the non-saturation region is described by

the equation:

iD = kn [2(VGS – VTh) VDS – V2DS] (8)

where iD is the drain current

VGS is the gate source voltage

VTh is the threshold voltage

VDS is the drain source voltage

Kn is the conduction parameter for n channel

(9)

where W is the n channel width, and Cox is the oxide

capacitance per unit area as described in Fig. 6.

For the saturation region of NMOS, the ideal drain

current is given by:

iD = kn(VGS – VTh)2 (10)

So, the magnitude of the current in the NMOS is a

function of the amount of charge in the inversion layer,

which in turn is a function of the applied gate voltage

[13]-[15]. The threshold voltage is the applied voltage

needed to create an inversion layer in order to turn on the

transistor on enhance mode.

II. MATERIAL STRUCTURE AND LAYOUT DESIGN

Nanotechnology: The techniques for the fabrication of

Carbon Nanotubes have evolved over the years. It started

with the Back-gated technique with a lot of defects. This

method involves the pre-patterning parallel strips of metal

across a silicon dioxide substrate, and then randomly

depositing the CNTs on the surface. The result is that one

metal is the source terminal and the other is the drain

terminal while the silicon oxide substrate serves as the

gate oxide. The limitations of this technique include very

poor metal contact area for the terminals leading to

formation of Schottkey Barrier at the metal

semiconductor interface. Again, the thickness of the

device does not allow the switching of the system using

low voltages [16]-[21]. Following these defects in the

Back gated technique the Top gated method was

introduced. This involves the deposition of single walled

carbon nanotubes solutions onto silicon oxide substrate.

Individual nanotubes are now isolated using Scanning

Electron Microscope. By annealing with high temperature,

a thin top-gate dielectric is deposited on top of the

nanotube by atomic layer deposition. The top contact is

then deposited on the gate dielectric achieving better area

contacts and minimizing contact resistance. The thin gate

dielectric also enables a larger electric field to be

generated in the nanotube with very low gate voltage. In

order to further increase the metal contact area the Wrap-

around gate CNFETs technique was developed in which

the entire circumference of the nanotube is gated [22]-

[25].

This technique involves the wrapping of the whole

CNTs in a gate dielectric and gate terminal through the

process of atomic layer deposition. This method was

deployed in the fabrication of the n-CNTFET. It offers

many advantages such as reduced leakage current,

improved device on/off ratio, and a better electrical

performance of the device [26]-[33].

III. FABRICATION AND TRANSPORT MECHANISM

The conventional silicon MOS technology is combined

with semiconducting carbon nanotube to create a

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©2014 Engineering and Technology Publishing

heterostructure with improved functionalities. The p-

carbon nanotube introduces a unique electronic structure

that reduces carrier scattering caused by one-dimensional

quantum confinement effect [34]-[37]. Recent studies

have shown that both carbon nanotubes and GE/Si core

shell nanowires demonstrated long carrier mean free

paths at room temperature. Carbon nanotubes offer near

ballistic channel transport and easy application of high -k

gate insulator. The scaling of planar silicon MOSFETs

has reached its limit and can only be taken further by

substituting the p type with a p carbon nanotube. In this

fabrication, the following parameters were used: A

silicon doping of NA = 1019

cm-3

, insulator thickness tins =

1nm and a dielectric constant of Kins = 4. The gate work

functions were selected to produce the same threshold

voltage VT for the P-CNTFET and NMOS. A 0.4V power

supply was used as required for high density systems.

Figure 2. Horizontal integration of NMOSFET with P-CNTFET

Figure 3. N-Channel enhancement mode MOSFET

Figure 4. P-CNTFET in Gate all-around contact

Single crystal silicon Si substrates with resistivity of

0.005-0.01Ωcm, were cleaned and coated with 120nm of

thermal SiO2. Single wall nanotubes produced by

produced by Laser ablation were dispersed from a 1, 2 -

dichloroethane solution by spinning onto the substrates

after mild sonication. Then the density of the solution

was adjusted to yield approximately one CNT in an area

of 5×5µm2. Ti source and drain electrodes were patterned

by electron-beam lithography and lift off. The separation

between the source and drain was 200-300nm apart.

Through horizontal monolithical integration, the NMOS

and P-carbon nanotube were place side-by-side on a semi

insulating substrate. Interconnections are made by

conductors over the epitaxial layers as shown in Fig. 2-

Fig. 4. This hybrid technology produced a

transconductance of 13000µS/µm.

Figure 5. CHMOSFET inverter load characteristics

Figure 6. CHMOSFET inverter voltage transfer characteristics

IV. RESULTS

The performance of the fabricated CHMOSFET

improved compared to the conventional CMOS or

CNTFET. The p-CNTFET produces 1850A/m of the on-

current per unit width at a gate override of 0.4V. This is

attributed to the high gate capacitance and improved

channel transport introduced by the P-CNTFET. The

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transconductance which is the ratio of the output drain

current to the input gate voltage also increased by 300%.

The CHMOSFET Inverter Load Characteristics is as

shown in Fig. 5 and Fig. 6.

V. CONCLUSION

The CHMOSFET hybrid technology of Carbon

nanotube and Silicon MOSFET is very promising in the

future of Nano-electronics. It presents a better control

over channel formation, a better threshold voltage,

desirable sub-threshold slope, impressive high carrier

mobility, high current density, and excellent high

transconductance. Furthermore, this hybrid technology is

a welcome development towards creating opportunity for

the mass production of this device at a reduced cost. It

also appears to be the most miniaturized form of silicon

CMOS.

ACKNOWLEDGEMENT

My gratitude goes to Prof. E. I. E. Ofodile, Dean of

Faculty of Engineering and Technology, NnamdiAzikiwe

University Awka, Nigeria, and the Materials and

Photonics Research Centre of Physics Department,

University of Lagos, Nigeria.

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Uzoma I. Oduah was born in Ogwashi-Uku,

Nigeria, in October 31, 1971. He holds both a Doctorate Degree (Ph.D.) in

Physics Electronics (2009) and a Master of

Technology Degree (M.Tech.) in Physics Electronics (2000) from Nnamdi Azikiwe

University, Awka, Anambra State, Nigeria. Furthermore, he specializes in Nanotechnology,

Semiconductor Bandgap Engineering,

Photonics and Advanced Micro-electronics. He is a lecturer in Physics Department of

University of Lagos, Faculty of Sciences, Akoka Campus, Lagos,

Nigeria where he is involved in teaching some of the departmental courses in Optoelectronics, Advanced Digital Electronics, Photonics,

and Laboratory Practical Demonstrations. He has over 10years research

experience garnered from various world class institutions. His previous work experience includes a Business Development Manager, in

Telecommunication Group of Spring Bank Plc, 143 Ahmadu Bello-way, Victoria Island, Lagos, Nigeria in 2010 where he rendered Professional

Advisory Services to telecommunication multinational companies. His

current research work is on carrier mobility enhancement in semiconductor Complementary Heterostructure Metal oxide

Semiconductor Field Effect Transistors (CHMOSFET). Dr. Oduah is a Fellow of Materials and Photonics Research Centre

(MAPHORC) University of Lagos, Nigeria. He is a Senior Member of

International Association of Computer Science and Information Technology (IACSIT), a Member of Biometric Research Professionals

and a Member of Institute of Physics (IOPs) International.

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