Fabless Semiconductor Company Achieve Faster Transistor and Behavioral Simulation with ADiT

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C u s t o m I n t e g r a t e d C I r C u I t s & a n a l o g / m I x e d - s I g n a l s u C C e s s s t o r y

A leading fabless semiconductor company for wireless communications and digital

multimedia solutions, headquartered in Taiwan, was able to increase their verification run times by 95%, dramatically shortening their time to tapeout, using the Mentor Graphics ADiT™ Fast-SPICE simulator.

On this particular project, the team faced two different categories of challenges: design flow and design complexity.

They needed to consolidate tools from an acquired company’s tool flow as well as integrate its IP into their design.

Because ADiT supports all major digital simulators and universally accepts IP written in any standard design language, the designers successfully met both the challenges design flow

and complexity. ADiT either outperformed or matched competitive tools in performance and accuracy during an evaluation to compare how various analog/mixed-signal (AMS) simulators performed in the consolidated tool flow. The team also had confidence in ADiT because they had used the tool for more than a decade.

The other challenges had to do with the design itself. In this case, the team needed to verify an AMS design with 14,000 MOSFET transistors and 56,000 nodes. They had to reduce the turnaround time to meet their tapeout schedule and integrate multiple language blocks.

To be able to speed up simulation, they had to raise the level of abstraction because of the large number of

transistors by replacing some blocks originally at the transistor level with behavioral models. At the time, they began the project, ADiT could only simulate at the transistor level, so the team worked with Mentor Graphics engineers to incorporate behavioral modeling. The result was that they could easily switch transistor-level analog blocks and transistor-level digital blocks into Verilog-AMS and Verilog-D modules, respectively, within the ADiT Verilog-AMS flow.

First, they transferred some of the analog parts of the design from the transistor level to Verilog-AMS. This resulted in a 35% reduction in the number of MOSFETS and a 33% reduction in simulation time.

Next, they transferred some of the digital parts into Verilog-D. The two transformations combined resulted in an 85% reduction in the number of MOSFETS.

Block diagram before transformation of modules.

Mentor Graphics customer support was critical to this success because of the joint development

of the behavioral modeling capability.

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and run test cases very quickly. There was no absolutely no doubt that the ADiT simulation tool delivered improved productivity for their mixed-language, mixed-signal design.

Mentor Graphics Analog/Mixed-Signal IC Design Flow

Performance comparison before and after transformations.

Ultimately, they achieved a 95% reduction in simulation time—from more than 58 hours to just 3 hours—because they were able to run both the behavioral and transistor blocks using ADiT.

Although ADiT delivers good results right out of the box, Mentor Graphics customer support was critical to this success because of the joint development of the behavioral modeling capability. The fabless team enjoyed the dedication of two full-time Mentor AMS experts onsite, who helped them develop their project