f2mc-16lx - fujitsu€¦ · i preface objectives and intended reader thank you for your continued...

FUJITSU MICROELECTRONICSCONTROLLER MANUAL

F2MC-16LX16-BIT MICROCONTROLLER

MB90435 SeriesHARDWARE MANUAL

CM44-10123-2E

F2MC-16LX16-BIT MICROCONTROLLER

MB90435 SeriesHARDWARE MANUAL

The information for microcontroller supports is shown in the following homepage.Be sure to refer to the "Check Sheet" for the latest cautions on development.

"Check Sheet" is seen at the following support page"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.

http://edevice.fujitsu.com/micom/en-support/

FUJITSU MICROELECTRONICS LIMITED

PREFACE

■ Objectives and Intended Reader

Thank you for your continued use of Fujitsu semiconductor products.

The MB90435 series has been developed as a general-purpose version of the F2MC-16LXseries, which is an original 16-bit single-chip microcontroller compatible with Application SpecificICs (ASICs).

This manual describes the functions and operation of the MB90435 series for designers who willuse the MB90435 series to design products. Read this manual before starting to designproducts.

■ Trademark

F2MC is the abbreviation of FUJITSU Flexible Microcontroller.

Other system and product names in this manual are trademarks of respective companies ororganizations.

The symbols TM and ® are sometimes omitted in this manual.

■ Structure of This Manual

This manual has 24 chapters and an appendix:

CHAPTER 1 "OVERVIEW"

This chapter explains the features and basic specifications of the M90540/545 seriesproducts.

CHAPTER 2 "CPU"

This chapter explains the CPU.

CHAPTER 3 "INTERRUPTS"

This chapter explains the interrupt functions and operations.

CHAPTER 4 "CLOCK AND RESET"

This chapter explains the functions and operations of clocks and resets.

CHAPTER 5 "LOW-POWER CONTROL CIRCUIT"

This chapter explains the functions and operation of the low-power control circuit.

CHAPTER 6 "LOW-POWER CONSUMPTION MODES"

This chapter explains the functions and operation of the low-power consumption modes.

CHAPTER 7 "MEMORY ACCESS MODES"

This chapter explains the functions and operations of the memory access modes.

CHAPTER 8 "I/O PORTS"

This chapter explains the functions and operations of the I/O ports.

CHAPTER 9 "TIMEBASE TIMER"

This chapter explains the functions and operations of the timebase timer.

i

CHAPTER 10 "WATCH-DOG TIMER"

This chapter explains the functions and operations of the watch-dog timer.

CHAPTER 11 "WATCH TIMER"

This chapter explains the functions and operations of the watch timer.

CHAPTER 12 "16-BIT I/O TIMER"

This chapter explains the functions and operations of the 16-bit I/O timer.

CHAPTER 13 "16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)"

This chapter explains the functions and operations of the 16-bit reload timer (with the eventcount function).

CHAPTER 14 "8/16-BIT PPG"

This chapter explains the functions and operation of the 8/16-bit PPG.

CHAPTER 15 "DELAYED INTERRUPTS"

This chapter explains the functions and operations of the delayed interrupt.

CHAPTER 16 "DTP/EXTERNAL INTERRUPTS"

This chapter explains the functions and operations of the DTP/external interrupts.

CHAPTER 17 "A/D CONVERTER"

This chapter explains the functions and operations of the A/D converter.

CHAPTER 18 "UART0"

This chapter explains the UART0 functions and operations.

CHAPTER 19 "UART1 (SCI)"

This chapter explains the UART1 (SCI) functions and operation.

CHAPTER 20 "SERIAL I/O"

This chapter explains the functions and operations of the serial I/O.

CHAPTER 21 "ADDRESS MATCH DETECTION FUNCTION"

This chapter explains the address match detection function and operation.

CHAPTER 22 "ROM MIRRORING FUNCTION SELECTION MODULE"

This chapter explains the ROM mirroring function selection module.

CHAPTER 23 "1M/2M-BIT FLASH MEMORY"

This chapter explains the functions and operation of the 1M/2M-bit flash memory.

CHAPTER 24 "EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION"

This chapter provides examples of serial programming connection with the AF220/AF210/AF120/AF110 flash microcomputer programmer manufactured by Yokogawa DigitalComputer Corporation.

Appendix

The appendix provides I/O maps and outlines instructions.

ii

Copyright ©2002-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.

• The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document are presented solely for thepurpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSUMICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. Whenyou develop equipment incorporating the device based on such information, you must assume any responsibility arising out ofsuch use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out ofthe use of the information.

• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as licenseof the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSUMICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes noliability for any infringement of the intellectual property rights or other rights of third parties which would result from the use ofinformation contained herein.

• The products described in this document are designed, developed and manufactured as contemplated for general use, includingwithout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developedand manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical lifesupport system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersiblerepeater and artificial satellite).Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims ordamages arising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from suchfailures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, andprevention of over-current levels and other abnormal operating conditions.

• Exportation/release of any products described in this document may require necessary procedures in accordance with theregulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

iii

CONTENTS

CHAPTER 1 OVERVIEW ................................................................................................... 11.1 Product Overview .................................................................................................................................. 21.2 Features ................................................................................................................................................ 31.3 Block Diagram ....................................................................................................................................... 51.4 Package Dimensions ............................................................................................................................. 61.5 Pin Assignment ...................................................................................................................................... 81.6 Pin Functions ....................................................................................................................................... 101.7 I/O Circuits ........................................................................................................................................... 151.8 Handling the Device ............................................................................................................................. 18

CHAPTER 2 CPU ............................................................................................................. 212.1 Outline of CPU ..................................................................................................................................... 222.2 Memory Space ..................................................................................................................................... 232.3 Memory Space Map ............................................................................................................................. 242.4 Linear Addressing ................................................................................................................................ 252.5 Bank Addressing Types ....................................................................................................................... 262.6 Multi-byte Data in Memory Space ........................................................................................................ 282.7 Registers .............................................................................................................................................. 29

2.7.1 Accumulator (A) .............................................................................................................................. 312.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................... 332.7.3 Processor Status (PS) .................................................................................................................... 342.7.4 Program Counter (PC) .................................................................................................................... 37

2.8 Register Bank ...................................................................................................................................... 382.9 Prefix Codes ........................................................................................................................................ 402.10 Interrupt Disable Instructions ............................................................................................................... 422.11 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions .............................................................. 43

CHAPTER 3 INTERRUPTS .............................................................................................. 453.1 Outline of Interrupts ............................................................................................................................. 463.2 Interrupt Sources ................................................................................................................................. 473.3 Interrupt Vector .................................................................................................................................... 493.4 Hardware Interrupts ............................................................................................................................. 51

3.4.1 Hardware Interrupt Operation ......................................................................................................... 533.4.2 Flow of Hardware Interrupt Operation ............................................................................................ 56

3.5 Software Interrupts .............................................................................................................................. 573.6 Extended Intelligent I/O Service (EI2OS) ............................................................................................. 59

3.6.1 Interrupt Control Register (ICR) ...................................................................................................... 613.6.2 Extended Intelligent I/O Service Descriptor (ISD) .......................................................................... 643.6.3 Operation of Extended Intelligent I/O Service (EI2OS) ................................................................... 673.6.4 Execution Time of the Extended Intelligent I/O Service (EI2OS) .................................................... 69

3.7 Exception Due to Execution of an Undefined Instruction ..................................................................... 71

CHAPTER 4 CLOCK AND RESET .................................................................................. 734.1 Clock Generator ................................................................................................................................... 74

v

4.2 Reset Cause Occurrence .................................................................................................................... 754.3 Reset Causes ..................................................................................................................................... 80

CHAPTER 5 LOW-POWER CONTROL CIRCUIT ........................................................... 835.1 Outline of Low-Power Control Circuit .................................................................................................. 845.2 Block Diagram of Low-Power Control Circuit ...................................................................................... 865.3 Low-Power Control Circuit Registers .................................................................................................. 87

5.3.1 Low-Power Mode Control Register (LPMCR) ................................................................................ 885.3.2 Clock Selection Register (CKSCR) ................................................................................................ 91

5.4 Status Transition for Clock Selection .................................................................................................. 94

CHAPTER 6 LOW-POWER CONSUMPTION MODES ................................................... 976.1 Low-Power Consumption Modes ........................................................................................................ 98

6.1.1 Sleep Mode .................................................................................................................................. 1026.1.2 Pseudo Watch Mode ................................................................................................................... 1036.1.3 Watch Mode ................................................................................................................................. 1046.1.4 Stop mode .................................................................................................................................. 1056.1.5 Hardware Standby Mode ............................................................................................................. 1076.1.6 Intermittent CPU Operation ......................................................................................................... 108

6.2 Status Transitions in Low-Power Consumption Mode ...................................................................... 1096.3 Status Transition Diagram for Low-Power Consumption Mode ........................................................ 114

CHAPTER 7 MEMORY ACCESS MODES .................................................................... 1237.1 Outline of Memory Access Modes .................................................................................................... 124

7.1.1 Mode Pins .................................................................................................................................... 1257.1.2 Mode Data ................................................................................................................................... 1267.1.3 Memory Space in Each Bus Mode .............................................................................................. 127

7.2 External Memory Access (Bus Pin Control Circuit) ........................................................................... 1297.2.1 External Memory Access (External Bus Pin Control Circuit) Registers ....................................... 1307.2.2 Automatic Ready Function Selection Register (ARSR) ............................................................... 1317.2.3 External Address Output Control Register (HACR) ..................................................................... 1337.2.4 Bus Control Signal Selection Register (ECSR) ............................................................................ 134

7.3 External Memory Access Control Signal Operation .......................................................................... 1377.3.1 Ready Function ............................................................................................................................ 1397.3.2 Hold Function ............................................................................................................................... 141

CHAPTER 8 I/O PORTS ................................................................................................ 1438.1 I/O Ports ............................................................................................................................................ 1448.2 I/O Port Registers ............................................................................................................................. 145

8.2.1 Port Data Register (PDR) ............................................................................................................ 1468.2.2 Port Direction Register (DDR) ...................................................................................................... 1478.2.3 Pull-up Control Register (PUCR) ................................................................................................. 1488.2.4 Analog Input Enable Register (ADER) ........................................................................................ 150

CHAPTER 9 TIMEBASE TIMER .................................................................................... 1519.1 Outline of Timebase Timer ................................................................................................................ 1529.2 Timebase Timer Control Register (TBTC) ........................................................................................ 1549.3 Operations of Timebase Timer ......................................................................................................... 156

vi

CHAPTER 10 WATCH-DOG TIMER ................................................................................ 15710.1 Outline of Watch-dog Timer ............................................................................................................... 15810.2 Watch-dog Timer Control Register (WDTC) ...................................................................................... 16010.3 Watch-dog Timer Operation .............................................................................................................. 162

CHAPTER 11 WATCH TIMER ......................................................................................... 16311.1 Outline of Watch Timer ...................................................................................................................... 16411.2 Watch Timer Control Register (WTC) ................................................................................................ 16611.3 Watch Timer Operation ...................................................................................................................... 168

CHAPTER 12 16-BIT I/O TIMER ...................................................................................... 16912.1 Outline of 16-Bit I/O Timer ................................................................................................................. 17012.2 16-bit I/O Timer Registers .................................................................................................................. 17212.3 16-bit Free-running Timer .................................................................................................................. 173

12.3.1 16-bit Free-running Timer Registers ............................................................................................. 17412.3.2 Timer Counter Control Status Register ........................................................................................ 17512.3.3 16-bit Free-running Timer Operation ............................................................................................ 177

12.4 Output Compare ................................................................................................................................ 17912.4.1 Output Compare Register ............................................................................................................. 18012.4.2 Control Status Register of Output Compare ................................................................................. 18112.4.3 16-bit Output Compare Operation ................................................................................................ 184

12.5 Input Capture ..................................................................................................................................... 18712.5.1 Input Capture Register Details ..................................................................................................... 18812.5.2 16-bit Input Capture Operation ..................................................................................................... 190

CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ................ 19313.1 Outline of 16-Bit Reload Timer (with Event Count Function) ............................................................. 19413.2 16-Bit Reload Timer (with Event Count Function) ............................................................................. 196

13.2.1 Timer Control Status Register (TMCSR) ...................................................................................... 19713.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) ...................... 200

13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer .............................................. 20113.4 Underflow Operation of 16-bit Reload Timer ..................................................................................... 20313.5 Output Pin Functions of 16-bit Reload Timer ..................................................................................... 20413.6 Counter Operation State .................................................................................................................... 205

CHAPTER 14 8/16-BIT PPG ............................................................................................ 20714.1 Outline of 8/16-bit PPG ...................................................................................................................... 20814.2 Block Diagram of 8/16-bit PPG .......................................................................................................... 20914.3 8/16-bit PPG Registers ...................................................................................................................... 211

14.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................... 21214.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................... 21414.3.3 PPG0, 1 Clock Selection Register (PPG0/1) ................................................................................ 21714.3.4 Reload Register (PRLL/PRLH) ..................................................................................................... 219

14.4 Operations of 8/16-bit PPG ................................................................................................................ 22014.5 Selecting a Count Clock for 8/16-bit PPG .......................................................................................... 22214.6 Controlling Pin Output of 8/16-bit PPG Pulses .................................................................................. 22314.7 8/16-bit PPG Interrupts ...................................................................................................................... 22414.8 Initial Values of 8/16-bit PPG Hardware ............................................................................................ 225

vii

CHAPTER 15 DELAYED INTERRUPT ............................................................................ 22715.1 Outline of Delayed Interrupt Module ................................................................................................. 22815.2 Delayed Interrupt Register ................................................................................................................ 22915.3 Delayed Interrupt Operation .............................................................................................................. 230

CHAPTER 16 DTP/EXTERNAL INTERRUPTS ............................................................... 23116.1 Outline of DTP/External Interrupts .................................................................................................... 23216.2 DTP/External Interrupt Registers ...................................................................................................... 23416.3 Operations of DTP/External Interrupts .............................................................................................. 23616.4 Switching between External Interrupt and DTP Requests ................................................................ 23816.5 Notes on Using DTP/External Interrupts ........................................................................................... 239

CHAPTER 17 A/D CONVERTER ..................................................................................... 24117.1 Features of A/D Converter ................................................................................................................ 24217.2 Block Diagram of A/D Converter ....................................................................................................... 24417.3 A/D Converter Registers ................................................................................................................... 245

17.3.1 Control Status Registers (ADCS0) ............................................................................................... 24617.3.2 Control Status Register (ADCS1) ................................................................................................ 24917.3.3 Data Registers (ADCR1 and ADCR0) ......................................................................................... 252

17.4 Operations of A/D Converter ............................................................................................................. 25417.5 Conversion Using EI2OS .................................................................................................................. 256

17.5.1 Starting EI2OS in Single Mode ................................................................................................... 25717.5.2 Starting EI2OS in Continuous Mode ............................................................................................ 25917.5.3 Starting EI2OS in Stop Mode ....................................................................................................... 261

17.6 Conversion Data Protection .............................................................................................................. 263

CHAPTER 18 UART0 ...................................................................................................... 26518.1 Feature of UART0 ............................................................................................................................. 26618.2 UART0 Block Diagram ...................................................................................................................... 26718.3 UART0 Registers .............................................................................................................................. 268

18.3.1 Serial Mode Control Register 0 (UMC0) ...................................................................................... 26918.3.2 Status Register 0 (USR0) ............................................................................................................ 27118.3.3 Input Data Register 0 (UIDR0) and Output Data Register 0 (UODR0) ........................................ 27318.3.4 Rate and Data Register 0 (URD0) ............................................................................................... 274

18.4 UART0 Operation ............................................................................................................................. 27618.5 Baud Rate ......................................................................................................................................... 27718.6 Internal and External Clock ............................................................................................................... 28018.7 Transfer Data Format ........................................................................................................................ 28118.8 Parity Bit ............................................................................................................................................ 28218.9 Interrupt Generation and Flag Set Timings ....................................................................................... 283

18.9.1 Flag Set Timings for a Receive Operation (in Mode 0, 1, or 3) .................................................... 28418.9.2 Flag Set Timings for a Receive Operation (in Mode 2) ................................................................ 28518.9.3 Flag Set Timings for a Transmit Operation .................................................................................. 28618.9.4 Status Flag During Transmit and Receive Operation .................................................................. 287

18.10 UART0 Application Example ............................................................................................................. 288

CHAPTER 19 UART1 (SCI) ............................................................................................. 29119.1 Features of UART1 ........................................................................................................................... 292

viii

19.2 UART1 Block Diagram ....................................................................................................................... 29319.3 UART1 Registers ............................................................................................................................... 294

19.3.1 Serial Mode Register 1 (SMR1) .................................................................................................... 29519.3.2 Serial Control Register 1 (SCR1) ................................................................................................. 29719.3.3 Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1) .......................... 29919.3.4 Serial Status Register 1 (SSR1) ................................................................................................... 30019.3.5 UART1 Prescaler Control Register (U1CDCR) ............................................................................ 302

19.4 UART1 Operating Modes and Clock Selection .................................................................................. 30319.4.1 Asynchronous (Start-Stop Synchronized) Mode .......................................................................... 30719.4.2 CLK Synchronous Mode ............................................................................................................... 308

19.5 UART1 Flags and Interrupt Sources .................................................................................................. 31019.6 UART1 Interrupts and Flag Set Timing .............................................................................................. 31119.7 Negative Clock Operation .................................................................................................................. 31419.8 UART1 Sample Applications and Precautionary Information ............................................................ 315

CHAPTER 20 SERIAL I/O ................................................................................................ 31720.1 Outline of Serial I/O ........................................................................................................................... 31820.2 Serial I/O Registers ............................................................................................................................ 319

20.2.1 Serial Mode Control Status Register (SMCS) .............................................................................. 32020.2.2 Serial Shift Data Register (SDR) .................................................................................................. 32520.2.3 Serial I/O Prescaler (SCDCR) ...................................................................................................... 326

20.3 Serial I/O Operation ........................................................................................................................... 32720.3.1 Shift Clock .................................................................................................................................... 32820.3.2 Serial I/O Operation ...................................................................................................................... 32920.3.3 Shift Operation Start/Stop Timing ................................................................................................. 33120.3.4 Interrupt Function of the Serial I/O Interface ................................................................................ 334

20.4 Negative Clock Operation .................................................................................................................. 335

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION .......................................... 33721.1 Overview of the Address Match Detection Function .......................................................................... 33821.2 Registers of the Address Match Detection Function .......................................................................... 33921.3 Operation of the Address Match Detection Function ......................................................................... 34121.4 Example of the Address Match Detection Function ........................................................................... 342

CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE ........................... 34522.1 Outline of ROM Mirroring Function Selection Module ....................................................................... 34622.2 ROM Mirroring Function Selection Register (ROMM) ....................................................................... 347

CHAPTER 23 1M/2M-BIT FLASH MEMORY ................................................................... 34923.1 Outline of 1M/2M-bit Flash Memory ................................................................................................... 35023.2 Sector Configuration of the Flash Memory ........................................................................................ 35123.3 Write/Erase Modes ............................................................................................................................ 35223.4 Flash Memory Control Status Register (FMCS) ................................................................................ 35423.5 Starting the Flash Memory Automatic Algorithm ............................................................................... 35623.6 Confirming the Automatic Algorithm Execution State ........................................................................ 358

23.6.1 Data Polling Flag (DQ7) ............................................................................................................... 36023.6.2 Toggle Bit Flag (DQ6) ................................................................................................................... 36223.6.3 Timing Limit Exceeded Flag (DQ5) .............................................................................................. 363

ix

23.6.4 Sector Erase Timer Flag (DQ3) ................................................................................................... 36423.6.5 Toggle Bit 2 Flag (DQ2) ............................................................................................................... 366

23.7 Detailed Explanation of Writing to and Erasing Flash Memory ......................................................... 36823.7.1 Setting The Read/Reset State ..................................................................................................... 36923.7.2 Writing Data ................................................................................................................................. 37023.7.3 Erasing All Data (Erasing Chips) ................................................................................................. 37223.7.4 Erasing Optional Data (Erasing Sectors) ..................................................................................... 37323.7.5 Suspending Sector Erase ............................................................................................................ 37523.7.6 Restarting Sector Erase ............................................................................................................... 376

23.8 Notes on using 1M/2M-bit Flash Memory ......................................................................................... 37723.9 Flash Security Feature ...................................................................................................................... 37923.10 Example of Programming 1M/2M-bit Flash Memory ......................................................................... 380

CHAPTER 24 EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION 385

24.1 Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection ........................... 38624.2 Example of Serial Programming Connection (User Power Supply Used) ........................................ 39024.3 Example of Serial Programming Connection (Power Supplied from the Programmer) .................... 39224.4 Example of Minimum Connection to the Flash Microcomputer Programmer

(User Power Supply Used) 39424.5 Example of Minimum Connection to the Flash Microcomputer Programmer

(Power Supplied from the Programmer) 396

APPENDIX .......................................................................................................................... 399APPENDIX A I/O Maps ............................................................................................................................... 400APPENDIX B Instructions ........................................................................................................................... 408

B.1 Instruction Types ............................................................................................................................ 409B.2 Addressing ..................................................................................................................................... 410B.3 Direct Addressing ........................................................................................................................... 412B.4 Indirect Addressing ......................................................................................................................... 418B.5 Execution Cycle Count ................................................................................................................... 426B.6 Effective Address Field ................................................................................................................... 429B.7 How to Read the Instruction List .................................................................................................... 430B.8 F2MC-16LX Instruction List ............................................................................................................ 433B.9 Instruction Map ............................................................................................................................... 447

INDEX...................................................................................................................................469

x

xi

Main changes in this edition

The vertical lines marked in the left side of the page show the changes.

Page Changes (For details, refer to main body.)

408 to 468 Changed the entire part of "APPENDIX B Instructions"

CHAPTER 1 OVERVIEW

This chapter explains the features and basic specifications of the MB90435 series products.

1.1 "Product Overview"

1.2 "Features"

1.3 "Block Diagram"

1.4 "Package Dimensions"

1.5 "Pin Assignment"

1.6 "Pin Functions"

1.7 "Input/Output Circuits"

1.8 "Handling the Device"

1

CHAPTER 1 OVERVIEW

1.1 Product Overview

The following table provides a quick outlook of the MB90435 Series

■ Overview of MB90435 series products

Table 1.1-1 Overview

Features MB90V540G MB90F438L(S)/F439(S) MB90437L(S)*1/438L(S)/439(S)

CPU F2MC-16LX CPU

System clock On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop)Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x4)

ROM capacity External Flash memoryMB90F438L(S): 128 KbytesMB90F439(S): 256 Kbytes

MB90437L(S)*1: 64 KbytesMB90438L(S): 128 KbytesMB90439(S): 256 Kbytes

RAM capacity 8 Kbytes MB90F438L(S): 4K bytesMB90F439(S): 6K bytes

MB90437L(S)*1: 2 KbytesMB90438L(S): 4 KbytesMB90439(S): 6 Kbytes

Clocks Two clocks/One clock system

MB90F438L/F439: Two clocks systemMB90F438LS/F439S: One clock system

MB90437L*1/438L/439: Two clocks systemMB90437LS*1/438LS/439S: One clock system

Package PGA-256 QFP100, LQFP100

Emulator- specific power supply *2

None -

*1: Under development*2: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.

Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.

2

1.2 Features

1.2 Features

Table 1.2-1 "MB90435 Series Features" lists the features of the MB90435 series.

■ Features

Table 1.2-1 MB90435 Series Features

Function Feature

UART0 Full duplex double bufferSupports asynchronous/synchronous (with start/stop bit) transferBaud rate: 4808/5208/9615/10417/19230/38460/62500/500000bps (asynchronous)500K/1M/2Mbps (synchronous) at System clock = 16MHz

UART1(SCI)

Full duplex double bufferAsynchronous (start-stop synchronized) and CLK-synchronous communicationBaud rate: 1202/2404/4808/9615/192301/31250/38460/62500bps (asynchronous)62.5K/125K/250K/500K/1Mbps (synchronous) at 6,8,10,12,16 MHz

Serial IO Transfer can be started from MSB or LSBSupports internal clock synchronized transfer and external clock synchronized transferSupports positive-edge and negative-edge clock synchronizationBaud rate: 31.25K/62.5K/125K/500K/1M/2M bps at System clock = 16MHz

A/D Converter

10-bit or 8-bit resolution8 input channelsConversion time: 26.3μs (per one channel)

16-bit Reload Timer(2 channels)

Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)Supports External Event Count function

16-bitI/O Timer

Signals an interrupt when overflowSupports Timer Clear when a match with Output Compare (Channel 0)Operation clock freq.: fsys/22, fsys/24, fsys/26, fsys/28(fsys = System clock freq.)

16-bitOutput Compare(4 channels)

Signals an interrupt when a match with 16-bit IO TimerFour 16-bit compare registersA pair of compare registers can be used to generate an output signal

16-bitInput Capture(8 channels)

Rising edge, falling edge or rising & falling edge sensitiveFour 16-bit Capture registersSignals an interrupt upon external event

3

CHAPTER 1 OVERVIEW

8/16-bit Programmable Pulse Generator (4 channels)

Supports 8-bit and 16-bit operation modesEight 8-bit reload countersEight 8-bit reload registers for L pulse widthEight 8-bit reload registers for H pulse widthA pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter4 output pinsOperation clock freq.: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128μs@fosc=4MHz(fsys = System clock frequency, fosc = Oscillation clock frequency)

External Interrupt Can be programmed edge sensitive or level sensitive

External bus interface

External access using the selectable 8-bit or 16-bit bus is enabled (external bus mode).

IO Ports Virtually all external pins can be used as general purpose IOAll push-pull outputs and schmitt trigger inputsBit-wise programmable as input/output or peripheral signal

32 kHz subclock Subclock for low-power operation

Flash Memory Supports automatic programming, Embedded AlgorithmTM *1

Write/Erase/Erase-Suspend/Resume commandsA flag indicating completion of the algorithmNumber of erase cycles: 10,000 timesData retention time: 10 yearsBoot block configurationErase can be performed on each blockBlock protection by externally programmed voltage

*1: Embeded Algorithm is a trade mark of Advanced Micro Devices Inc.

Table 1.2-1 MB90435 Series Features (Continued)

Function Feature

4

1.3 Block Diagram

1.3 Block Diagram

Figure 1.3-1 "Block Diagram" shows a block diagram of the MB90435 series.

■ Block Diagram

Figure 1.3-1 Block Diagram

RAM 2K/4K/6K

ROM64K/128K/256K

UART0

Prescaler

Serial I/O

10-bit

ADC 8ch

16-bit Reload

Timer 2ch

IO Timer

Clock Controller

Input Capture

8ch

Output Compare

4ch

External Interrupt

8 ch

8/16-bit PPG 4ch

16LXCPU

Inte

rnal

dat

a bu

s

X0, X1

RST

HST

SOT0SCK0SIN0

SCK2SOT2SIN2

AVCC

AVSS

AN0 to AN7AVRHAVRLADTG

TIN0, INT1

TOT0, TOT1

IN0 to IN5

OUT0, OUT1

PPG0 to PPG3

INT0 to INT7

UART1SOT1SCK1SIN1

(SCI)

External bus

interface

AD00 to AD15

A16 to A23

ALERD

WRL/WRWRHHRQ

HAK

RDY

CLK

X0A, X1A

IN6/OUT2, IN7/OUT3

Prescaler

Prescaler

5

CHAPTER 1 OVERVIEW

1.4 Package Dimensions

Figure 1.4-1 "FPT-100P-M06 Package Dimensions" shows the package dimensions of the FPT-100P-M06. Figure 1.4-2 "FPT-100P-M05 Package Dimensions" shows the package dimensions of the FPT-100P-M05Note that the dimensions show below are reference dimensions.For formal dimensions of each package, contact us.

■ FPT-100P-M06 Package Dimensions

Figure 1.4-1 FPT-100P-M06 Package Dimensions

100-pin plastic QFP Lead pitch 0.65 mm

Package width × package length

14.00 × 20.00 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 3.35 mm MAX

100-pin plastic QFP(FPT-100P-M06)

(FPT-100P-M06)

C 2001 FUJITSU LIMITED F100008S-c-4-4

1 30

31

50

5180

81

100

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

14.00±0.20(.551±.008)

17.90±0.40(.705±.016)

INDEX

0.65(.026) 0.32±0.05(.013±.002)

M0.13(.005)

"A"

0.17±0.06(.007±.002)

0.10(.004)

Details of "A" part

0~8°

(.035±.006)0.88±0.15

(.031±.008)0.80±0.20

0.25(.010)3.00

+0.35−0.20+.014−.008.118

(Mounting height)

0.25±0.20(.010±.008)(Stand off)

Dimensions in mm (inches).

Note: Pins width and pins thickness include plating thickness.

6

1.4 Package Dimensions

■ FPT-100P-M05 Package Dimensions

Figure 1.4-2 FPT-100P-M05 Package Dimensions

100-pin plastic LQFP Lead pitch 0.50 mm

Package width package length

14.0 14.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Weight 0.65g

100-pin plastic LQFP(FPT-100P-M05)

(FPT-100P-M05)

C 2000 FUJITSU LIMITED F100007S-3c-5

14.00±0.10(.551±.004)SQ

16.00±0.20(.630±.008)SQ

26

51

76 50

75

100

0.50(.020) 0.20±0.05(.008±.002)

M0.08(.003)0.145±0.055

(.0057±.0022)

0.08(.003)

"A"

INDEX.059

+.008+0.201.50(Mounting height)

0.50±0.20(.020±.008)0.60±0.15

(.024±.006)

0.25(.010)

0.10±0.10(.004±.004)

Details of "A" part

(Stand off)

Dimensions in mm (inches).

Pins width and pins thickness include plating thickness.

1 25

7

CHAPTER 1 OVERVIEW

1.5 Pin Assignment

Figure 1.5-1 "Pin Assignment of FPT-100P-M06"shows the pin assignments of the FPT-100P-M06. Figure 1.5-2 "Pin Assignment of FPT-100P-M05"shows the pin assignments of the FPT-100P-M05.

■ Pin Assignment

Figure 1.5-1 Pin Assignment of FPT-100P-M06

MB90435 series

8

1.5 Pin Assignment

Figure 1.5-2 Pin Assignment of FPT-100P-M05

P22/A18P23/A19P24/A20P25/A21P26/A22P27/A23P30/ALEP31/RD

VSS

P32/WRL/WR

P34/HRQP33/WRH

P35/HAKP36/RDYP37/CLK

P40/SOT0P41/SCK0P42/SIN0P43/SIN1

P44/SCK1VCC

P45/SOT1P46/SOT2P47/SCK2

C

123456789

10111213141516171819202122232425

75747372717069686766656463626160595857565554535251

RSTP97P96P95P94P93/INT3P92/INT2P91/INT1P90/INT0P87/TOT1P86/TIN1P85/OUT1P84/OUT0P83/PPG3P82/PPG2P81/PPG1P80/PPG0P77/OUT3/IN7P76/OUT2/IN6P75/IN5P74/IN4P73/IN3P72/IN2P71/IN1P70/IN0

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

P21

/A17

P20

/A16

P17

/AD

15P

16/A

D14

P15

/AD

13P

14/A

D12

P13

/AD

11P

12/A

D10

P11

/AD

09P

10/A

D08

P07

/AD

07P

06/A

D06

P05

/AD

05P

04/A

D04

P03

/AD

03P

02/A

D02

P01

/AD

01P

00/A

D00

VC

C

X1

X0

VS

S

X0A

X1A

PA

0

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

P50

/SIN

2P

51/IN

T4

P52

/INT

5P

53/IN

T6

P54

/INT

7P

55/A

DT

GA

VC

C

AV

RH

AV

RL

AV

SS

P60

/AN

0P

61/A

N1

P62

/AN

2P

63/A

N3

VS

S

P64

/AN

4P

65/A

N5

P66

/AN

6P

67/A

N7

P56

/TIN

0P

57/T

OT

0M

D0

MD

1M

D2

HS

T

LQFP-100MB90435 series

(TOP VIEW)

FPT-100P-M05

9

CHAPTER 1 OVERVIEW

1.6 Pin Functions

Table 1.6-1 "Pin Functions" lists pin names, circuit types, and pin functions.

■ Pin Functions

Table 1.6-1 Pin Functions

Pin No.Pin name

Circuit type

FunctionLQFP QFP

80, 81 82, 83 X0, X1

A (oscillation)

Pins for high-speed oscillation

78 80X0A

Pin for low-speed oscillation. Pull-down the pin externally for one clock system parts.

77 79X1A

Pin for low-speed oscillation. Leave the pin open for one clock system parts.

75 77 RST B External reset request input pin

50 52 HST C Hardware standby input pin

83 to 90 85 to 92

P00 to P07

I

General-purpose I/O ports with programmable pull-up function. These functions can be used in single-chip mode.

AD00 to AD07I/O pins for lower 8 bits of external address/data bus. These functions can be used when the external bus is enabled.

91 to 98 93 to 100

P10 to P17

I


P08 to AD15I/O pins for upper 8 bits of external address/data bus. These functions can be used when the external bus is enabled.

99 to 6 1 to 8

P20 to P27

I


A16 to A23I/O pins for A16 to A23 of external address bus. These functions can be used when the external bus is enabled.

7 9

P30

I

General-purpose I/O port with programmable pull-up function. This function can be used in single-chip mode.

ALEOutput pin that enables address latch. This function can be used when the external bus is enabled.

8 10

P31

I

General-purpose I/O port with programmable pull-up function. This function can be used in single-chip mode.

RD Read strobe output pin for data bus. This function can be used when the external bus is enabled.

10

1.6 Pin Functions

10 12

P32

I

General-purpose I/O port with programmable pull-up function. This function can be used in single-chip mode or when WR/WRL pin output is disabled.

WRL Write strobe output pin for data bus. This function can be used when both the external bus and WR/WRL pin are enabled.WRL is used for strobe write for the lower 8 bits of the data bus in 16-bit access mode. WR is used for strobe write for 8 bits of the data bus in 8-bit access mode.

WR

11 13

P33

I

General-purpose I/O port with programmable pull-up function. This function can be used in single-chip mode and 8-bit mode for the external bus or when WRH pin output is enabled.

WRH

Write strobe output pin for upper 8 bits of data bus. This function can be used when the external pin is enabled, 16-bit mode for external bus is selected, or the WRH pin output is enabled.

12 14

P34

I

General-purpose I/O port with programmable pull-up function. This function can be used in single-chip mode or when the hold function is disabled.

HRQHold request input pin. This function can be used when both the external bus and hold function are enabled.

13 15

P35

I


HAK Hold acknowledge output pin. This function can be used when both the external bus and hold function are enabled.

14 16

P36

I

General-purpose I/O port with programmable pull-up function. This function can be used in single-chip mode or when the external ready function is disabled.

RDYReady input signal. This function can be used when both the external bus and external ready function are enabled.

15 17

P37

H


CLKClock output pin. This function can be used when both the external bus and clock output are enabled.

16 18

P40

G

General-purpose I/O port. This function can be used when UART0 disables serial data output.

SOT0UART0 serial data output pin. This function can be used when UART0 enables serial data output.

17 19

P41

G

General-purpose I/O port. This function can be used when UART0 disables clock output.

SCK0UART0 clock I/O pin. This function can be used when UART0 enables clock output.

Table 1.6-1 Pin Functions (Continued)

Pin No.Pin name

Circuit type

FunctionLQFP QFP

11

CHAPTER 1 OVERVIEW

18 20

P42

G

General-purpose I/O port. This function can always be used.

SIN0UART0 serial data input pin. Set the corresponding DDR register to input if this function is used.

19 21

P43

G


SIN1UART1 serial data input pin. Set the corresponding DDR register to input if this function is used.

20 22

P44

G

General-purpose I/O port. This function can be used when UART1 disables clock output.

SCK1UART1 clock pulse I/O pin. This pin can be used when UART1 enables clock output.

22 24

P45

G

General-purpose I/O port. This function can be used when UART1 disables serial data output.

SOT1UART1 serial data output pin. This function can be used when UART1 enables serial data output.

23 25

P46

G

General-purpose I/O port. This function can be used when serial I/O disables serial data output.

SOT2Serial data output pin for I/O serial data. This function can be used when serial I/O enables serial data output.

24 26

P47

G

General-purpose I/O port. This function can be used when serial I/O disables clock output.

SCK2Clock pulse I/O pin of serial I/O. This function can be used when serial I/O enables clock output.

26 28

P50

D


SIN2Serial data input pin for serial I/O. Set the corresponding DDR register to input if this function is used.

27 to 30 29 to 32

P51 to P54

D

General-purpose I/O ports. These functions can always be used.

INT4 to INT 7External interrupt request input pins for INT4 and INT7. Set the corresponding DDR register to input if this function is used.

31 33

P55

D


ADTGTrigger input pin for A/D converter. Set the corresponding DDR register to input if this function is used.

36 to 39 38 to 41

P60 to P63

E

General-purpose I/O ports. These functions can be used when ports are specified in the register that enables analog input.

AN0 to AN3Analog input pins for A/D converter. These functions can be used when AD is specified in the register that enables analog input.


Pin No.Pin name

Circuit type

FunctionLQFP QFP

12

1.6 Pin Functions

41 to 44 43 to 46

P64 to P67

E

General-purpose I/O ports. These functions can be used when ports are specified in the register that enables analog input.

AN4 to AN7Analog input pins for A/D converter. These functions can be used when AD is specified in the register that enables analog input.

45 47

P56

D


TIN0Event input pin for reload timer 0. Set the corresponding DDR register to input if this function is used.

46 48

P57

D

General-purpose I/O port. This function can be used when reload timer 0 disables output.

TOT0Output pin for reload timer 0. This function can be used when reload timer 0 enables output.

51 to 56 53 to 58

P70 to P75

D


IN0 to IN5 Data sample input pins from which ICU0 to ICU5 capture data is input. Set the corresponding DDR register to input if this function is used.

57 to 58 59 to 60

P76 to P77

D

General-purpose I/O ports. These functions can be used when the OCU disables waveform output.

OUT2 to OUT3

Waveform output pins from which OCU2 and OCU3 comparison data is output. These functions can be used when the OCU enables waveform output.

IN6 to IN7Data sample input pins from which ICU6 and ICU7 capture data is input. Set the corresponding DDR register to input and disable the OCU waveform output if this function is used.

59 to 62 61 to 64

P80 to P83

D

General-purpose I/O ports. These functions can be used when PPG disables waveform output.

PPG0 to PPG3

PPG output pins. These functions can be used when PPG enables waveform output.

63 to 64 65 to 66

P84 to P85

D

General-purpose I/O ports. These functions can be used when the OCU disables waveform output.

OUT0 to OUT1

Waveform output pins from which OCU0 and OCU1 comparison data is output. These functions can be used when OCU enables waveform output.

65 67

P86

D


TIN1Event input pin for reload timer 1. Set the corresponding DDR register to input if this function is used.

66 68

P87

D

General-purpose I/O port. This function can be used when reload timer 0 disables output.

TOT1Output pin for reload timer 1. This function can be used when reload timer 1 enables output.


Pin No.Pin name

Circuit type

FunctionLQFP QFP

13

CHAPTER 1 OVERVIEW

67 to 70 69 to 72

P90 to P93

D


INT0 to INT3 External interrupt request input pins for INT0 to INT3. Set the corresponding DDR register to input if this function is used.

71 73 P94 D General-purpose I/O port.




76 78 PA0 D General-purpose I/O port.

32 34 AVCCPower supply

Power supply input pin for A/D converter. See Section 1.8 "Handling the Device".

35 37 AVSSPower supply

Dedicated ground pin for A/D converter

33 35 AVRHPower supply

Reference voltage input pin for A/D converter. See Section 1.8 "Handling the Device".

34 36 AVRLPower supply

Reference low-voltage input pin for A/D converter

4748

4950

MD0MD1

COperating-mode-dedicated input pins. Connect these pins directly to VCC or VSS.

49 51 MD2 FOperating-mode-dedicated input pin. Connect this pin directly to VCC or VSS.

25 27 C -Power capacitor pin. Connect this pin externally to a 0.1 μF ceramic capacitor.

21, 82 23, 84 VCCPower supply

Power (5.0V) input pin for digital circuit

9, 4079

11, 4281

VSSPower supply

Ground power (0.0V) pins for digital circuit


Pin No.Pin name

Circuit type

FunctionLQFP QFP

14

1.7 I/O Circuits

1.7 I/O Circuits

Table 1.7-1 "I/O Circuits" shows input/output circuits.

■ I/O Circuits

Table 1.7-1 I/O Circuits

Circuit type Diagram Remarks

A • Oscillation feedback resistor:

Approx. 1 MΩ (High-speed oscillation)Approx. 10 MΩ (Low-speed oscillation)

B• Hysteresis input• Pull-up resistor: Approx. 50 kΩ

C• Hysteresis input

X1, X1A

X0, X0A

Standby control signal

Oscillation feedback resistor

HYSR

R (pull-up)

HYSR

15

CHAPTER 1 OVERVIEW

D• CMOS output• Hysteresis input

E• CMOS output• Hysteresis input• Analog input

F• Hysteresis input• Pull-down resistor:

Approx. 50 kΩ (except flash device product)

G• CMOS output• Hysteresis input• TTL input (for flash device product in

flash write mode only)

Table 1.7-1 I/O Circuits (Continued)


HYS

P-ch

N-ch

R

Analog input

HYS

R

Vcc

P-ch

P-ch

N-ch

N-ch

R

R (pull-down)

HYS

Vcc

RHYS

RTTL

P-ch

N-ch

16

1.7 I/O Circuits

H• CMOS output• Hysteresis input• Programmable pull-up resistor:

Approx. 50 kΩ

I• CMOS output• Hysteresis input• TTL input (for flash device product in

flash write mode only)• Programmable pull-up resistor:

Approx. 50 kΩ

Table 1.7-1 I/O Circuits (Continued)


Vcc

RHYS

Vcc CNTL

P-ch

N-ch

Vcc

RHYS

RTTL

Vcc CNTL

P-ch

N-ch

17

CHAPTER 1 OVERVIEW

1.8 Handling the Device

When handling devices, be careful about the following:• Preventing latch-up• Treatment of unused pins• Using external clock• Power supply pins (VCC/VSS)

• Pull-up/down resistors• Crystal Oscillator Circuit• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs• Connection of Unused Pins of A/D Converter• N.C. Pin• Notes on Energization• Use of the subclock• Initialization• Directions of "DIV A, Ri" and "DIVW A, RWi" instructions• Using REALOS• Notes on during operation of PLL clock mode

■ Handling the Device

❍ Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions:

• A voltage higher than Vcc or lower than Vss is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between VCC and VSS.

• The AVcc power supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to thedevice. For the same reason, also be careful not let the analog power-supply voltage (AVCC, AVRH)exceed the digital power-supply voltage.

❍ Treatment of unused pins

Unused input pins left open may cause abnormal operation, or latch-up leading to permanentdamage. Unused input pins should be pulled down through at least 2KΩ resistance.

Unused input/output pins may be left open in output state, but if such pins are in input state theyshould be handled in the same way as input pins.

18

1.8 Handling the Device

❍ Using external clock

To use external clock, drive X0 pin only and leave X1 pin.

Below is a diagram of how to use external clock.

Figure 1.8-1 Example of Using External Clock

❍ Power supply pins (VCC/VSS)

In products with multiple VCC or VSS pins, the pins of a same potential are internally connectedin the device to avoid abnormal operations including latch-up. However connect the pins toexternal power and ground line to lower the electro-magnetic emission level, to preventabnormal operation of signals caused by the rise in the ground level, and to conform to the totalcurrent rating.

Make sure to connect VCC and VSS pins via the lowest impedance to power lines.

It is recommended to provide a bypass capacitor of around 0.1 μF between VCC and VSS pinsnear the device.

❍ Pull-up/down resistors

The MB90435 series does not support internal pull-up/down resistors (except Port0 - Port3:pull-up resistors). Use external components where needed.

MB90435 seriesX0

X1Open

VccVss

Vss

Vcc

Vss

VccMB90435

Series

Vcc Vss

VccVss

19

CHAPTER 1 OVERVIEW

❍ Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure toprovide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (orceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillationcircuits do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pinswith a ground area for stabilizing the operation.

❍ Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs(AN0 to AN7) after turning-on the digital power supply (VCC).

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In thiscase, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog anddigital power supplies simultaneously is acceptable).

❍ Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.

❍ N.C. Pin

The N.C. (internally connected) pin must be opened for use.

❍ Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time duringenergization at 50 μs or more (0.2 V to 2.7 V).

❍ Use of the subclock

Use the one clock system parts when the subclock is not used. In that case, pull-down the pinX0A and leave the pin X1A open. When using the one clock system parts, a 32 kHz oscillatorhas to be connected to the X0A and X1A pins.

❍ Initialization

In the device, there are internal registers which are initialized only by a power-on reset. Toinitialize these registers, please turn on the power again.

❍ Directions of "DIV A, Ri" and "DIVW A, RWi" instructions

In the Signed multiplication and division instructions ("DIV A, Ri" and "DIVW A, RWi"), the valueof the corresponding bank register (DTB, ADB, USB, SSB) is set in "00h".

If the values of the corresponding bank registers (DTB,ADB,USB,SSB) are set to other than"00H", the remainder by the execution result of the instruction is not stored in the register of theinstruction operand.

❍ Using REALOS

The use of EI2OS is not possible with the REALOS real time operating system.

❍ Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped.Performance of this operation, however, cannot be guaranteed.

20

CHAPTER 2 CPU

This chapter explains the CPU.

2.1 "Outline of CPU"

2.2 "Memory Space"

2.3 "Memory Space Map"

2.4 "Linear Addressing"

2.5 "Bank Addressing Types"

2.6 "Multi-byte Data in Memory Space"

2.7 "Registers"

2.8 "Register Bank"

2.9 "Prefix Codes"

2.10 "Interrupt Disable Instructions"

2.11 "Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions"

21

CHAPTER 2 CPU

2.1 Outline of CPU

The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require high-speed real-time processing, such as home-use or vehicle-mounted electronic

appliances. The F2MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing.

■ Outline of CPU

In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal32-bit accumulator (32-bit data can be processed by some instructions). Memory space of up to16 megabytes (expandable) can be accessed by either the linear or bank method. The

instruction set, based on the F2MC-8 A-T architecture, has been made richer by addinginstructions that are compatible with high-level languages, expanding addressing modes,improving the multiplication and division instructions, and enhancing bit processing.

The features of the F2MC-16LX CPU are explained below.

❍ Minimum instruction execution time: 62.5 ns (at 4-MHz oscillation, 4 times clock multiplication)

❍ Maximum memory space: 16 Mbytes, accessed in linear or bank mode

❍ Instruction set optimized for controller applications

• Rich data types: Bit, byte, word, long word

• Extended addressing modes: 23 types

• High-precision operation (32-bit length) based on 32-bit accumulator

❍ Powerful interrupt functions

Eight priority levels (programmable)

❍ CPU-independent automatic transfer

Up to 16 channels of the extended intelligent I/O service

❍ Instruction set compatible with high-level language (C)/multitasking

System stack pointer/instruction set symmetry/barrel-shift instructions

❍ Improved execution speed: 4-byte queue

22

2.2 Memory Space

2.2 Memory Space

An F2MC-16LX CPU has a 16-megabyte memory space. All data items, programs, and

input-outputs managed by F2MC-16LX CPU are located in this 16-megabyte memory space. The CPU can access resources by indicating their addresses using a 24-bit address bus.

■ Outline of CPU Memory Space

Figure 2.2-1 "Sample Relationship between F2MC-16LX System and Memory Map" shows a

sample relationship between the F2MC-16LX system and memory map.

Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory Map

■ Address Generation Types

The F2MC-16LX has the following two addressing:

❍ Linear addressing

An entire 24-bit address is specified by an instruction.

❍ Bank addressing

The eight high-order bits of an address are specified by an appropriate bank register, and theremaining 16 low-order bits are specified by an instruction.

F2MC-16LX

CPU

[Device]

Program

Data

Interrupt

Peripheral

General-

Program area

Data area

Interrupt controller

Peripheral circuits

General-purpose ports

circuits

purpose ports

FFFFFFHFF8000H

810000H

800000H

0000C0H

0000B0H

000020H

000000H

23

CHAPTER 2 CPU

2.3 Memory Space Map

The memory space of the MB90435 Series is shown in Figure 2.3-1 "Memory Space Map".

■ Memory Space Map

The high-order portion of bank 00 gives the image of the FF bank ROM to make the smallmodel of the C compiler effective. Since the low-order 16 bits are the same, the table in ROMcan be referenced without using the far specification in the pointer declaration.

For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.

The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank00.

The image between FF4000H and FFFFFFH is visible in bank 00, while the image betweenFF0000H and FF3FFFH is visible only in bank FF.

Figure 2.3-1 Memory Space Map

FFFFFFH

FF0000H

FEFFFFH

FE0000H

FDFFFFH

FD0000H

FCFFFFH

FC0000H

00FFFFH

004000H

003FFFH

003900H

0008FFH

000100H

0000BFH

000000H

*1: Under development

FFFFFFH

FF0000H

00FFFFH

004000H

003FFFH

003900H

000100H

0000BFH

000000H

00FFFFH

004000H

003FFFH

003900H

000100H

0000BFH

000000H

MB90V540G MB90437L(S) *1 MB90F438L(S)/438L(S) MB90F439(S)/439(S)

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)

ROM (Image of FF bank)



ROM (FF bank)

Peripheral PeripheralPeripheral

RAM 8K RAM 4K

PeripheralPeripheralPeripheral

RAM 2K

0010FFH

0020FFH

001FF0H001FF5H ROM correction

External access memory

002000H 002000H







FFFFFFH

FF0000H

FEFFFFH

FE0000H

ROM (FF bank)

ROM (FE bank)



FFFFFFH

FF0000H

FEFFFFH

FE0000H

FDFFFFH

FD0000H

FCFFFFH

FC0000H

00FFFFH

004000H

003FFFH

003900H

000100H

0000BFH

000000H

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)


Peripheral

RAM 6K

Peripheral

002100H

0018FFH




24

2.4 Linear Addressing

2.4 Linear Addressing

There are two types of linear addressing:• 24-bit operand specification: Directly specifies a 24-bit address using operands.• 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a

32-bit general-purpose register value as the address.

■ 24-bit Operand Specification

Figure 2.4-1 "Example of Linear Method (24-bit Register Operand Specification)" shows anexample of 24-bit operand specification. Figure 2.4-2 "Example of Linear Method (32-bitRegister Indirect Specification") shows an example of 32-bit register indirect specification.

Figure 2.4-1 Example of Linear Method (24-bit Register Operand Specification)

■ 32-bit Register Indirect Specification

Figure 2.4-2 Example of Linear Method (32-bit Register Indirect Specification)

17

12

452D

3456

17452D H

123456 H

JMPP 123456 H

Old program counter

New program counter

Next instruction

+ program bank

+ program bank

JMPP 123456 H

XXXX

+7

RL1

3AOld AL

New AL

(The high-order eight bits are ignored.)

MOV A, @RL1+7

240906F9

090700 H

003A

25

CHAPTER 2 CPU

2.5 Bank Addressing Types

In the bank method, the 16-Mbyte space is divided into 256 64-Kbyte banks. The following five bank registers are used to specify the banks corresponding to each space:• Program bank register (PCB)• Data bank register (DTB)• User stack bank register (USB)• System stack bank register (SSB)• Additional bank register (ADB)

■ Bank Addressing Types

❍ Program bank register (PCB)

The 64-Kbyte bank specified by the PCB is called a program (PC) space. The PC spacecontains instruction codes, vector tables, and immediate value data, for example.

❍ Data bank register (DTB)

The 64-Kbyte bank specified by the DTB is called a data (DT) space. The DT space containsreadable/writable data, and control/data registers for internal and external resources.

❍ User stack bank register (USB)/system stack bank register (SSB)

The 64-Kbyte bank specified by the USP or SSP is called a stack (SP) space. The SP space isaccessed when a stack access occurs during a push/pop instruction or interrupt register saving.The S flag in the condition code register determines the stack space to be accessed.

❍ Additional bank register (ADB)

The 64-Kbyte bank specified by the ADB is called an additional (AD) space. The AD space, forexample, contains data that cannot fit into the DT space.

Table 2.5-1 "Default Space" lists the default spaces used in each addressing mode, which arepre-determined to improve instruction coding efficiency. To use a non-default space for anaddressing mode, specify a prefix code corresponding to a bank before the instruction. Thisenables access to the bank space corresponding to the specified prefix code.

After reset, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a valuespecified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H(000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector.

26

2.5 Bank Addressing Types

Figure 2.5-1 "Physical Addresses of Each Space" is an example of a memory space divided intoregister banks.

Figure 2.5-1 Physical Addresses of Each Space

Table 2.5-1 Default Space

Default space Addressing mode

Program space PC indirect, program access, branch

Data space Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir

Stack space Addressing mode using PUSHW, POPW, @RW3, or @RW7

Additional space Addressing mode using @RW2 or @RW6

FF H

B3 H

92H

68H

4B H

FFFFFFH

FF0000 H

B3FFFFH

920000 H

68FFFFH

680000H

4BFFFFH

4B0000H

000000H

Phy

sica

l add

ress

Program space

Additional space

User stack space

Data space

System stack space

: PCB (Program bank register)

: ADB (Additional bank register)

: USB (User stack bank register)

: DTB (Data bank register)

: SSB (System stack bank register)

92FFFFH

B30000H

27

CHAPTER 2 CPU

2.6 Multi-byte Data in Memory Space

Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits.If a reset signal is input immediately after the low-order bits are written, the high-order bits might not be written.

■ Multi-byte Data Allocation in Memory Space

Figure 2.6-1 "Sample Allocation of Multi-byte Data in Memory" is a diagram of multi-byte dataconfiguration in memory. The low-order eight bits of a data item are stored at address n, thenaddress n+1, address n+2, address n+3, etc.

Figure 2.6-1 Sample Allocation of Multi-byte Data in Memory

■ Accessing Multi-byte Data

Fundamentally, accesses are made within a bank. For an instruction accessing a multi-bytedata item, address FFFFH is followed by address 0000H of the same bank. Figure 2.6-2"Execution of MOVW A, 080FFFFH" is an example of an instruction accessing multi-byte data.

Figure 2.6-2 Execution of MOVW A, 080FFFFH

H

L

01010101

11001100

11111111

00010100

MSB LSB

01010101 11001100 11111111 00010100

Address n

L

H

80FFFF H

800000 H

01H

23H

?? ??

23H 01H

AL before execution

AL after execution

···

28

2.7 Registers

2.7 Registers

The F2MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture. The general-purpose registers share the CPU address space with RAM. The general-purpose registers are the same as the special registers in that they can be accessed without using an address. The applications of the general-purpose registers can be specified by the user however, as is ordinary memory space.

■ Special Registers

The F2MC-16LX CPU core has the following 13 special registers:

• Accumulator (A=AH:AL): Two 16-bit accumulators (Can be used as a single 32-bitaccumulator.)

• User stack pointer (USP): 16-bit pointer indicating the user stack area

• System stack pointer (SSP): 16-bit pointer indicating the system stack area

• Processor status (PS): 16-bit register indicating the system status

• Program counter (PC): 16-bit register holding the address of the program

• Program bank register (PCB): 8-bit register indicating the PC space

• Data bank register (DTB): 8-bit register indicating the DT space

• User stack bank register (USB): 8-bit register indicating the user stack space

• System stack bank register (SSB): 8-bit register indicating the system stack space

• Additional bank register (ADB): 8-bit register indicating the AD space

• Direct page register (DPR): 8-bit register indicating a direct page

Figure 2.7-1 "Special Registers" is a diagram of the special registers.

29

CHAPTER 2 CPU

Figure 2.7-1 Special Registers

■ General-purpose Registers

The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH(maximum configuration) of main storage. The register bank pointer (RP) indicates which of theabove addresses are currently being used as a register bank. Each bank has the following threetypes of registers. These registers are mutually dependent as described in Figure 2.7-2"General-purpose Registers".

• R0 to R7: 8-bit general-purpose register

• RW0 to RW7: 16-bit general-purpose register

• RL0 to RL3: 32-bit general-purpose register

Figure 2.7-2 General-purpose Registers

The relationship between the high-order and low-order bytes of a byte or word register isexpressed as follows:

RW (i + 4) = R (i x 2 + 1) x 256 + R (i x 2) [i=0 to 3]

The relationship between the high-order and low-order bytes of Rli and RW can be expressedas follows:

RL (i) = RW (i x 2 + 1) x 65536+RW (i x 2) [i=0 to 3]

Accumulator

User stack pointer

System stack pointer

Processor status

Program counter

Direct page register

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

AH AL

USP

SSP

PS

PC

DPR

PCB

DTB

USB

SSB

ADB

8 bit16 bit

32 bit

000180 H + RP × 10H

MSB LSB

RW0

RW1

RW2

RW3

R1 R0

R3

R5

R7

R2

R4

R6

RW4

RW5

RW6

RW7

RL0

RL1

RL2

RL3

16 bit

First address ofLow-order

High-order

general-purpose register

30

2.7 Registers

2.7.1 Accumulator (A)

The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data.

■ Accumulator (A)

In 32-bit data processing, AH and AL are used together. Only AL is used for word processing in16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figure2.7-3 "32-bit Data Transfer" and Figure 2.7-4 "AL-AH Transfer") . The data in the A register can

be operated upon with data in memory or with registers (Ri, RWi, or RLi). As with the F2MC-8L,when a word or shorter data item is transferred to AL, the previous data item in AL isautomatically transferred to AH (data save function). The data save function and the operationsbetween AL and AH help to improve processing efficiency.

When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-extended and stored as a 16-bit data item in AL. The data in AL can be handled either as wordor byte long.

When a byte-processing arithmetic operation instruction is executed on AL, the high-order eightbits of AL before operation are ignored. The high-order eight bits of the operation result allbecome zeroes.

The A register is not initialized by a reset. The A register holds an undefined value immediatelyafter a reset.

Figure 2.7-3 32-bit Data Transfer

XXXX H XXXX H

8F74 H 2B52 H

DTB A6 H+6

RW1

A61540 H

A6153E H

MSB LSB

8F H

2B H

15H

74H

52H

38HAH AL

MO VL A,@R W1+6

Old A

New A

(Instruction that performs a long-word-length read using the result of RW1 + an 8-bit offset as the address and stores the read value in the A register)

Memory space

31

CHAPTER 2 CPU

Figure 2.7-4 AL-AH Transfer

+6

RW1

A61540 H

A6153E H

XXXX H 1234 H

1234 H 1234 H

DTB A6 H

8F H

2B H

15H

74H

52H

38H

MSB LSB

MO VW A,@R W1+6

Old A

New A

(Instruction that performs a word-length read using the result of RW1 + an 8-bit offset as the address and stores the read value in the A register)

Memory space

32

2.7 Registers

2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP)

USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed.

■ User Stack Pointer (USP) and System Stack Pointer (SSP)

USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoringdata in the event of a push/pop instruction or subroutine execution. The USP and SSP registersare used by stack instructions. The USP register is enabled when the S flag in the processorstatus register is '0,' and the SSP register is enabled when the S flag is '1' (see Figure 2.7-5"Stack Manipulation Instruction and Stack Pointer"). Since the S flag is set when an interrupt isaccepted, register values are always saved in the memory area indicated by SSP duringinterrupt processing. SSP is used for stack processing in an interrupt routine, while USP is usedfor stack processing outside an interrupt routine. If the stack space is not divided, use only theSSP.

During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP)or USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefinedvalues.

Figure 2.7-5 Stack Manipulation Instruction and Stack Pointer

Note:

Specify an even-numbered address in the stack pointer whenever possible.

AL A624 H USB USP

SSPSSB0

C6 H

56H

F328 H

1234 H

C6F326 H

MSB LSB

XXXX

AL A624 H USB USP

SSPSSB0

C6 H

56H

F326 H

1234 H C6F326 H 24HA6 H

AL A624 H USB USP

SSPSSB

C6 H

56H

F328 H

1234 H

561232 H XXXX

1

AL A624 H USB USP

SSPSSB1

C6 H

56H

F328 H

1232 H

561232 H 24HA6 H

Example 1 PUSHW A when the S flag is '0'

Before execution

S flag

After executionUser stack is used because

Example 2 PUSHW A when the S flag is '1'

System stack is used becausethe S flag is '1.'

the S flag is '0.'

Before execution

After execution

33

CHAPTER 2 CPU

2.7.3 Processor Status (PS)

The PS register consists of the bits controlling the CPU Operation and the bits indicating the CPU status.

■ Processor Status (PS)

As shown in Figure 2.7-6 "Processor Status (PS) Structure", the high-order byte of the PSregister consists of a register bank pointer (RP) and an interrupt level mask register (ILM). TheRP indicates the start address of a register bank. The low-order byte of the PS register is acondition code register (CCR), containing the flags to be set or reset depending on the results ofinstruction execution or interruptoccurrences.

Figure 2.7-6 Processor Status (PS) Structure

■ Condition Code Register (CCR)

Figure 2.7-7 "Condition Code Register (CCR) Configuration" is a diagram of condition coderegister configuration.

Figure 2.7-7 Condition Code Register (CCR) Configuration

❍ I: Interrupt enable flag:

Interrupts other than software interrupts are enabled when the I flag is 1 and are masked whenthe I flag is 0. The I flag is cleared by a reset.

❍ S: Stack flag:

When the S flag is 0, USP is enabled as the stack manipulation pointer.

When the S flag is 1, SSP is enabled as the stack manipulation pointer.

The S flag is set by an interrupt reception or a reset.

❍ T: Sticky bit flag:

1 is set in the T flag when there is at least one '1' in the data shifted out from the carry afterexecution of a logical right/arithmetic right shift instruction. Otherwise, 0 is set in the T flag. Inaddition, '0' is set in the T flag when the shift amount is zero.

❍ N: Negative flag:

The N flag is set when the MSB of the operation result is '1,' and is otherwise cleared.

ILM RP CCRPS

15 13 12 8 7 0

Initial value 000 00000 -01XXXXX X:Undefined

7 6 5 4 3 2 1 0

- I S T N Z V C : CCR

- 0 1 X X X X XInitial value X: Undefined

34

2.7 Registers

❍ Z: Zero flag:

The Z flag is set when the operation result is all zeroes, and is otherwise cleared.

❍ V: Overflow flag:

The V flag is set when an overflow of a signed value occurs as a result of operation executionand is otherwise cleared.

❍ C: Carry flag:

The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operationexecution, and is otherwise cleared.

■ Register Bank Pointer (RP)

The RP register indicates the relationship between the general-purpose registers of the F2MC-16LX and the internal RAM addresses. Specifically, the RP register indicates the first memoryaddress of the currently used register bank in the following conversion expression: [00180H +(RP) x 10H] (see Figure 2.7-8 "Register Bank Pointer (RP)"). The RP register consists of fivebits, and can take a value between 00H and 1FH. Register banks can be allocated at addressesfrom 000180H to 00037H in memory.

Even within that range, however, the register banks cannot be used as general-purposeregisters if the banks are not in internal RAM. The RP register is initialized to all zeroes by areset. An instruction may transfer an eight-bit immediate value to the RP register; however, onlythe low-order five bits of that data are used.

Figure 2.7-8 Register Bank Pointer (RP)

■ Interrupt Level Mask Register (ILM)

The ILM register consists of three bits, indicating the CPU interrupt masking level. An interruptrequest is accepted only when the level of the interrupt is higher than that indicated by thesethree bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (seeTable 2.7-1 "Levels Indicated by the Interrupt Level Mask (ILM) Register"). Therefore, for aninterrupt to be accepted, its level value must be smaller than the current ILM value. When aninterrupt is accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the sameor lower level cannot be accepted subsequently. ILM is initialized to all zeroes by a reset. Aninstruction may transfer an eight-bit immediate value to the ILM register, but only the low-orderthree bits of that data are used.

Figure 2.7-9 Interrupt Level Register (ILM)

Initial value

B 3 B 2 B 1 B 0B4

0 0 0 0 0

: RP

Initial value

I L M 2 I L M 1 I L M 0

0 0 0

: ILM

35

CHAPTER 2 CPU

Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register

ILM2 ILM1 ILM0 Level value Acceptable interrupt level

0 0 0 0 Interrupt disabled

0 0 1 1 0 only

0 1 0 2 Level value smaller than 1






36

2.7 Registers

2.7.4 Program Counter (PC)

The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. The high-order eight bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset.The PC register can also be used as a base pointer for operand access.

■ Program Counter (PC)

Figure 2.7-10 "Program Counter" shows the program counter.

Figure 2.7-10 Program Counter

PCB PCFE H ABCD H

FEABCD H

Next instruction to be executed

37

CHAPTER 2 CPU

2.8 Register Bank

A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers.

■ Register Bank

Table 2.8-1 "Register Functions" lists the functions of the registers. Table 2.8-2 "Relationshipbetween Registers" indicates the relationship between the registers.

In the same manner as for an ordinary RAM area, the register bank values are not initialized bya reset. The status before a reset is maintained. When the power is turned on, however, theregister bank will have an undefined value.

Table 2.8-1 Register Functions

R0 to R7 Used as operands of instructions.Note: R0 is also used as a counter for barrel shift or normalization instructions.

RW0 to RW7 Used as pointers.Used as operands of instructions.Note: RW0 is used as a counter for string instructions.

RL0 to RL3 Used as long pointers.Used as operands of instructions.

Table 2.8-2 Relationship between Registers

RW0RL0

RW1

RW2RL1

RW3

R0RW4

RL2R1

R2RW5

R3

R4RW6

RL3R5

R6RW7

R7

38

2.8 Register Bank

❍ Direct page register (DPR) <Initial value: 01H>

DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shownin Figure 2.8-1 "Generating a Physical address in Direct Addressing Mode". DPR is eight bitslong, and is initialized to 01H by a reset. DPR can be read or written to by an instruction.

Figure 2.8-1 Generating a Physical address in Direct Addressing Mode

❍ Program counter bank register (PCB) <Initial value: Value in reset vector>

❍ Data bank register(DTB) <Initial value: 00H>

❍ User stack bank register(USB) <Initial value: 00H>

❍ System stack bank register(SSB) <Initial value: 00H>

❍ Additional data bank register(ADB) <Initial value: 00H>

Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), orAD space is allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset.Bank registers other than PCB can be read or written to. PCB can be read but cannot be writtento.

PCB is updated when the JMPP, CALLP, RETP, RETI, or RETF instruction branching to theentire 16-Mbyte space is executed or when an interrupt occurs. For operation of each register,see Section 2.2 "Memory space".

α α α α α α α α

α α α α α α α α β β β β β β β β γ γ γ γ γ γ γ γ

MSB LSB

DTB register

24-bit physicaladdress

γ γ γ γ γ γ γ γβ β β β β β β β

Direct address during instructionDPR register

39

CHAPTER 2 CPU

2.9 Prefix Codes

Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix.

■ Bank Select Prefix

The memory space used for accessing data is determined for each addressing mode.

When a bank select prefix is placed before an instruction, the memory space used for accessingdata by that instruction can be selected regardless of the addressing mode.

Table 2.9-1 "Bank Select Prefix" lists the bank select prefixes and the corresponding memoryspaces.

Use the following instructions with care:

❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)

The bank register specified by an operand is used regardless of the prefix.

❍ Stack manipulation instructions (PUSHW, POPW)

SSB or USB is used according to the S flag regardless of the prefix.

❍ I/O access instructions

The IO space of the bank is used regardless of the prefix.

❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8)

The instruction is executed normally, but the prefix affects the next instruction.

❍ POPW PS

SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the nextinstruction.

Table 2.9-1 Bank Select Prefix

Bank select prefix Space selected

PCB PC space

DTB Data space

ADB AD space

SPBEither the SSP or USP space is used according to the stack flag value.

MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8MOV io, #imm16 / MOVB A, io:bp / MOB io:bp, A /SETB io:bp / CLRB io:bpBBC io:bp, rel / BBS io:bp, rel WBTC, WBTS

40

2.9 Prefix Codes

❍ MOV ILM,#imm8


❍ RETI

SSB is used regardless of the prefix.

■ Common Register Bank Prefix (CMR)

To simplify data exchange between multiple tasks, the same register bank must be accessedrelatively easily regardless of the RP value. When CMR is placed before an instruction thataccesses a register bank, that instruction accesses the common bank (the register bankselected when RP=0) at addresses from 000180H to 00018FH regardless of the current RPvalue. When using the common register bank prefix (CMR), use the following instructionscarefully:


If an interrupt request occurs during execution of a string instruction with a prefix code, theprefix code becomes invalid when the string instruction is resumed after the interrupt isprocessed. Thus, the string instruction is executed falsely after the interrupt is processed. Donot prefix any of the above string instructions with CMR.

❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)


❍ MOV ILM,#imm8


■ Flag Change Disable Prefix (NCC)

To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before aninstruction disables flag changes associated with that instruction. When using the flag changedisable prefix (NCC), use the following instructions carefully:


If an interrupt request occurs during execution of a string instruction with a prefix code, theprefix code becomes invalid when the string instruction is resumed after the interrupt isprocessed. Thus, the string instruction is executed incorrectly after the interrupt is processed.Do not prefix any of the above string instructions with NCC.

❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)


❍ Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI)

CCR changes according to the instruction specifications regardless of the prefix.

❍ JCTX @A

CCR changes according to the instruction specifications regardless of the prefix.

❍ MOV ILM,#imm8


41

CHAPTER 2 CPU

2.10 Interrupt Disable Instructions

Interrupt requests are not sampled for the following ten instructions: - MOV ILM,#imm8 - PCB - SPB - OR CCR,#imm8 - NCC - AND CCR,#imm8 - ADB - CMR - POPW PS - DTB

■ Interrupt Disable Instructions

If a valid interrupt request occurs during execution of any of the above instructions, the interruptcan be processed only when an instruction other than the above is executed. For details, seeFigure 2.10-1 "Interrupt Disable Instruction".

Figure 2.10-1 Interrupt Disable Instruction

■ Restrictions on Interrupt Disable Instructions and Prefix Instructions

When a prefix code is placed before an interrupt disable instruction, the prefix code affects thefirst instruction after the code other than the interrupt disable instruction.

Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes

■ Consecutive Prefix Codes

When competitive prefix codes are placed consecutively, the latter becomes valid.

In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB.

Figure 2.10-3 Consecutive Prefix Codes

• • • • • • • • • • •

Interrupt disable instruction

Interrupt request Interrupt acceptance

(a) Ordinary instruction

(a)

• • • •MOV A, FF H

CCR:XXX10XX

NCC MOV ILM,#imm8 ADD A,01 H

CCR:XXX10XX

Interrupt disable instruction

CCR does not change with NCC.

• • • • • • • •A D B D T B P C B A D D A , 0 1 H •

Prefix code

PCB is valid as the prefix code

42

2.11 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions

2.11 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions

Set the value of the corresponding bank register to "00H" when using "DIV A, Ri" and

"DIVW A, RWi" instructions.

■ Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions

If the value of corresponding bank registers (DTB, ADB, USB, SSB) is set to "00H", theremainder of division results are stored in the register of the instruction operand. If the value isset to a value other than "00H", the higher 8-bit address is specified by the bank registercorresponding to the register of the instruction operand. The lower 16-bit address thenbecomes the same address as that of the register of the instruction operand at which theremainder is stored.

Table 2.11-1 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions

Instruction Name of the bank register affected

when executing the instructions shown

in the table

Address at which the remainder is stored

DIV A, R0 DTB (DTB: Higher 8-bit) + (0180H + RP x 10H + 8H : Lower 16-bit)

DIV A, R1 (DTB: Higher 8-bit) + (0180H + RP x 10H + 9H : Lower 16-bit)

DIV A, R4 (DTB: Higher 8-bit) + (0180H + RP x 10H + CH : Lower 16-bit)

DIV A, R5 (DTB: Higher 8-bit) + (0180H + RP x 10H + DH : Lower 16-bit)

DIVW A, RW0 (DTB: Higher 8-bit) + (0180H + RP x 10H + 0H : Lower 16-bit)



DIVW A, RW5 (DTB: Higher 8-bit) + (0180H + RP x 10H + AH : Lower 16-bit)

DIV A, R2 ADB (ADB: Higher 8-bit) + (0180H + RP x 10H + AH : Lower 16-bit)

DIV A, R6 (ADB: Higher 8-bit) + (0180H + RP x 10H + EH : Lower 16-bit)

DIVW A, RW2 (ADB: Higher 8-bit) + (0180H + RP x 10H + 4H : Lower 16-bit)

DIVW A, RW6 (ADB: Higher 8-bit) + (0180H + RP x 10H +EH : Lower 16-bit)

DIV A, R3 USBSSB *1

(USB *2: Higher 8-bit) + (0180H + RP x 10H + BH : Lower 16-bit)

DIV A, R7 (USB *2: Higher 8-bit) + (0180H + RP x 10H + FH : Lower 16-bit)

DIVW A, RW3 (USB *2: Higher 8-bit) + (0180H + RP x 10H + 6H : Lower 16-bit)

DIVW A, RW7 (USB *2: Higher 8-bit) + (0180H + RP x 10H + EH : Lower 16-bit)

*1: Depending on the S bit of the CCR register*2: When the S bit of the CCR register is "0"

43

CHAPTER 2 CPU

[Example]

If "DIV A, R0" instruction is executed in the case of DTB=053H/RP=003H, the address of R0is as follows: 0180H+RP (003H) x 10H+08H (address equivalent to R0) = 0001B8H

The bank register to be specified by "DIV A, R0" is DTB, so the address to which bank-specified 053H is added, that is 05301B8H, is the address at which the remainder of a resultis stored.

For an explanation of the bank register, Ri register, and RWi register, see Section 2.7"Registers".

■ Evasion of notes

In order to evade notes of the "DIV A, Ri" and "DIVW A, RWi" instructions during programdevelopment, the compiler modifies the program so that the respective instructions are notgenerated. The assembler then replaces these instructions by functions equivalent to theinstruction strings.

Use the following compiler and assembler.

• Compiler: Version V02L06 of cc907 or later, and version V30L02 of fcc907s or later

• Assembler: Version V03L04 of asm907a or later, and version V30L04 (Rev.30004) of

fasm907s or later

44

CHAPTER 3 INTERRUPTS

This chapter explains the interrupt functions and operations.

3.1 "Outline of Interrupts"

3.2 "Interrupt Sources"

3.3 "Interrupt Vector"

3.4 "Hardware Interrupts"

3.5 "Software Interrupts"

3.6 "Extended Intelligent I/O Service (EI2OS)"

3.7 "Exception Due to Execution of an Undefined Instruction

45


3.1 Outline of Interrupts

The F2MC-16LX has interrupt functions that, when an event occurs, terminate the processing being currently executed and transfer control to a separately defined program.

■ Outline of Interrupts

There are four types of interrupt functions:

• Hardware interrupt: Interrupt processing due to an internal resource event

• Software interrupt: Interrupt processing due to an instruction causing a software event

• Extended intelligent I/O service (EI2OS): Transfer processing due to an internal resourceevent

• Exception: Termination due to an operation exception

This section explains these four types

46

3.2 Interrupt Sources

3.2 Interrupt Sources

Table 3.2-1 "Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers" lists the interrupt sources, interrupt vectors, and interrupt control registers in the MB90435 series.

■ Interrupt Sources

Table 3.2-1 Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers

Interrupt source EI2OS clearInterrupt vector Interrupt control register

Number Address Number Address

Reset X #08 FFFFDCH - -

INT9 instruction X #09 FFFFD8H - -

Exception X #10 FFFFD4H - -

Reserved X #11 FFFFD0H ICR00 0000B0H

Reserved X #12 FFFFCCH

Reserved X #13 FFFFC8H ICR01 0000B1H

Reserved X #14 FFFFC4H

External interrupt INT0/INT1 O #15 FFFFC0H ICR02 0000B2H

Timebase timer X #16 FFFFBCH

16-bit reload timer 0 O #17 FFFFB8H ICR03 0000B3H

A/D converter O #18 FFFFB4H

Input/output timer X #19 FFFFB0H ICR04 0000B4H

External interrupt INT2/INT3 O #20 FFFFACH

Serial I/O O #21 FFFFA8H ICR05 0000B5H

PPG 0/1 X #22 FFFFA4H

Input capture 0 O #23 FFFFA0H ICR06 0000B6H

External interrupt INT4/INT5 O #24 FFFF9CH

Input capture 1 O #25 FFFF98H ICR07 0000B7H

PPG 2/3 X #26 FFFF94H

External interrupt INT6/INT7 O #27 FFFF90H ICR08 0000B8H

Monitoring timer X #28 FFFF8CH

PPG 4/5 X #29 FFFF88H ICR09 0000B9H

Input capture 2/3 O #30 FFFF84H

47


Note:

In a peripheral module in which two interrupt sources are assigned to the same interrupt

number, an EI2OS interrupt clear signal clears both interrupt request flags.

At EI2OS termination, an EI2OS clear signal is issued to all interrupt flags assigned to the

same interrupt number. If an interrupt flag starts EI2OS and another interrupt flag is set by a

hardware event, the flag is cleared by the EI2OS clear signal issued by the first event and

the latter event is lost. Do not use EI2OS for this interrupt number.

When EI2OS is enabled, one of two interrupt signals in the same interrupt control register

(ICR) is issued to start EI2OS. Although an individual EI2OS descriptor should be provided

for each interrupt source, the two interrupt sources actually share the same EI2OS

descriptor. While one interrupt source is using EI2OS, therefore, the other interrupt sourcemust be disabled.

PPG 6/7 X #31 FFFF80H ICR10 0000BAH

Output compare 0 O #32 FFFF7CH

Output compare 1 O #33 FFFF78H ICR11 0000BBH

Input capture 4/5 O #34 FFFF74H

Output compare 2/3-input capture 6/7

O #35 FFFF70H ICR12 0000BCH

16-bit reload timer 1 O #36 FFFF6CH

UART 0 receive #37 FFFF68H ICR13 0000BDH

UART 0 transmit O #38 FFFF64H

UART 1 receive #39 FFFF60H ICR14 0000BEH

UART 1 transmit O #40 FFFF5CH

Flash memory X #41 FFFF58H ICR15 0000BFH

Delayed interrupt X #42 FFFF54HH

: An EI2OS interrupt clear signal clears the interrupt request flag. A stop request is issued.O : An EI2OS interrupt clear signal clears the interrupt request flag.X : An EI2OS interrupt clear signal does not clear the interrupt request flag.

Table 3.2-1 Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers (Continued)

Interrupt source EI2OS clearInterrupt vector Interrupt control register

Number Address Number Address

48

3.3 Interrupt Vector

3.3 Interrupt Vector

Table 3.3-1 "Interrupt Vector" lists MB90435 series interrupt vectors.

■ Interrupt Vector

Table 3.3-1 Interrupt Vector

Software interrupt

instruction

Vector address L

Vector address M

Vector address H

Mode register

Interrupt No.

Hardware interrupt

INT 0 FFFFFCH FFFFFDH FFFFFEH Not used #0 None

: : : : : : :

INT 7 FFFFE0H FFFFE1H FFFFE2H Not used #7 None

INT 8 FFFFDCH FFFFDDH FFFFDEH FFFFDFH #8 (RESET vector)

INT 9 FFFFD8H FFFFD9H FFFFDAH Not used #9 ROM correction

INT 10 FFFFD4H FFFFD5H FFFFD6H Not used #10 <Exception>

INT 11 FFFFD0H FFFFD1H FFFFD2H Not used #11 None

INT 12 FFFFCCH FFFFCDH FFFFCEH Not used #12 None

INT 13 FFFFC8H FFFFC9H FFFFCAH Not used #13 None

INT 14 FFFFC4H FFFFC5H FFFFC6H Not used #14 None

INT 15 FFFFC0H FFFFC1H FFFFC2H Not used #15 External interrupt INT0/INT1

INT 16 FFFFBCH FFFFBDH FFFFBEH Not used #16 Timebase timer

INT 17 FFFFB8H FFFFB9H FFFFBAH Not used #17 16-bit reload timer 0

INT 18 FFFFB4H FFFFB5H FFFFB6H Not used #18 A/D converter

INT 19 FFFFB0H FFFFB1H FFFFB2H Not used #19 I/O timer

INT 20 FFFFACH FFFFADH FFFFAEH Not used #20 External interrupt INT2/INT3

INT 21 FFFFA8H FFFFA9H FFFFAAH Not used #21 Serial I/O

INT 22 FFFFA4H FFFFA5H FFFFA6H Not used #22 PPG 0/1

INT 23 FFFFA0H FFFFA1H FFFFA2H Not used #23 Input capture 0

INT 24 FFFF9CH FFFF9DH FFFF9EH Not used #24 External interrupt INT4/INT5

INT 25 FFFF98H FFFF99H FFFF9AH Not used #25 Input capture 1

INT 26 FFFF94H FFFF95H FFFF96H Not used #26 PPG 2/3

49


INT 27 FFFF90H FFFF91H FFFF92H Not used #27 External interrupt INT6/INT7

INT 28 FFFF8CH FFFF8DH FFFF8EH Not used #28 Monitoring timer

INT 29 FFFF88H FFFF89H FFFF8AH Not used #29 PPG 4/5

INT 30 FFFF84H FFFF85H FFFF86H Not used #30 Input capture 2/3

INT 31 FFFF80H FFFF81H FFFF82H Not used #31 PPG 6/7

INT 32 FFFF7CH FFFF7DH FFFF7EH Not used #32 Output compare 0

INT 33 FFFF78H FFFF79H FFFF7AH Not used #33 Output compare 1

INT 34 FFFF74H FFFF75H FFFF76H Not used #34 Input capture 4/5

INT 35 FFFF70H FFFF71H FFFF72H Not used #35 Output compare 2/3Input capture 6/7

INT 36 FFFF6CH FFFF6DH FFFF6EH Not used #35 16-bit reload timer 1

INT 37 FFFF68HH FFFF69H FFFF6AH Not used #36 UART 0 receive

INT 38 FFFF64H FFFF65H FFFF66H Not used #37 UART 0 transmit

INT 39 FFFF60H FFFF61H FFFF62H Not used #38 UART 1 receive

INT 40 FFFF5CH FFFF5DH FFFF5EH Not used #39 UART 1 transmit

INT 41 FFFF58H FFFF59H FFFF5AH Not used #40 Flash memory

INT 42 FFFF54H FFFF55H FFFF56H Not used #41 Delayed interrupt

INT 43 FFFF50H FFFF51H FFFF52H Not used #42 None

: : : : : : :

INT 254 FFFC04H FFFC05H FFFC06H Not used #254 None

INT 255 FFFC00H FFFC01H FFFC02H Not used #255 None

Table 3.3-1 Interrupt Vector (Continued)

Software interrupt

instruction

Vector address L

Vector address M

Vector address H

Mode register

Interrupt No.

Hardware interrupt

50

3.4 Hardware Interrupts


In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. This function is called the hardware interrupt function.

■ Hardware Interrupts

A hardware interrupt occurs when the relevant conditions are satisfied as a result of twooperations: comparison between the interrupt request level and the value in the interrupt levelmask register (ILM) of PS in the CPU, and hardware reference to the I flag value of PS.

The CPU performs the following processing when a hardware interrupt occurs:

• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU tothe system stack.

• Sets ILM in the PS register. The currently requested interrupt level is automatically set.

• Fetches the corresponding interrupt vector value and branches to the processing indicatedby that value.

■ Structure of Hardware Interrupt

Hardware interrupts are handled by the following three sections:

❍ Internal resources

Interrupt enable and request bits: Used to control interrupt requests from resources.

❍ Interrupt controller

ICR: Assigns interrupt levels and determines the priority levels of simultaneously requestedinterrupts.

❍ CPU

I and ILM: Used to compare the requested and current interrupt levels and to identify theinterrupt enable status.

Microcode: Interrupt processing step

The status of these sections are indicated by the resource control registers for internalresources, the ICR for the interrupt controller, and the CCR value for the CPU. To use ahardware interrupt, set the three sections beforehand by using software.

The interrupt vector table referenced during interrupt processing is assigned to addressesFFFC00H to FFFFFFH in memory. These addresses are shared with software interrupts.

■ Hardware Interrupt Request during Writing to the Input-Output Area

When data is being written to the input-output area, hardware interrupt requests are notaccepted. This prevents the CPU from making operational mistakes, which could be caused ifan interrupt request were generated while data was being rewritten to the interrupt controlregisters for each source.

51


■ Multiple Interrupts

The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs whileanother interrupt is being processed, control is transferred to the higher-level interrupt after thecurrent instruction completes execution. After the higher-level interrupt terminates, the CPUreturns to processing of the previous interrupt. If an interrupt of the same or lower level occurswhile another interrupt is being processed, the new interrupt request is kept pending untiltermination of the current interrupt processing unless the ILM value or I flag is changed by aninstruction. The extended intelligent I/O service cannot be used for the activation of multipleinterrupts. During processing of the extended intelligent I/O service, all other interrupt requestsor extended intelligent I/O service requests are kept pending.

■ Register Saving onto the Stack

Figure 3.4-1 "Registers Saved on the Stack" shows the order of the registers saved in the stack.

Figure 3.4-1 Registers Saved on the Stack

Word (16 bits)

MSB LSBH

SSP (SSP value before interrupt)

AH

AL

DPR ADB

DTB PCB

PC

PS

L

SSP (SSP value after interrupt)

52


3.4.1 Hardware Interrupt Operation

An internal resource that has the hardware interrupt request function has an interrupt request flag and interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the interrupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU. The interrupt request flag is set when an event occurs that is unique to the internal resource. When the interrupt enable flag indicates "enable", the resource issues an interrupt request to the interrupt controller.

■ Hardware Interrupt Operation

When two or more interrupt requests are received at the same time, the interrupt controllercompares the interrupt levels (IL) in ICR, selects the request at the highest level (the smallest ILvalue), then reports that request to the CPU. If multiple requests are at the same level, theinterrupt controller selects the request with the lowest interrupt number. The relationshipbetween the interrupt requests and ICRs is determined by the hardware.

The CPU compares the received interrupt level and the ILM in the PS register. If the interruptlevel is smaller than the ILM value and the I bit of the PS register is set to 1, the CPU activatesthe interrupt processing microcode after the currently executing instruction is completed. TheCPU references the ISE bit of the ICR of the interrupt controller at the beginning of the interruptprocessing microcode, checks that the ISE bit is 0 (interrupt), and activates the interruptprocessing body.

The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to thememory area indicated by SSB and SSP, fetches three bytes of interrupt vector and loads themonto PC and PCB, updates the ILM of PS to a level value of the received interrupt, sets the Sflag, then performs branch processing. As a result, the interrupt processing program defined bythe user is executed next.

Figure 3.4-2 "Occurrence and Release of Hardware Interrupt" illustrates the flow from theoccurrence of a hardware interrupt until there is no interrupt request in the interrupt processingprogram.

53


Figure 3.4-2 Occurrence and Release of Hardware Interrupt

Operations (1) to (7) in Figure 3.4-2 "Occurrence and Release of Hardware Interrupt" areexplained below.

1. An interrupt cause occurs in a peripheral.

2. The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, theperipheral issues an interrupt request to the interrupt controller.

3. Upon reception of the interrupt request, the interrupt controller determines the priority levelsof simultaneously requested interrupts. Then, the interrupt controller transfers the interruptlevel of the corresponding interrupt to the CPU.

4. The CPU compares the interrupt level requested by the interrupt controller with the ILM bit ofthe processor status register.

5. If the comparison shows that the requested level is higher than the current interruptprocessing level, the I flag value of the same processor status register is checked.

6. If the check in step 5. shows that the I flag indicates interrupt enable status, the requestedlevel is written to the ILM bit. Interrupt processing is performed as soon as the currentlyexecuting instruction is completed, then control is transferred to the interrupt processingroutine.

7. When the interrupt cause of step 1. is cleared by software in the user interrupt processingroutine, the interrupt request is completed.

The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shownbelow.

Interrupt start: 24 + 6 x (Table 3.4-1 "Compensation Values for Interrupt Processing CycleCount "machine cycles)

Interrupt return: 15 + 6 x (Table 3.4-1 "Compensation Values for Interrupt Processing CycleCount " machine cycles) RETI instruction

IR

PS I ILM

AND

F 2 M C - 1 6 LX·

·····

C P U

Inte

rnal

dat

a bu

s

Register file

MicrocodeCheck Comparator

Peripheral

Enable FF

Cause FF

Leve

l com

para

tor

Inte

rrup

t lev

el IL

Interrupt

PS : Processor statusI : Interrupt enable flag in CCRILM : Interrupt level in PSIR : Instruction register

controllerPeripheral

54


Table 3.4-1 Compensation Values for Interrupt Processing Cycle Count

Address indicated by the stack pointer Cycle count compensation value

External area, 8-bit data bus +4

External area, even-numbered address +1

External area, odd-numbered address +4

Internal area, even-numbered address 0

Internal area, odd-numbered address +2

55


3.4.2 Flow of Hardware Interrupt Operation

Figure 3.4-3 "Flow of Hardware Interrupt Operation" shows the flow of hardware interrupt operation.

■ Flow of Hardware Interrupt Operation

Figure 3.4-3 Flow of Hardware Interrupt Operation

I&IF&IE=1 YESAND

ILM IL

NONO YES

ISE = 1

YES INT instruction?

NO

Execute an ordinary instruction

S 1NO Repetition of

string type instruction completed?

(fetch interrupt vector)

YES

Update PC

I : Interrupt enable flag in CCRILM : Interrupt level mask register in PSIF : Interrupt request for internal resourceIE : Interrupt enable flag for internal resourceISE : EI2OS enable flagIL : Interrupt request level for internal resourceS : Flag in CCR

Fetch the next instruction and decode

Save PS, PC, PCB, DTB, ADB, DPR, and A to the SSP stack, then set ILM = IL

Extended intelligent I/O service processing

Save PS, PC, PCB, DTB, ADB, DPR, and A to the SSP stack, then set I = 0 and ILM = IL

56

3.5 Software Interrupts

3.5 Software Interrupts

The software interrupt function returns control from the program being executed by the CPU to the user-defined interrupt processing program in response to execution of a special instruction.

■ Software Interrupts

A software interrupt is always activated when the software interrupt instruction is executed.

The CPU performs the following processing when a software interrupt occurs:

• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU tothe system stack.

• Sets I in the PS register. Interrupts are automatically disabled.

• Fetches the corresponding interrupt vector value, then branches to the processing indicatedby that value.

A software interrupt request issued by the INT instruction has no interrupt request or enableflag. A software interrupt request is always issued by executing the INT instruction.

The INT instruction does not have an interrupt level. Therefore, the INT instruction does notupdate ILM. The INT instruction clears the I flag to suspend subsequent interrupt requests.

■ Structure of Software Interrupts

Software interrupts are handled within the CPU:

CPU.....Microcode: Interrupt processing step

As shown in Table 3.3-1 "Interrupt Vector", software interrupts share the same interrupt vectorarea with hardware interrupts. For example, interrupt request number INT 15 is used forexternal interrupt #0 (hardware interrupt) as well as for INT #15 (software interrupt). Therefore,external interrupts #0 and INT #15 call the same interrupt processing routine.

■ Software Interrupt Operation

When the CPU fetches and executes the software interrupt instruction, the software interruptprocessing microcode is activated. The software interrupt processing microcode saves 12 bytes(PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. Themicrocode then fetches three bytes of interrupt vector and loads them onto PC and PCB, resetsthe I flag, and sets the S flag. Then, the microcode performs branch processing. As a result, theinterrupt processing program defined by the user application program is executed next.

Figure 3.5-1 "Occurrence and Release of Software Interrupt" illustrates the flow from theoccurrence of a software interrupt until there is no interrupt request in the interrupt processingprogram.

57


Figure 3.5-1 Occurrence and Release of Software Interrupt

Figure 3.5-1 "Occurrence and Release of Software Interrupt" illustrates the flow from theoccurrence of a software interrupt until there is no interrupt request in the interrupt processingprogram.

1. The software interrupt instruction is executed.

2. Special CPU registers in the register file are saved according to the microcodecorresponding to the software interrupt instruction.

3. The interrupt processing is completed with the RETI instruction in the user interruptprocessing routine.

■ Note on Software Interrupt

When the program bank register (PCB) is FFH, the CALLV instruction vector area overlaps thetable of the INT #vct8 instruction. When designing software, ensure that the CALLV instructiondoes not use the same address as that of the #vct8 instruction.

RAM

IR

PS I S

F 2 M C - 1 6 LX• C P U

➀

➁

PS : Processor statusI : Interrupt enable flag in CCRILM : IInterrupt level in PSIR : Instruction registerB unit : Bus interface unit

Inte

rnal

dat

a bu

s

Save

Register file

MicrocodeQueue Fetch

Instruction bus

B unit

58

3.6 Extended Intelligent I/O Service (EI2OS)


The EI2OS function automatically transfers data between input and output and memory. An interrupt processing program was conventionally used for such

processing, but EI2OS enables data transfer to be performed like DMA (direct memory access).Note:

The use of EI2OS is not possible with the REALOS real time operating system.

■ Extended Intelligent I/O Service (EI2OS)

The extended intelligent I/O service (EI2OS) has the following advantages over the conventionalinterrupt processing method:

• The program size can be small because it is not necessary to write a transfer program.

• No internal register is used for transfer, eliminating the need for register saving andincreasing the transfer speed.

• Transfer can be terminated from I/O, preventing unnecessary data from being transferred.

• Incrementing, decrementing, or no update can be selected for the buffer address.

• Incrementing, decrementing, or no update can be selected for the I/O register address (if thebuffer address is updated).

At the end of EI2OS, processing automatically branches to an interrupt processing routine afterthe end condition is set. Thus, the user can identify the end condition.

Figure 3.6-1 "Outline of Extended Intelligent I/O Service" provides an overview of EI2OS.

59


Figure 3.6-1 Outline of Extended Intelligent I/O Service

Note:

The area that can be specified by IOA is between 000000H and 00FFFFH.

The area that can be specified by BAP is between 000000H and FFFFFFH.

The maximum transfer count that can be specified by DTC is 65,536.

■ Structure

EI2OS is handled by the following four sections:

Internal resources

Interrupt enable and request bits: Used to control interrupt requests from resources.


ICR: Assigns interrupt levels, determines the priority levels of simultaneously requested

interrupts, and selects the EI2OS operation.

CPU

I and ILM: Used to compare the requested and current interrupt levels and to identify theinterrupt enable status

Microcode: EI2OS processing step

RAM

Descriptor: Describes the EI2OS transfer information.

by

by BAP

by IOA

ISDby ICS

CPU

Memory space

I/O register

Buffer

Peripheral

Interrupt request

Interrupt control register


I/O register

I/O requests transfer.The interrupt controller selects thedescriptor.The transfer source and destinationare read from the descriptor.Data is transferred between I/O andmemory.The interrupt source is automatically cleared.

DCT

60


3.6.1 Interrupt Control Register (ICR)

The interrupt control register, located in the interrupt controller, handles the interrupts corresponding to all I/Os that have an interrupt function. The interrupt control register has the following three functions:• Setting an interrupt level for each related peripheral• Selecting whether to use an ordinary interrupt or extended intelligent I/O service for

a related peripheral• Selecting the extended intelligent I/O service channelDo not access an interrupt control register with a read-modify-write instruction, since an erroneous operation will result.

■ Interrupt Control Register (ICR)

Figure 3.6-2 "Interrupt Control Register (ICR)" shows the bit configuration of the interrupt controlregister.

Figure 3.6-2 Interrupt Control Register (ICR)

Note:

ICS3 to ICS0 are valid only when EI2OS is activated. Set ISE to 1 to activate EI2OS and to 0

not to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0.

For ICS3 and ICS2, 1 is always read.

ICS1 and ICS0 can only be written to. S1 and S0 can only be read.

[Bits 15 to 12 and 7 to 4]: ICS3 to ICS0

The ICS3 to ICS0 bits specify the EI2OS channel.

They are write-only bits. The values set for these bits determine the extended intelligent I/Oservice descriptor addresses in memory. The ICS bits are initialized by a reset.

Table 3.6-1 "ICS Bits, Channel Numbers, and Descriptor Addresses" lists thecorrespondence between ICS bits, channel numbers, and descriptor addresses.

Interrupt control register (ICR)15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0

Address B0H to BFH ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 During writing

Read/write (W) (W) (W) (W) (W) (W) (W) (W)Initial value (0) (0) (0) (0) (0) (1) (1) (1)

15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0

S1 S0 ISE IL2 IL1 IL0 During reading

(-) (-) (R) (R) (R) (R) (R) (R)Initial value (-) (-) (0) (0) (0) (1) (1) (1)Read/write

Address B0H to BFH

Bit No.

Bit No.

61


[Bits 13 and 12 and bits 5 and 4]: S0 and S1

The S0 and S1 bits indicate the EI2OS termination status.

They are read-only bits. When the values in these bits are checked at EI2OS termination, atermination condition can be identified. These bits are initialized to 00 by a reset.

Table 3.6-2 "S Bits and Termination Conditions" shows the relationship between the S bitsand termination conditions.

Table 3.6-1 ICS Bits, Channel Numbers, and Descriptor Addresses

ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address

0 0 0 0 0 000100H

0 0 0 1 1 000108H

0 0 1 0 2 000110H

0 0 1 1 3 000118H

0 1 0 0 4 000120H

0 1 0 1 5 000128H

0 1 1 0 6 000130H

0 1 1 1 7 000138H

1 0 0 0 8 000140H

1 0 0 1 9 000148H

1 0 1 0 10 000150H

1 0 1 1 11 000158H

1 1 0 0 12 000160H

1 1 0 1 13 000168H

1 1 1 0 14 000170H

1 1 1 1 15 000178H

Table 3.6-2 S Bits and Termination Conditions

S1 S0 Termination condition

0 0 EI2OS running or not activated

0 1 Stopped status due to count termination

1 0 Reserved

1 1 Stopped status due to a request from the internal resource

62


[Bits 11 and 3]: ISE

The ISE bit enables EI2OS. This bit can be read and written to.

If this bit is 1 when an interrupt request is generated, EI2OS is activated. If this bit is 0 when

an interrupt request is generated, the interrupt sequence is activated. When the EI2OStermination condition is met (when the S1 and S0 bits are not 00), the ISE bit is cleared to 0.

If the corresponding peripheral function does not have the EI2OS function, the ISE bit mustbe set to 0 by software. The ISE bit is initialized to 0 by a reset.

[Bits 10 to 8 and bits 2 to 0]: IL0, IL1, and IL2

The IL0, IL1, and IL2 bits set the interrupt level.

These bits specify the interrupt level of the corresponding internal resources. These bits canbe read and written to. These bits are initialized to level 7 (no interrupt) by a reset. Table3.6-3 "Interrupt Level Setting Bits and Interrupt Levels" shows the relationship between theinterrupt level setting bits and interrupt levels.

Table 3.6-3 Interrupt Level Setting Bits and Interrupt Levels

ILM2 ILM1 ILM0 Interrupt level

0 0 0 0 (highest interrupt)

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6 (lowest interrupt)

1 1 1 7 (no interrupt)

63


3.6.2 Extended Intelligent I/O Service Descriptor (ISD)

The extended intelligent I/O service descriptor exists between 000100H and 00017FH in

internal RAM, and consists of the following items:• Data transfer control data• Status data• Buffer address pointer

■ Extended Intelligent I/O Service Descriptor (ISD)

Figure 3.6-3 "Extended Intelligent I/O Service Descriptor Configuration" shows the configurationof the extended intelligent I/O service descriptor.

Figure 3.6-3 Extended Intelligent I/O Service Descriptor Configuration

■ Data Counter (DCT)

This is a 16-bit register that works as a counter corresponding to the number of data items

transferred. This counter is decremented by one before data transfer. EI2OS is terminated whenthis counter reaches 0. Figure 3.6-4 "Data Counter Configuration" is a diagram of the datacounter configuration.

Figure 3.6-4 Data Counter Configuration

■ I/O Register Address Pointer (IOA)

This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/Oregister used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/Obetween addresses 000000H and 00FFFFH can be specified. Figure 3.6-5 "I/O RegisterAddress Pointer Configuration" is a diagram of the IOA configuration.

High-order 8 bits of data counter (DCTH)

Low-order 8 bits of data counter (DCTL)

High-order 8 bits of I/O address pointer (IOAH)

Low-order 8 bits of I/O address pointer (IOAL)

EI2OS status (ISCS)

High-order 8 bits of buffer address pointer (BAPH)

Medium-order 8 bits of buffer address pointer (BAPM)

Low-order 8 bits of buffer address pointer (BAPL)

H

LISD start address

000100 H + 8 × ICS

Data counter (upper) 15 14 13 12 11 10 9 8

B15 B14 B13 B12 B11 B10 B09 B08 DCTH

Initial value (X) (X) (X) (X) (X) (X) (X) (X)

7 6 5 4 3 2 1 0

B07 B06 B05 B04 B03 B02 B01 B00 DCTL


Data counter (lower) Bit No.

Bit No.

64


Figure 3.6-5 I/O Register Address Pointer Configuration

EI2OS status register (ISCS)

The EI2OS status register (ISCS) is eight bits, and indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer addresspointer and I/O register address pointer. This register also indicates whether the bufferaddress pointer or I/O register address pointer is updated or fixed. Figure 3.6-6 "ISCSConfiguration" shows the ISCS configuration.

Figure 3.6-6 ISCS Configuration

* Always write 0 to bits 7 to 5 of ISCS.

[Bit 4]: IF

The IF bit specifies whether the I/O register address pointer is updated or fixed.

[Bit 3]: BW

The BW bit specifies the transfer data length.

[Bit 2]: BF

The BF bit specifies whether the buffer address pointer is updated or fixed.

I/O address pointer (upper) 15 14 13 12 11 10 9 8

A15 A14 A13 A12 A11 A10 A09 A08 IOAH


I/O address pointer (lower) 7 6 5 4 3 2 1 0

A07 A06 A05 A04 A03 A02 A01 A00 IOAL


Bit No.

Bit No.

BW BF DIR SEIF

7 6 5 4 3 2 1 0

ReservedReserved ReservedISCS

(Undefined when reset)

(X) (X) (X) (X) (X) (X) (X) (X)

Bit No.

Initial value

Table 3.6-4 I/O Register Address Pointer Update/Fixed Selection Bit (IF)

IF Function

0 After data transfer, the I/O register address pointer is updated.

1 After data transfer, the I/O register address pointer is not updated.

Table 3.6-5

BW Function

0 Byte

1 Word

65


Note:

Only the lower 16 bits of the buffer address pointer are updated. Only incrementing isallowed.

[Bit 1]: DIR

The DIR bit specifies the data transfer direction.

[Bit 0]: SE

The SE bit controls the termination of the extended intelligent I/O service based on resourcerequests.

■ Buffer Address Pointer (BAP)

This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each

EI2OS channel. Therefore, each EI2OS channel can be used for transfer with anywhere in the16-Mbyte space.

Note:

If the BF bit of ISCS is set to "0" (update enabled), only the low-order 16 bits of BAP changesand BAPH does not change.

Table 3.6-6 Buffer Address Pointer Update/Fixed Selection Bit (BF)

BF Function

0 After data transfer, the buffer address pointer is updated.

1 After data transfer, the buffer address pointer is not updated.

Table 3.6-7 Data Transfer Direction Specification Bit (DIR)

DIR Setting

0 I/O -> buffer

1 Buffer -> I/O

Table 3.6-8 EI2OS Termination Control Bit

SE Setting

0 Not terminated by a resource request.

1 Terminated by a resource request.

66


3.6.3 Operation of Extended Intelligent I/O Service (EI2OS)

Figure 3.6-7 "Operation Flow of the Extended Intelligent I/O Service (EI2OS)" shows the

operation flow of the extended intelligent I/O service (EI2OS). Figure 3.6-8 "Procedure

for Using the Extended Intelligent I/O Service (EI2OS)" shows the procedure for using

the extended intelligent I/O service (EI2OS).

■ Operation Flow of the Extended Intelligent I/O Service (EI2OS)

Figure 3.6-7 Operation Flow of the Extended Intelligent I/O Service (EI2OS)

Data indicated by IOA (Data transfer)Memory indicated by BAP

-1

Update value by BW

Update value by BW

NO

NO NO

NO

NO

NO

NO

YES

YES

YES

YES

YES

YES

YES EI OS termination processing

Interrupt request generated

by internal resource

Termination request from

resource?

ISE 1

Read ISD/ISCS

Clear interrupt request from internal resource

Return to CPU operation

Decrement DCT

Set S1 and S0 to 00

DIR 1

IF 0

BF 0

DCT 00

Data indicated by BAP (Data transfer)Memory indicated by BAP

Interrupt sequence

Clear ISE to 0

Interrupt sequence

Update BAP

Update IOA

Set S1 and S0 to 11Set S1 and S0 to 01

SE 1

ISD : IEI2OS descriptor ISCS : EI2OS status registerIF : IOA update/fixed selection bit in the

EI2OS status register (ISCS)BW : Transfer data length specification

bit in the EI2OS status register (ISCS)BF : BAP update/fixed selection bit in the

EI2OS status register (ISCS)DIR : Data transfer direction specification

bit in the EI2OS status register (ISCS)SE : EI2OS termination control bit in the

EI2OS status register (ISCS)

DCT : Data counterIOA : I/O register address pointerBAP : Buffer address pointerISE : EI2OS enable bit in the interrupt control register (ICR)S1,S0 : EI2OS status in the interrupt control register (ICR)

2

67


Figure 3.6-8 Procedure for Using the Extended Intelligent I/O Service (EI2OS)

Start

Set the system stack area

Set the EI2OS descriptor

Initialize the internal resource

Set the interrupt control register (ICR)

Set the internal resource to start operation. Set the interrupt enable bit (ICR)

Set the ILM and I in the PS

Execute the user program

Set the extended intelligent I/O service again (switch channels)

Process data in the buffer

RETI

Transfer data

Decide whether to end counting or to branch to an interrupt by termination request from resource

NO

YES

(Interrupt request)and ISE 1

(Branch to interrupt vector)

ISE: EI2OS enable bit in the interrupt control register (ICR)S1, S0: EI2OS status of the interrupt control register (ICR)

S1, S0 "01"orS1, S0 "11"

S1, S0 "00"

Software processing Hardware processing

Initi

aliz

atio

n

68


3.6.4 Execution Time of the Extended Intelligent I/O Service (EI2OS)

The time required for executing the extended intelligent I/O service (EI2OS) changes in the following cases:• When data transfer continues (when the stop condition is not satisfied)• When a stop request is issued from a resource• When the counting is completed

■ Execution Time of the Extended Intelligent I/O Service (EI2OS)

❍ When data transfer continues (when the stop condition is not satisfied)

(Table 3.6-9 "Execution Time When the Extended EI2OS Continues" + Table 3.6-10 "Data

Transfer Compensation Values for Extended EI2OS Execution Time") machine cycles

❍ When a stop request is issued from a resource

(36 + 6 x Table 3.4-1 "Compensation Values for Interrupt Processing Cycle Count") machinecycles

❍ When the counting is completed

(Table 3.6-9 "Execution Time When the Extended EI2OS Continues" + Table 3.6-10 "Data

Transfer Compensation Values for Extended EI2OS Execution Time" + (21 + 6 x Table 3.4-1"Compensation Values for Interrupt Processing Cycle Count")) machine cycles

Table 3.6-9 Execution Time When the Extended EI2OS Continues

ISCS SE bit Set to 0 Set to 1

I/O address pointer Fixed Updated Fixed Updated

Buffer address pointer Fixed 32 34 33 35

Updated 34 36 35 37

69


Table 3.6-10 Data Transfer Compensation Values for Extended EI2OS Execution Time

I/O address pointer Internal access External access

B/E O B/E 8/O

Buffer address pointer

Internal access

B/E 0 +2 +1 +4

O +2 +4 +3 +6

External access

B/E +1 +3 +2 +5

8/O +4 +6 +5 +8

B : Byte data transfer8 : 8-bit external bus word transferE : Even address word transferO : Odd address word transfer

70

3.7 Exception Due to Execution of an Undefined Instruction

3.7 Exception Due to Execution of an Undefined Instruction

In the F2MC-16LX, an exception occurs when an undefined instruction is executed and exception processing is performed.Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as the result of an unexpected operation. It is recommended that exception processing be used only for debugging or for activating emergency recovery software.

■ Exception Due to Execution of an Undefined Instruction

The F2MC-16LX handles all codes that are not defined in the instruction map as undefinedinstructions. When an undefined instruction is executed, processing equivalent to the INT 10software interrupt instruction is performed.

Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved onto the systemstack, and processing branches to the routine indicated by the interrupt number 10 vector. Inaddition, the I flag is cleared and the S flag is set. The PC value saved on the stack is theaddress at which the undefined instruction is stored. Although processing can be restored withthe RETI instruction, this is pointless because the same exception occurs again.

71


72

CHAPTER 4 CLOCK AND RESET

This chapter explains the functions and operations of clocks and resets.

4.1 "Clock Generator"

4.2 "Reset Cause Occurrence"

4.3 "Reset Causes"

73


4.1 Clock Generator

The clock generator controls internal clock operation, including such functions as sleep, timer, stop, and PLL multiplication. This internal clock is called the machine clock, and one cycle of the machine clock is called a machine cycle. A clock based on the source oscillation is called the main clock, and a clock based on the internal VCO oscillation is called the PLL clock.

■ Notes on Clock Generator

When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 5MHz. When an external clock source is used, its frequency can be between 3 MHz and 16MHz.The highest operating frequency for the CPU and peripheral resource circuits is 16 MHz,however. Normal operation is not guaranteed if a multiplication factor resulting in a higherfrequency than 16 MHz is specified. For example, if the external clock frequency is 16 MHz,only 1 can be specified as the multiplication factor.

The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHzmust not be specified.

Figure 4.1-1 Clock Generator Circuit Block Diagram

S Q

R

S Q

R

S Q

R

XLX0

1/2 1/2048 1/4 1/4 1/8

1 2 3 4

ResetInterrupt

Transition to stop mode

Transition to timer or sleep mode

Selecting the oscillation stabilization wait time

Selecting the machine clock

Machine clock

PLL multiplication

Time base timer

Selecting the watch-dog

Watch-dogtimer

Watch-dog reset

HST

timer interval

74

4.2 Reset Cause Occurrence


When a reset cause occurs, F2MC-16LX terminates the currently executing processing and waits for reset release.

■ Reset Cause Occurrence

A reset is caused by the following factors:

• Power-on reset

• Hardware standby release

• Watch-dog timer overflow

• External reset request via RST pin

• Reset request by software

Upon exit from the stop mode or after a power-on reset, the oscillation stabilization interval isinserted before operation is restarted.

If a reset cause is generated, the F2MC-16LX immediately stops the current operation beingexecuted and enters reset release standby mode.

The machine clock and watch-dog function are initialized based on the reset causes.

The content of the watch-dog timer control register will change according to the reset cause.Thus, the cause of the previous reset can be known.

Note:

In a mode other than stop mode, external reset input is internally sampled by the clockcircuit. When external clock signal supply is used, reset signal input is not received.

If an external bus is being used, the address generated by the device is undefined when areset cause occurs. The signals to be used for external bus access, including RD and WR,become inactive.

75


■ Operation after Reset Release

When a reset cause is removed, the F2MC-16LX immediately outputs the address in which thereset vector is stored, then fetches the reset vector and mode data. The reset vector and modedata are assigned to the four bytes between FFFFDCH and FFFFDFH. After reset is released,the reset vector and mode data are transferred to the registers by the hardware as described inFigure 4.2-1 "Source and Destination of Reset Vector and Mode Data".

Use the mode pin to specify whether to read the reset vector and mode data from internal ROM

or from external memory. When the mode pin is set to external vector mode, the F2MC-16LX

reads the reset vector and mode data from external memory. When using the F2MC-16LX insingle chip mode or internal ROM external bus mode, Fujitsu recommends specifying internalvector mode.

The bus mode after the reset vector and mode data are read is specified by the mode data.

Figure 4.2-1 Source and Destination of Reset Vector and Mode Data

Note:

The mode register in the above diagram is not defined immediately after a reset. Storemode data in the memory space so that the value is written to this area.

PCB

PC

FFFFDFH

FFFFDEH

FFFFDDH

FFFFDCH

Memory space

Mode data

Reset vector bits 23 to 16



F2MC-16LX CPU

Register

Reset sequence

Mode

Micro ROM

76


■ Registers not Initialized by Reset Input

This microcontroller contains registers initialized only by a power-on reset.

Table 4.2-1 "Registers not Initialized by Reset Input" lists registers not initialized by each resetcause.

In particular, handle the MCS bit carefully because it sets the machine clock. For example, ifpower-on does not satisfy the power-on reset specification, no power-on reset occurs. For thisreason, the internal operating frequency may become outside the valid operation range,because MCS is not initialized, and the microcontroller may not operate normally.

If the CPU crashes for some reason and MCS, CS1, or CS0 is rewritten, the internal operatingfrequency may also become outside the valid operation range. The microcontroller may not beable to recover normally from this status by RST input only (however, if the internal watchdogstate occurs, MCS is initialized and the microcontroller operates normally).

When either of the above cases occurs, use of HST plus RST (connecting HST and RST with ajumper) is recommended.

Table 4.2-2 "Registers not Initialized by Reset Input" lists registers that are not initialized byreset input using HST plus RST. Note that the operation status after the reset is released differsdepending on the reset input type, HST plus RST reset input, or only RST input, as listed inTable 4.2-2 "Registers not Initialized by Reset Input".

Table 4.2-1 Registers not Initialized by Reset Input

Type of resetCKSCR WTC LPMCR

WS1 WS0 MCS CS1 CS0 WDCS CG1 CG0

Software reset(Only RST is used.)

X X X X X X X X

Watchdog reset X X O X X X O O

Power-on reset O O O O O O O O

Hardware standby

Main mode

X X O X X X O O

Sub mode

O O O O O O O O

WS1 and WS0: Set the oscillation stabilization time for the main clock. MCS: Specifies the machine clock (0 = PLL clock or 1 = main clock).CS1 and CS0: Set the multiplication factor for the PLL clock.WDCS: Specifies the input clock source for the watchdog timer (0 = watch timer or 1 = timebase timer).O: InitializedX: Not initialized

77


Table 4.2-2 Registers not Initialized by Reset Input

Type of resetCKSCR WTC LPMCR

WS1 WS0 WDCS CS1 CS0 WDCS CG1 CG0

HST + RST

Main mode

X X X X X X O O

Sub mode (*1) O O O O O O O O

Y: InitializedN: Not initialized*1: Including the sub mode transition period.

78


Figure 4.2-2 Operation Transition by Reset Input

(RST, HST+RST) Reset input

A. Oscillation status

Status

Status

Only RSTused(HST ="H")

Oscillating

Oscillating

Oscillating

OscillatingHST + RSTused

HST plus RST used

Stopped

Oscillating Stopped

Main

Sub

Oscillating

Main

Sub

Main

Sub

Waiting for mainclock oscillation

stabilization

Waiting for mainclock oscillation

stabilization

Main clock operation enabled

Main clock operation enabled

Oscillation stabilizationtime set before reset input

Oscillation stabilization timeof 218main clock cycles

B. Execution timing (L: Stop, H: Start)

[Operation Transition by Reset Input]

Main clock mode

Subclock mode

Main mode

Sub mode

Waiting for subclockoscillation stabilization

Subclock operationenabled

Waiting for subclockoscillation stabilization

Subclock operationenabled

216 cycles of subclock oscillation (32 kHz) (about 2 s)

216 cycles of subclock oscillation (32 kHz) (about 2 s)

Vcc (power supply)

Only RST used (HST ="H")

Power-on reset

2 main clock cycles whensubclock mode requestedLine disabling period setby SCS bits

2 main clock cycles whensubclock mode requestedWrite disabling period set by SCS bits

Power-onreset

79


4.3 Reset Causes

Table 4.3-1 "Reset Causes" lists the five reset causes. The machine clock and watch-dog function are initialized differently for each reset cause.The reset cause register indicates the reset cause.

■ Reset Causes

Each reset cause has a corresponding flip-flop. The contents of the flip-flop can be obtained byreading the watch-dog timer control register. If the reset cause must be identified after the resetis released, be sure that the value read from the watch-dog timer control register is processedby software and processing branches to an appropriate application program.

Table 4.3-1 Reset Causes

Reset CauseMachine clock

Watch-dog timer

Oscillation stabilization

waitAt sub-clock At PLL clock

Power-onWhen the power is

turned onMain clock * Main clock * Stop Yes

Hardware standby

"L" level input to HST pin Main clock * Main clock * Stop Yes

Watch-dog timer

Watch-dog timer overflow

Main clock * Main clock * Stop Yes

External pin "L" level input to RST pinMain clock * or

PLL clock PLL clockPrevious status

maintainedNo

Software0 written to the RST bit in

the LPMCR registerMain clock * or

PLL clock PLL clockPrevious status

maintainedNo

*: fOSC/2 (fOSC: the source oscillation)Notes:

In stop mode, input of the external pin reset signal allows an oscillation stabilization wait time to be set.

The oscillation stabilization time for a power-on reset and hardware standby is fixed to 218 cycles of source oscillation. For other types of reset, the oscillation stabilization wait time is determined by WS1 and WS0 of the clock selection register.

80

4.3 Reset Causes

Figure 4.3-1 Reset Cause bit Block Diagram

When there are multiple reset causes, the corresponding reset cause bits in the watch-dog timercontrol register are set. Therefore, if an external reset request and a watch-dog reset occur atthe same time, both the ERST and WRST bits are set to 1.

A power-on reset is an exception; while the PONR bit is 1, the values of other bits do notindicate the correct reset causes. Therefore, design software so that the other reset cause bitvalues are ignored while the PONR bit is set to 1.

(An asterisk (*) in the table means that the previous value is maintained.)

The reset cause bits are only cleared by reading the watch-dog timer control register. The resetcause bit that corresponds to the reset cause that has already been generated remains 1 even ifanother reset cause is generated.

See Chapter 9 "TIMEBASE TIMER", Chapter 10 "WATCH-DOG TIMER" and Chapter 11"WATCH TIMER" for details about the configuration and reset cause bits of the watch-dog timercontrol register.

R R RF / FF / F F / F F / F F / F

HST=L RST=L

S R S S SSR

HST pin RST pin

Without periodic clearRST bit setPower on

Power-on Hardware standby External reset Watch-dog timer LPMCR. RST bit

DelayWTC register

WTC register read

Internal data bus

circuit

write detection circuitdetection circuit release detection

circuitrequest detection

circuit reset detection circuit

Table 4.3-2 Reset Cause Bits

Reset cause PONR STBR WRST ERST SRST

Power-on 1 - - - -

Hardware standby * 1 * * *

Watch-dog timer * * 1 * *

External pin * * * 1 *

RST bit * * * * 1

81


82

CHAPTER 5 LOW-POWER CONTROL CIRCUIT

This chapter explains the functions and operation of the low-power control circuit.

5.1 "Outline of Low-Power Control Circuit"

5.2 "Block Diagram of Low-Power Control Circuit"

5.3 "Low-Power Control Circuit Registers"

5.4 "Status Transition for Clock Selection"

83


5.1 Outline of Low-Power Control Circuit

The low-power control circuit is mainly used in low-power consumption mode. The intermittent CPU operation function and oscillation stabilization wait time can be set by setting register bits.In the overall block diagram, the low-power control circuit is a part of the clock control circuit (see Section 1.3 "Block Diagram").

■ Operation Modes of Low-power Control Circuit

The MB90435 series supports the following operation modes: PLL clock mode, PLL sleepmode, PLL watch mode, pseudo watch mode, main clock mode, main sleep mode, main watchmode, main stop mode, subclock mode, subclock sleep mode, subclock watch mode, subclockstop mode, and hardware standby mode. Operation modes other than PLL clock mode areclassified as low-power modes.

■ Intermittent CPU Operation Function

The intermittent CPU operation function pauses the clock supplied to the CPU for a certainperiod to delay the activation of the internal bus cycle when an internal register, internal memory(ROM, RAM, I/O, or resource memory), or external bus is accessed. The CPU execution speedis decreased while a high-speed clock is supplied to internal resources, enabling processingwith less power consumed. The CG1 and CG0 bits of the low-power consumption mode controlregister (LPMCP) are used to select the cycle count for pausing the clock to be supplied to theCPU.

The external bus operation is performed by using the same clock signal as that used forperipheral resources.

The instruction execution time using the intermittent CPU operation function can be obtained byadding a compensation value to the ordinary execution time. The compensation value isobtained by multiplying the number of accesses to a register, internal memory, or internalresource by the cycle count for pausing.

■ Main Clock Oscillation Stabilization Wait Time

The WS1 and WS0 bits of the clock selection register (CKSCR) are used to select the mainclock oscillation stabilization wait time when stop mode is released. Select the oscillationstabilization wait time according to the type and characteristics of the oscillation circuit andoscillation device to be connected to X0 and X1 pins.

Reset signals other than power-on reset and hardware standby do not initialize these bits. Afterpower-on reset or hardware standby release is generated, these bits are initialized to 11. In that

case, the main clock oscillation stabilization wait time is about 218 counts of the sourceoscillation.

84

5.1 Outline of Low-Power Control Circuit

■ Switching between Machine Clocks

❍ Switching between main clock and PLL clock

Data is written to the MCS bit of the clock selection register (CKSCR) to switch between themain clock and PLL clock.

When the MCS bit is changed from 1 to 0, the PLL clock takes over from the main clock after

the PLL clock oscillation stabilization wait time (212 machine clock cycles).

When the MCS bit is changed from 0 to 1, the main clock takes over from the PLL clock the nexttime the edges of the PLL clock and main clock signals match (after 1 to 8 PLL clock cycles).

Writing to the MCS bit does not immediately change the machine clock. To manipulate aresource that depends on the machine clock, always reference the MCM bit beforehand tocheck that the machine clock has been switched.

❍ Switching between main clock and subclock

In the two clocks system parts, data is written to the SCS bit of the clock selection register(CKSCR) to switch between the main clock and subclock.

If the SCS bit is changed from 1 to 0, the operation is switched from the main clock to subclockwhen the next edge of the subclock signal is detected.

If the SCS bit is changed from 0 to 1, the operation is switched from the subclock to the mainclock after the main clock oscillation stabilization wait time.

Writing to the SCS bit does not immediately change the machine clock.

Manipulate a resource after the machine clock operation is checked.

However, subclock can not be used in the one clock system parts.

Note:

When subclock mode is returned to main clock mode using an external reset pin (RST pin),input level "L" for at least 2 machine cycles of the subclock.

❍ Initializing the machine clock

The MCS bit and SCS bit are not initialized by a reset using an external pin or RST bit. Thesebits are initialized to 1 by any other reset.

Note:

When tune on the power or hardware standby mode or stop mode is released, the subclockoscillation stabilization time (about 2 seconds) is generated. In the meantime, whenswitching from the main clock mode to the subclock mode, the oscillation stabilization time isgenerated.

In attempting to switch the clock mode, do not attempt to switch to another clock mode orlow-power consumption mode until the first switching is completed. The MCM and SCM bitsof the clock selection register (CKSCR) indicate that switching is completed.

■ PLL Clock Multiplication Function

The CS1 and CS0 bits are used to set the multiplication factor of the PLL clock to 2, 4, 6, and 8.This clock is divided by two and used as a machine clock signal.

85


5.2 Block Diagram of Low-Power Control Circuit

This section contains a block diagram of the low-power control circuit.

■ Block Diagram of Low-Power Control Circuit

Figure 5.2-1 Block Diagram of Low-Power Control Circuit and Clock Generator

CKSCR Main clock (OSC oscillation)

MCMPLL multiplication circuit

MCS 1 2 3 4CPU clock generation

CPU clockCKSCR

CS1 CPU

CS0 CPU clock selector 0/9/17/33 intermittent cycle selection

LPMCR

CG1

Intermittent CPU operation functionCycle count selection circuitCG0

LPMCR Peripheral clock generation

Peripheral clock

SLP

STP

RST ReleaseHST activation

HST pin

Interrupt request or RST

CKSCROscillation stabilization wait time selector

210Clock input

WS1 213

215 Timebase timerWS0 217 *1

212 214 216 219

LPMCR

SPL Pin high-impedance control circuit Pin HI-Z

LPMCR

*1: 218 at power-on

RST pinInternal reset generation circuit

RST Internal RST

To watch-dog timer

WDGRST

Subclock switch control

SCM

SCS

CKSCR

1/2 1/4

1/2

1/4 Subclock (OSC oscillation)

TMD

SCM SLEEP

MSTP

STOP

Main clock OSC stop

Subclock OSC stop

Self-refresh control circuitSSR Self refresh

Inte

rnal

dat

a bu

s

Standby control circuit

Dividing by 2

Dividing by 4

1/2

86

5.3 Low-Power Control Circuit Registers


A low-power control circuit has the following two registers:• Low-power mode control register • Clock selection register

■ Low-Power Mode Control Register

Figure 5.3-1 Low-Power Control Circuit Registers

Low-Power Mode Control Register

7 6 5 4 3 2 1 0

Address: 0000A0H STP SLP SPL RST TMD CG1 CG0 SSR LPMCR

(W) (W) (R/W) (W) (W) (R/W) (R/W) (R/W)Initial value (0) (0) (0) (1) (1) (0) (0) (0)Read/write

Bit No.

Clock selection register 15 14 13 12 11 10 9 8

Address:0000A1H SCM MCM WS1 WS0 SCS MCS CS1 CS0 CKSCR

(R) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value (1) (1) (1) (1) (1) (1) (0) (0)Read/write

Bit No.

87


5.3.1 Low-Power Mode Control Register (LPMCR)

This section explains the configuration and bit functions of the low-power mode control register (LPMCR).

■ Low-Power Mode Control Register (LPMCR)

Figure 5.3-2 Low-Power Mode control Register (LPMCR)

[bit 7] STP

Writing 1 to this bit starts pseudo watch mode (CKSCR. MCS=0 and SCS=1) or stop mode(CKSCR. MCS=1 or SCS=0). Writing 0 performs no operation. This bit is cleared to 0 by areset, watch mode release, or stop mode release. This is a write-only bit. The value readfrom this bit is always 0.

[bit 6] SLP

Writing 1 to this bit starts sleep mode. Writing 0 performs no operation. This bit is cleared to0 by a reset, sleep mode release, or stop mode release.

Writing 1 to the STP and SLP bits simultaneously starts watch mode or pseudo watch mode.This is a write-only bit. The value read from this bit is always 0.

[bit 5] SPL

When 0 is written to this bit, the external pin level in timer, pseudo timer, or stop mode ismaintained. When 1 is written to this bit, the external pin in timer, pseudo timer, or stopmode is set to high impedance. This bit is cleared to 0 by a reset.

[bit 4] RST

Writing "0" to this bit generates internal reset signals for three machine cycles. Writing "1"performs no operation. "1" is always read from this bit.

[Bit 3] TMD

Two clocks system:

Writing 0 to this bit starts watch mode. Writing 1 performs no operation. This bit is clearedto 1 by a reset, watch mode release, or stop mode release. This is a write-only bit. Thevalue read from this bit is always 1.

One clock system:

Always write "1".

Low Power Module Control Register (LPMCR)

7 6 5 4 3 2 1 0

Address 0000A0H STP SLP SPL RST TMD CG1 CG0 Reserved LPMCR

(W) (W) (R/W) (W) (W) (R/W) (R/W) (-)Initial value (0) (0) (0) (1) (1) (0) (0) (0)Read/write

Bit No.

88


[bits 2 and 1] CG1 and CG0

These bits are used to set the clock pause cycle count during intermittent CPU operation.

These bits are initialized to "00" upon a reset by power-on, hardware standby, or watch-dog.These bits are not initialized by any other type of reset.

Table 5.3-1 lists the CG bit setting.

[Bit 0] Reserved

This is a reserved bit. Always write "0".

Table 5.3-1 CG bit setting.

CG1 CG0 CPU clock pause cycle count

0 0 0 cycle (CPU clock = Resource clock)

0 1 9 cycles (CPU clock: Resource clock = 1:3 to 4 approx.)



89


■ Access to the Low-Power Mode Control Register

To use word length to write data to the low-power mode control register, be sure that evenaddresses are used. Writing with odd addresses to switch to low-power consumption modemay cause a malfunction.

Writing data to the low-power mode control register starts low-power consumption mode(including stop mode and sleep mode). Use the instructions listed in Table 5.3-2 "Instructions toBe Used for Switching to Low-Power Consumption Mode" for this purpose. Using otherinstructions to start low-power consumption mode may cause a malfunction. Any instructioncan be used to control functions other than switching to low-power consumption mode from thelow-power mode control register.

To use word length to write data to the low-power mode control register, be sure that evenaddresses are used. Writing with odd addresses to start low-power consumption mode maycause a malfunction.

Table 5.3-2 Instructions to Be Used for Switching to Low-Power Consumption Mode

MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,#immRi

MOV io,A MOV dir,A MOV addr16,A MOV eam,A

MOV RLi+dip8,A MOVP addr24,A

MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi

MOVW io,A MOVW dir,A MOVW addr16,A MOVW eam,RWi

MOVW RLi+dip8,A MOPW addr24,A

SETB io:bp SETB dir:bp SETB addr16:bp

90


5.3.2 Clock Selection Register (CKSCR)

This section explains the configuration and bit functions of the clock selection register (CKSCR).

■ Clock Selection Register (CKSCR)

Figure 5.3-3 Clock Selection Register (CKSCR)

[Bit 15] SCM

Two clocks system:

This bit indicates whether the main clock or subclock is selected as the machine clock.When this bit is set to 0, the subclock is selected. When this bit is set to 1, the main clock isselected. When SCS=1 and SCM=0, the system is waiting for main clock oscillation tostabilize.

One clock system:

The read value is always "1".

[bit 14] MCM

This bit indicates whether the main clock or PLL clock is selected as the machine clock. "0"indicates that the PLL clock is selected, and "1" indicates that the main clock is selected.When MCS=0 and MCM=1, the system is waiting for the PLL clock oscillation to stabilize.

The PLL clock oscillation stabilization wait time is fixed to 213 main clock cycles.

Clock Selection Register

15 14 13 12 11 10 9 8

Address 0000A1H SCM MCM WS1 WS0 SCS MCS CS1 CS0 CKSCR

(R) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value (1) (1) (1) (1) (1) (1) (0) (0)Read/write

Bit No.

91


[bits 13 and 12] WS1 and WS0

The WS1 and WS0 bits are used to specify the oscillation stabilization wait time when stopmode is released. Specify the oscillation stabilization time according to the type andcharacteristics of the oscillation circuits and oscillation devices connected to the X0 and X1pins.

These bits are not initialized by a reset except a power-on reset and hardware standby

release. Therefore, at power-on, the oscillation stabilization wait time is about 218 counts ofsource oscillation. These bits can be read and written.

Table 5.3-3 "WS Bit Setting" lists the WS bit setting.

[Bit 11] SCS

Two clocks system:

This bit is used to select the main clock or subclock as the machine clock. Writing 0 selectsthe subclock. Writing 1 selects the main clock. When this bit is updated from 0 to 1, theoscillation stabilization wait time for oscillation clock is generated and the timebase timer iscleared automatically. When the subclock is selected, the operation clock is generated bydividing the subclock by fore (the operation clock is 8 kHz at a source oscillation of 32 kHz).

This bit is initialized to 1 by a power-on, hardware standby, watch-dog, external, or softwarereset.

One clock system:

Always write "1".

[bit 10] MCS

This bit is used to select the main clock or PLL clock as the machine clock. Writing "0"selects the PLL clock and writing "1" selects the main clock. When this bit is updated from"1" to "0", the PLL clock oscillation stabilization wait period is created by automaticallyclearing the timebase timer. The oscillation stabilization wait time for the PLL clock is fixed to

213 main clock cycles.

When the main clock is selected, the operation clock is generated by dividing the main clockby two. (The operation clock is 2 MHz at 4 MHz source oscillation.)

When the MCS bit is updated from 0 to 1, the main clock takes over from the PLL clockwhen the edges of the main clock and PLL clock match (after about 1 to 8 PLL clock cycles).Writing to the MCS bit does not immediately change the machine clock. To use a resourcethat depends on the machine clock, always reference the MCM bit beforehand to checkwhether the machine clock has been changed.

Table 5.3-3 WS Bit Setting

WS1 WS0 Oscillation stabilization wait time (at 4 MHz source oscillation)

0 0 Approx. 256μs (210 counts of source oscillation)

0 1 Approx. 2.05 ms (213 counts of source oscillation)

1 0 Approx. 8.19 ms (215 counts of source oscillation)

1 1 Approx. 32.77 ms (217 counts of source oscillation)Approx. 65.54 ms (218 counts of source oscillation) at power-on reset and hardware standby only

92


Note:

The MCS bit is initialized to 1 by a power-on, hardware standby, or watch-dog reset insteadof a reset using an external pin or RST bit.

[bits 9 and 8] CS1 and CS0

These bits determine the multiplication factor of the PLL clock. These bits are initialized to00 by a reset due to power-on and hardware standby.

When the MCS bit is 0, write is disabled. Write 1 to the MCS bit (main clock mode), thenupdate the CS bits. These bits can be read and written to.

Table 5.3-4 "CS Bit Setting" lists the settings of the CS bits.

Note:

When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 5MHz. When an external clock source is used, its frequency can be between 3 MHz and16MHz. Since the highest operating frequency for the CPU and peripheral resource circuitsis 16 MHz, however, normal operation is not guaranteed if a multiplication factor resulting ina higher frequency than 16 MHz is specified. For example, if the external clock frequency is16 MHz, only 1 can be specified as the multiplication factor.

The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4MHz must not be specified.

Table 5.3-4 CS Bit Setting

CS1 CS0 Machine clock (at 4 MHz source oscillation)

0 0 4 MHz (Operation frequency = OSC oscillation frequency)

0 1 8 MHz (Operation frequency = OSC oscillation frequency *2)



93


5.4 Status Transition for Clock Selection

This section explains the status transitions for clock selection.

■ Status Transition for Clock Selection

Figure 5.4-1 Status transition diagram 1 for clock selection (Two clocks system parts No.1)

Power on

Main Main PLLxSCS=1, MCS=1

CS1/0=xx

PLL1 main PLL1 multiplication




SCM=1, MCM=1SCS=1, MCS=0

CS1/0=xxSCM=1, MCM=1

SCS=0 or MCS=1

CS1/0=00SCM=1, MCM=0

SCS=0 or MCS=1


SCS=0 or MCS=1


SCS=0 or MCS=1


SCS=1, MCS=0


SCS=1, MCS=0


SCS=1, MCS=0


SCS=1, MCS=0


SCS=1, MCS=0


MainSCS=0, MCS=x

SCM=1SCM=1

Subclock PLLx

subclock

MCS bit clear and SCS bit setPLL clock oscillation stabilization wait termination and CS1/0=00PLL clock oscillation stabilization wait termination and CS1/0=01PLL clock oscillation stabilization wait termination and CS1/0=10PLL clock oscillation stabilization wait termination and CS1/0=11MCS bit set or SCS bit clearSynchronization timing between PLL clock and main clock and SCS=1Synchronization timing between PLL clock and main clock and SCS=0Main clock oscillation stabilization wait termination and MCS=0

94

5.4 Status Transition for Clock Selection

Figure 5.4-2 Status Transition Diagram 2 for Clock Selection (Two clocks system parts No.2)

Power on

Main Main subclockSCS=1, MCS=1

MCM=1

subclock Main subclock

SCM=1SCS=0

MCM=1SCM=1

SCS=1

MCM=1SCM=0

SCS=0

MCM=1SCM=0

SCS=0, MCS=x


MainSCS=1, MCS=0


subclockPLLx

PLLx

SCS bit clearSubclock edge detection timingSCS bit setMain clock oscillation stabilization wait termination and MCS=1Synchronization timing between PLL clock and main clock and SCS=0Main clock oscillation stabilization wait termination and MCS=0

95


Figure 5.4-3 Clock Selection Status Transition 3 (one-way item)

Note:

In attempting to switch the clock mode, do not attempt to switch to another clock mode orlow-power consumption mode until the first switching is completed. The MCM bit of the clockselection register (CKSCR) indicates that switching is completed.

Power-on

Main clockSCS = 1, MCS = 1SCM = 1, MCM = 1CS1/0 = xxB

Main clock

Main clock

PLLx

The MCS bit is cleared and the SCS bit is set.The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 00B.The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 01B.The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 10B.The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 10B.The MCS bit is set.The PLL clock is synchronized with the main clock and the SCS bit is 1.

SCS = 1, MCS = 0SCM = 1, MCM = 1CS1/0 = xxB

PLL multiplication factor: 1SCS = 1, MCS = 0SCM = 1, MCM = 0CS1/0 = 00'B




SCS = 1, MCS = 1SCM = 1, MCM = 0CS1/0 = 00'B




PLL multiplication factor: 1

Main clockPLL multiplication factor: 2



96

CHAPTER 6 LOW-POWER CONSUMPTION MODES

This chapter explains the functions and operation of the low-power consumption modes.

6.1 "Outline of Low-Power Control Circuit"

6.2 "Status Transitions in Low-Power Consumption Mode"

6.3 "Status Transition Diagram for Low-Power Consumption Mode"

97


6.1 Low-Power Consumption Modes

The MB90435 series supports the following operation modes:• PLL clock mode• PLL sleep mode• PLL watch mode• Pseudo watch mode• Main clock mode• Main sleep mode• Main watch mode• Main stop mode• Subclock mode• Subclock sleep mode• Subclock watch mode• Subclock stop mode• Hardware standby modeModes other than PLL clock mode are classified as low-power consumption modes.

■ Low-Power Consumption Modes

❍ Main clock mode and main sleep mode

In main clock mode or main sleep mode, the main clock (main OSC oscillation clock) and thesubclock (subclock OSC oscillation clock) are used for operation.

The operation clock is generated by dividing the main clock signal by two, and the subclocksignal (subclock OSC oscillation clock) is used as the timer clock signal while the PLL clock(VCO oscillation clock) is stopped.

❍ Subclock mode and subclock sleep mode

In subclock mode or subclock sleep mode, only the subclock is used for operation. Theoperation clock is generated by the subclock signal by fore, and the main clock and PLL clockare stopped.

❍ PLL sleep mode and main sleep mode

In PLL sleep mode or main sleep mode, only the CPU operation clock is stopped. Clocks otherthan the CPU clock are used for operation.

❍ Pseudo watch mode

In pseudo watch mode, only the watch timer and timebase timer are used for operation.

98


❍ PLL watch mode, Main watch mode, and subclock watch mode

In PLL watch mode, main watch mode, or subclock watch mode, only the watch timer is usedfor operation. Only the subclock signal is used for operation and the main clock and PLL clockare stopped. PLL watch mode, main watch mode, and subclock watch mode are different inthat the operation modes at return by interrupts are PLL clock mode, main clock mode, andsubclock mode. The operation in the watch modes is the same.

❍ Main stop mode, subclock stop mode, and hardware standby mode

In main stop mode, subclock stop mode, or hardware standby mode, oscillation is stopped anddata can be held at the lowest power consumption level. Main stop mode and subclock stopmode are different in that the operation mode at return by interrupts is main clock mode andsubclock mode. Operation in the stop modes is the same.

❍ Intermittent CPU operation function

The intermittent CPU operation function causes intermittent operation of the clock supplied tothe CPU when an internal register, internal memory, internal resource, or external bus isaccessed. The CPU execution speed is decreased while a high-speed clock is supplied tointernal resources, enabling processing with little power consumed.

The CS1 and CS0 bits are used to set the multiplication factor of the PLL clock. Themultiplication factor is obtained by multiplying the clock signal by 2, 4, 6, or 8. This clock signalis divided by two and used as a machine clock signal.

Note:


99


■ Operation Status of Low-Power Consumption Mode

Table 6.1-1 "Operation Status in Low-Power Consumption Mode (Two clocks system parts)"and Table 6.1-2 "Operation Status in Low-Power Consumption Mode (One clock system parts)lists the chip operation status in each operation mode.

Table 6.1-1 Operation Status in Low-Power Consumption Mode (Two clocks system parts)

StatusTransition condition

Subclock oscillation

Main oscillation

Machine clock

CPU Peripheral PinRelease method

SubclockSCS=0MCS=x

Operating Stopped Operating Operating Operating OperatingExternal resetInterrupt

Subclock sleep

SCS=0MCS=xSLP=1

Operating Stopped Operating Stopped Operating OperatingExternal resetInterrupt

Main sleep

SCS=1MCS=1SLP=1

Operating Operating Operating Stopped Operating OperatingExternal resetInterrupt

PLL sleep

SCS=1MCS=0SLP=1

Operating Operating Operating Stopped Operating OperatingExternal resetInterrupt

Pseudo timer (SPL=0)

SCS=1MCS=0STP=1

Operating Operating Stopped Stopped StoppedPrevious status held

External resetInterrupt *1

Pseudo timer (SPL=1)

SCS=1MCS=0STP=1

Operating Operating Stopped Stopped Stopped HI-ZExternal resetInterrupt *1

Timer (SPL=0)

SCS=xMCS=xTMD=0

Operating Stopped Stopped Stopped StoppedPrevious status held


Timer (SPL=1)

SCS=xMCS=xTMD=0

Operating Stopped Stopped Stopped Stopped HI-ZExternal resetInterrupt *2

Stop (SPL=0)

MCS=1or SCS=0STP=1

Stopped Stopped Stopped Stopped StoppedPrevious status held


Stop (SPL=1)

MCS=1or SCS=0STP=1

Stopped Stopped Stopped Stopped Stopped HI-ZExternal resetInterrupt *3

Hardware standby

HST=L Stopped Stopped Stopped Stopped Stopped HI-Z HST=H

*1: Watch prescaler, timebase timer, and external interrupt*2: Watch prescaler and external interrupt*3: External interrupt

100


Table 6.1-2 Operation Status in Low-Power Consumption Mode (One clock system parts)

Transition condition

Subclock oscillation

Main clock oscillation

Machine clock

CPU Peripherals PinsRelease method

Main sleepSCS=1MCS=1SLP=1

- Operating Operating Stopped Operating OperatingExternal reset interrupt

POLL sleepSCS=1MCS=0SLP=1

- Operating Operating Stopped Operating OperatingExternal reset interrupt

Pseudo watch

(SPL=0)

SCS=1MCS=0STP=1

- Operating Stopped Stopped Stopped RetainedExternal reset interrupt *4

Pseudo watch

(SPL=1)

SCS=1MCS=0STP=1

- Operating Stopped Stopped Stopped Hi-zExternal reset interrupt *4

Stop (SPL=0)

SCS=1MCS=1STP=1

- Stopped Stopped Stopped Stopped RetainedExternal reset interrupt *5

Stop (SPL=1)

SCS=1MCS=1STP=1

- Stopped Stopped Stopped Stopped Hi-zExternal reset interrupt *5

Hardware standby

HST=L - Stopped Stopped Stopped Stopped Hi-z HST=H

*4: Timebase timer and external interrupt*5: External interrupt

101


6.1.1 Sleep Mode

In sleep mode, only the clock supplied to the CPU is stopped. As a result, the CPU terminates while peripheral circuits keep operating.However, the watch mode cannot be used in the one clock system parts.

■ Transition to Sleep Mode

Writing 1 to the SLP bit, 1 to the TMD bit, and 0 to the STP bit of low-power consumption modecontrol register (LPMCR) starts transition to sleep mode.

If an interrupt request has been issued when "1" is written to the SLP bit, the standby controlcircuit does not enter sleep mode. Therefore, the CPU executes the next instruction if theinterrupt cannot be accepted, or immediately branches to the interrupt processing routine if theinterrupt can be accepted.

In sleep mode, the values of special registers such as the accumulator and the internal RAM aremaintained.

■ Releasing Sleep Mode

The standby control circuit releases sleep mode in the event of a reset input or an interrupt. Ifsleep mode is released by a reset, the reset status takes effect after sleep mode is released.

If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 insleep mode, the standby control circuit releases sleep mode. After sleep mode is released,processing is handled as normal interrupt processing. The CPU executes the instruction that isnot in the standby write pending state, then executes interrupt processing when the interruptcan be accepted according to the I flag in the condition code register (CCR), interrupt levelmask register (ILM), and interrupt control register (ICR). If the interrupt cannot be accepted,processing continues with the instruction following the instruction that was placed in sleepmode.

Note:

When subclock sleep mode is returned to main clock mode using an external reset pin (RSTpin), input level "L" for at least 2 machine cycles of the subclock.

102


6.1.2 Pseudo Watch Mode

Pseudo watch mode stops operations other than source oscillation (main and subclock), the watch timer, and the timebase timer.

■ Transition to Pseudo Watch Mode

Writing 1 to the SCS bit and 0 to the MCS bit of the clock selection register (CKSCR) and 1 tothe TMD bit and 1 to the STP bit of low-power consumption mode control register (LPMCR)starts transition to pseudo watch mode.

The SPL bit of the low-power mode control register (LPMCR) can be used to control whetherthe I/O pin is maintained at the immediately preceding status or at high impedance in pseudowatch mode.

If an interrupt request has been issued when 1 is written to the STP bit, the standby controlcircuit does not enter pseudo watch mode.

In pseudo watch mode, the values of special registers such as the accumulator and the internalRAM register are maintained.

■ Releasing Pseudo Watch Mode

The standby control circuit releases pseudo watch mode when a reset signal is input or aninterrupt request is issued. If pseudo watch mode is released by a reset cause, the reset statustakes effect after pseudo watch mode is released.

To return from pseudo watch mode, the standby control circuit initially releases pseudo watchmode, then enters the PLL clock oscillation stabilization wait state. When the release of pseudowatch mode starts by an interrupt request, the reset sequence is performed using the mainclock.

If a peripheral resource circuit issues an interrupt request of a higher interrupt level than 7, thestandby control circuit releases pseudo watch mode. After pseudo watch mode is released,processing is handled as normal interrupt processing. The CPU executes the instruction thatboth is not in the write pending state and follows the standby write instruction, then executesinterrupt processing when the interrupt can be accepted according to the I flag in the conditioncode register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). Ifthe interrupt cannot be accepted, processing continues with the instruction following theinstruction that was executed before transition to pseudo watch mode.

Notes: [only for MB90437L(S)/438L(S)]

• When pseudo watch mode is returned to main clock mode using an external reset pin (RSTpin), input level "L" for at least 100 μs.

• When pseudo watch mode is returned by an interrupt, the interrupt processing is performedafter the maximum 80 μs after the interrupt request is accepted.

103


6.1.3 Watch Mode

Watch mode stops operations other than subclock source oscillation and the watch timer.However, the watch mode cannot be used in the one clock system parts.

■ Transition to Watch Mode

Writing 0 to the TMD bit of the clock selection register (CKSCR) starts transition to watch mode.

The SPL bit of the low-power mode control register (LPMCR) can be used to control whetherthe I/O pin is maintained at the immediately preceding status or at high impedance in pseudowatch mode.

If an interrupt request has been issued when 1 is written to the TMD bit, the standby controlcircuit does not enter watch mode.

In watch mode, the values of special registers such as the accumulator and the internal RAMregister are maintained.

■ Releasing Watch Mode

The standby control circuit releases watch mode when a reset signal is input or an interruptrequest is issued. If watch mode is released by a reset cause, the reset status takes effect afterwatch mode is released.

To return from subclock watch mode, the standby control circuit initially releases watch mode,then immediately enters subclock state. When the release of subclock watch mode is a resetcause, the reset sequence is performed using the subclock signal.

To return from main watch mode or PLL watch mode, the standby control circuit initiallyreleases watch mode, then enters the main clock oscillation stabilization wait state. When therelease of watch mode is a reset cause, the reset sequence is performed using the subclocksignal.

If a peripheral resource circuit issues an interrupt request of a higher interrupt level than 7, thestandby control circuit releases watch mode. After pseudo watch mode is released, processingis handled as normal interrupt processing. The CPU executes the instruction that both is not inthe write pending state and follows the standby write instruction, then executes interruptprocessing when the interrupt can be accepted according to the I flag in the condition coderegister (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If theinterrupt cannot be accepted, processing continues with the instruction following the instructionthat was executed before transition to pseudo watch mode.

Note:

When watch mode is returned to main clock mode using an external reset pin (RST pin),input level "L" for at least 2 machine cycles of the subclock.

104


6.1.4 Stop mode

Stop mode stops source oscillation (main and subclock). Data can be maintained at the lowest power consumption level.

■ Transition to Stop Mode

Writing 0 to the SCS bit or 1 to the MCS bit of the clock control register and 1 to the STP bit ofthe low-power mode control register (LPMCR) causes the standby control circuit to enter stopmode.

The SPL bit of the low-power mode control register (LPMCR) can be used to control whetherthe I/O pin is maintained at the immediately preceding status or at high impedance.

If an interrupt request has been issued when 1 is written to the STP bit, the standby controlcircuit does not enter stop mode.

In stop mode, the values of special registers such as the accumulator and the internal RAMregister are maintained.

■ Releasing Stop Mode

The standby control circuit releases stop mode when a reset signal is input or an interrupt isgenerated. If stop mode is released by a reset cause, the reset status takes effect after stopmode is released.

To return from subclock watch mode, the standby control circuit initially enters subclockoscillation stabilization wait mode, then releases stop mode. When the release of stop mode isa reset cause, the reset sequence is performed after the subclock oscillation stabilization waittime elapses.

To return from main stop mode, the standby control circuit initially enters main clock oscillationstabilization wait mode, then releases stop mode. When the release of stop mode is a resetcause, the reset sequence is performed after the main clock oscillation stabilization wait timeelapses.

If a peripheral circuit or other resource issues an interrupt request of a higher interrupt level than7 in stop mode, the standby control circuit releases stop mode. After subclock stop mode isreleased, the subclock oscillation stabilization wait time applies and processing is handled asnormal interrupt processing. The CPU executes the instruction that both is not in the writepending state and follows the standby write instruction, then executes interrupt processing whenthe interrupt can be accepted according to the I flag in the condition code register (CCR),interrupt level mask register (ILM), and interrupt control register (ICR). If the interrupt cannot beaccepted, processing continues with the instruction following the instruction that was executedbefore transition to stop mode.

After main stop mode is released, the oscillation stabilization wait time specified in WS1 andWS0 bits of the clock selection register (CKSCR) elapses and processing is then handled asnormal interrupt processing. The CPU executes the instruction that both is not in the writepending state and follows the standby write instruction, then branches to interrupt processingwhen the interrupt can be accepted according to the I flag in the condition code register (CCR),interrupt level mask register (ILM), and interrupt control register (ICR). If the interrupt cannot beaccepted, processing continues with the instruction following the instruction that was executedbefore transition to stop mode.

105


Note:

When stop mode is returned to main clock mode using an external reset pin (RST pin), input

level "L" for at least the oscillation time of the oscillator (*1) + 4 machine cycles.

*1: The oscillation time of the oscillator is the time required to reach 90% of amplitude. Ittakes several to dozens of ms for crystal oscillators, hundreds of μs to several ms forFAR/ceramic oscillators, and 0 ms for external clocks.

106


6.1.5 Hardware Standby Mode

In the hardware standby mode, oscillation is stopped and all I/O pins are set to high impedance while the HST pin is at "L" level, regardless of other statuses (including reset).

■ Transition to Hardware Standby Mode

The standby control circuit can be set in hardware standby mode from any status by setting theHST pin at "L" level. In hardware standby mode, oscillation is stopped and all I/O pins are set tohigh impedance while the HST pin is at "L" level, regardless of other status including reset.

In hardware standby mode, the internal RAM contents are maintained but the special registerssuch as the accumulator are initialized.

■ Releasing Hardware Standby Mode

Hardware standby mode can be released only by the HST pin. When the HST pin is set at "H"level, the standby control circuit releases hardware standby mode, enables the internal resetsignal, and enters oscillation stabilization wait status. After the oscillation stabilization waitperiod, the standby control circuit releases the internal reset, and consequently the CPU startsexecution from the reset sequence.

The oscillation stabilization wait time for hardware standby mode is fixed to 218 cycles of thesource oscillation.

107


6.1.6 Intermittent CPU Operation

The intermittent CPU operation function delays the activity of the internal bus cycle to stop the clock supplied to the CPU when a register, internal memory (ROM, RAM, I/O or resource), or the external bus is accessed. While a high-speed clock is supplied to internal resources, the CPU execution speed is decreased, thus enabling processing with little power consumed. The CG1 and CG0 bits are used to specify the cycle count for clock stop.External bus operation is performed using the same clock as that for the resource.

■ Intermittent CPU Operation

The instruction execution time using the intermittent CPU operation function can be obtained byadding a compensation value to the ordinary execution time. The compensation value isobtained by multiplying the number of accesses to a register, internal memory, internalresource, or external bus by the cycle count for pausing.

108

6.2 Status Transitions in Low-Power Consumption Mode


In low-power consumption mode, the transition to each status is based on the condition set in the clock selection register or low-power mode control register.

■ Transition Conditions in Low-Power Consumption Mode

The meanings of symbols used in the table and figure are explained below:

• MCS: MCS bit (clock selection register) (PLL clock mode selected when MSC=0)

• SCS: SCS bit (clock selection register) (subclock mode selected when SCS=0)

• STP: STP bit (low-power mode control register) (stop mode selected when STP=1)

• SLP: SLP bit (low-power mode control register) (sleep mode selected when SLP=1)

• TMD: TMD bit (low-power mode control register) (watch mode selected when TMD=0)

• MCM: MCM bit (clock selection register) (PLL clock used when MCM=0)

• SCM: SCM bit (clock selection register) (subclock used when SCM=0)

• SCD: Subclock oscillation stop (subclock oscillation stopped when SCD=1)

• MCD: Main clock oscillation stop (main clock oscillation stopped when MCD=1)

• PCD: PLL clock oscillation stop (PLL clock oscillation stopped when PCD=1)

Table 6.2-1 Transition Conditions of the Two Clocks System Parts

Status before transition Transition condition Status after transition

Power-on 01 Main oscillation stabilization wait termination

Main mode

Main oscillation stabilization 05 Main oscillation stabilization wait termination

Main mode

Main mode 06 SCS=0 write MS transition mode

07 SCS=1, MCS=0 write MP transition mode

31 TMD=1, STP=0, SLP=1 write Main sleep mode

32 TMD=0 write Main timer transition mode

33 TMD=1, STP=1 write Main stop

PLL mode 21 SCS=0 write PS transition mode

20 SCS=1, MCS1 write PM transition mode

59 TMD=1, STP=0, SLP=1 write PLL sleep mode

58 TMD=0 write PLL timer transition P

57 TMD=1, STP=1 write Pseudo timer transition mode

109


Subclock mode 10 SCS=1, MCS1 write SM transition mode

12 SCS=1, MCS=0 write SP transition mode

11 Reset activation Main oscillation stabilization

42 TMD=1, STP=0, SLP=1 write Subclock sleep mode

43 TMD=0 write Subclock watch mode

44 TMD=1, STP=1 write Subclock stop mode

PM transition mode 13 PLL -> main switch wait termination Main mode

38 TMD=1, STP=0, SLP=1 write PM transition sleep mode

39 TMD=0 write and PLL -> main switch wait termination

Main timer transition mode

40 TMD=1, STP =1 write and PLL -> main switch wait termination

Main stop mode

SM transition mode 02 Main oscillation stabilization time wait termination

Main mode

03 Reset activation or interrupt Main oscillation stabilization

04 SCS=0 write Subclock mode

27 TMD=1, STP=0, SLP=1 write SM transition sleep mode

28 TMD=0 write and main oscillation stabilization wait termination

Main watch mode

29 TMD=1, STP=1 write and main oscillation stabilization wait termination

Main stop mode

MP transition mode 16 PLL oscillation stabilization wait termination

PLL mode

14 SCS=1, MCS=1 write Main mode

15 SCS=0 write MS transition mode

68 TMD=1, STP=0, SLP=1 write MP transition sleep mode

70 TMD=0 write PLL timer transition mode

69 TMD=1, STP=1 write Pseudo watch mode

Table 6.2-1 Transition Conditions of the Two Clocks System Parts (Continued)


110


SP transition mode 17 Main oscillation stabilization wait termination

MP transition mode

18 MCS=1 write SM transition mode


75 TMD=1, STP=0, SLP=1 write SP transition sleep mode

76 TMD=0 write PLL watch mode

78 TMD=1, STP=1 write and main oscillation stabilization wait termination

Pseudo watch mode

MS transition mode 09 Main -> subclock switch wait termination Subclock mode

08 Reset activation Main mode

51 TMD=1, STP=0, SLP=1 write MS transition sleep mode

52 TMD=0 write and main -> subclock switch wait termination

Subclock watch mode

53 TMD=1, STP=1 write and main -> subclock switch wait termination

Subclock stop mode

PS transition mode 23 PLL -> main clock switch wait termination MS transition mode

22 SCS=1 write PM transition mode

56 TMD=1, STP=0, SLP=1 write PS transition sleep mode

Main sleep 26 Interrupt or reset activation Main mode

SM transition sleep 24 Main oscillation stabilization wait termination

Main sleep

25 Interrupt or reset activation SM transition mode

PM transition sleep 34 PLL -> main clock switch wait termination Main sleep mode

35 Interrupt or reset activation PM transition mode

PLL sleep mode 63 Interrupt or reset activation PLL mode

MP transition sleep 66 PLL oscillation stabilization wait termination

PLL sleep mode

67 Interrupt or reset activation MP transition mode

SP transition sleep 73 Main oscillation stabilization wait termination

MP transition sleep

74 Interrupt or reset activation SP transition mode

Subclock sleep 46 Interrupt or reset activation Subclock mode

MS transition sleep 49 Main -> subclock switch wait termination Subclock sleep mode

50 Interrupt or reset activation MS transition mode



111


Note:

• When stop mode is returned to main clock mode using an external reset pin (RST pin), input



• When subclock mode, sleep mode or watch mode is returned to main clock mode using anexternal reset pin (RST pin), input level "L" for at least 2 machine cycles of the subclock.

PS transition sleep 54 PLL -> main clock switch wait termination MS transition sleep mode

55 Interrupt or reset activation PS transition mode

Main timer 30 Interrupt or reset activation SM transition mode

Main timer transition 36 Main -> subclock switch wait termination Main timer

37 Interrupt or reset activation Main mode

PLL timer 77 Interrupt or reset activation SP transition mode

PLL timer transition M 72 Main -> subclock switch wait termination PLL timer


PLL timer transition P 65 PLL -> main clock switch wait termination PLL time transition M

64 Interrupt or reset activation PLL mode

Subclock timer 47 Interrupt or reset activation Subclock mode

Main stop 41 Interrupt or reset activation Main oscillation stabilization

Pseudo timer 62 Interrupt or reset activation MP transition mode

Pseudo timer transition 61 PLL -> main clock switch wait termination Pseudo watch mode


Subclock stop 48 Interrupt Subclock oscillation stabilization


Subclock oscillation stabilization

45 Subclock oscillation stabilization termination

Subclock mode




112


Note:

When stop mode is returned to main clock mode using an external reset pin (RST pin), input



Table 6.2-2 Transition Conditions of the One Clock System Parts

Status before transition

Transition condition Status after transition

Power-on 01 Main oscillation stabilization time end Main mode

Main oscillation stabilization

05 Main oscillation stabilization time end Main mode

Main mode

07 SCS=1, MCS=0 write MP transition mode

31 TMD=1, STP=0, SLP=1 write Main sleep

33 TMD=1, STP=1 write Main stop

PLL mode

20 SCS=1, MCS=1 write PM transition mode

59 TMD=1, STP=0, SLP=1 write PLL sleep

57 TMD=1, STP=1 write Pseudo watch transition

PM transition mode

13 PLL/main switching timing wait end Main mode

38 TMD=1, STP=0, SLP=1 write PM transition sleep

40 TMD=1, STP=1 write & PLL to main switching timing wait end

Main stop

MP transition mode 16 PLL oscillation stabilization wait time end PLL mode

14 SCS=1, MCS=1 write Main mode

68 TMD=1, STP=0, SLP=1 write MP transition sleep

69 TMD=1, STP=1 write Pseudo watch mode

Main sleep 26 Interrupt or reset activation Main mode

PM transition sleep 34 PLL/main switching timing wait end Main sleep

35 Interrupt or reset activation PM transition mode

PLL sleep 63 Interrupt or reset activation PLL mode

MP transition sleep 66 PLL oscillation stabilization wait time end PLL sleep


Main stop 41 Interrupt or reset activation Main oscillation stabilization

Pseudo watch 62 Interrupt or reset activation MP transition mode

Pseudo watch transition 61 PLL/main switching timing wait end Pseudo watch mode


113


6.3 Status Transition Diagram for Low-Power Consumption Mode

Figure 6.3-1 "Status Transition Diagram A for Low-Power Consumption Mode (Two Clocks System Parts)" to Figure 6.3-7 "Status Transition Diagram for Low-Power Consumption Mode (One Clock System Parts) 3" are status transition diagrams.For simplification, the status transition diagrams show events that occur simultaneously as stepwise transitions. In actuality, status transition take place instantaneously.

■ Status Transition Diagram for Low-Power Consumption Mode (Two Clocks System Parts)

For simplification, the status transition diagram shows events that occur simultaneously asstepwise transitions. In actuality, however, status transitions take place instantaneously.

In the status transition diagram, if MSC=1 and SLP=1 are set simultaneously in PLL clockmode, a transition to PM transition mode is followed by a transition to PM transition sleep. Inactuality, however, a transition from PLL clock mode to PM transition sleep takes placeinstantaneously. If reset is activated in subclock sleep mode, a transition to subclock mode isfollowed by a transition to a main oscillation stabilization period. In actuality, however, atransition from subclock sleep mode to a main oscillation stabilization period takes place.

Note:

• When stop mode is returned to main clock mode using an external reset pin (RST pin), input



• When subclock mode, sleep mode or watch mode is returned to main clock mode using anexternal reset pin (RST pin), input level "L" for at least 2 machine cycles of the subclock.

114


Figure 6.3-1 Status Transition Diagram A for Low-Power Consumption Mode (Two Clocks System Parts)

Power-on reset SM transition mode 03 Main oscillation stabilization period

SCS=1, MCS=1, SCS=1, MCS=1, SCS=1, MCS=1,STP=0, SLP=0, STP=0, SLP=0, STP=0, SLP=0,TMD=1 TMD=1 TMD=1SCM=1,MCM=1, SCM=0,MCM=1, 04 SCM=1,MCM=1,SCD=0, MCD=0, SCD=0, MCD=0, SCD=0, MCD=0,PCD=1 PCD=1 PCD=1

0201 05

10

11

Main mode MS transition mode Subclock modeSCS=1, MCS=1, SCS=0, MCS=x, SCS=0, MCS=x,STP=0, SLP=0, 06 STP=0, SLP=0, 09 STP=0, SLP=0,TMD=1 TMD=1 TMD=1SCM=1,MCM=1, 08 SCM=1,MCM=1, SCM=0,MCM=1,SCD=0, MCD=0, SCD=0, MCD=0, SCD=0, MCD=1,PCD=1 PCD=1 PCD=1

07 12

18 19

13 15

PM transition mode MP transition mode SP transition modeSCS=1, MCS=1, 14 SCS=1, MCS=0, SCS=1, MCS=0,STP=0, SLP=0, STP=0, SLP=0, 17 STP=0, SLP=0,TMD=1 TMD=1 TMD=1SCM=1,MCM=0, SCM=1,MCM=1, SCM=0,MCM=1,SCD=0, MCD=0, SCD=0, MCD=0, SCD=0, MCD=0,PCD=1 PCD=0 PCD=1

16

2320

PLL mode PS transition modeSCS=1, MCS=0, 22 SCS=0, MCS=x,STP=0, SLP=0, STP=0, SLP=0,TMD=1 21 TMD=1SCM=1,MCM=0, SCM=1,MCM=0,SCD=0, MCD=0, SCD=0, MCD=0,PCD=0 PCD=0

115


Figure 6.3-2 Status Transition Diagram B for Low-Power Consumption Mode (Two Clocks System Parts)

SM transition sleep Main sleepSCS=1, MCS=1, SCS=1, MCS=1,STP=0, SLP=1, STP=0, SLP=1,TMD=1 TMD=1 26SCM=0, MCM=1, 24 SCM=1, MCM=1,SCD=0, MCD=0, SCD=0, MCD=0,PCD=1 PCD=1

25

27 31

SM transition mode 28 Main timer Main modeSCS=1, MCS=1, SCS=1, MCS=1, SCS=1, MCS=1,STP=0, SLP=0, STP=0, SLP=0, STP=0, SLP=0,TMD=1 TMD=0 TMD=1SCM=0, MCM=1, 30 SCM=0, MCM=1, SCM=1, MCM=1,SCD=0, MCD=0, SCD=0, MCD=1, SCD=0, MCD=0,PCD=1 PCD=1 PCD=1

3229 03 33

3734 36 05

PM transition sleep Main timer transitionMain oscillation stabilization time

SCS=1, MCS=1, SCS=1, MCS=1, SCS=1, MCS=1,STP=0, SLP=1, STP=0, SLP=0, STP=0, SLP=0,TMD=1 TMD=0 TMD=1SCM=1, MCM=0, SCM=1, MCM=1, SCM=1, MCM=1,SCD=0, MCD=0, SCD=0, MCD=0, SCD=0, MCD=0,PCD=0 PCD=1 PCD=1

35

38

39PM transition mode Main stop

SCS=1, MCS=1, SCS=1, MCS=1, 41STP=0, SLP=0, STP=1, SLP=0,TMD=1 40 TMD=1SCM=1, MCM=0, SCM=1, MCM=1,SCD=0, MCD=0, SCD=1, MCD=1,PCD=0 PCD=1

116


Figure 6.3-3 Status Transition Diagram C for Low-Power Consumption Mode (Two Clocks System Parts)

Subclock mode 45Subclock oscillation stabilization time 80

Main oscillation stabilization timeSCS=0, MCS=x, SCS=0, MCS=x, SCS=1, MCS=x,

STP=0, SLP=0, STP=0, SLP=0, STP=0, SLP=0,TMD=1 TMD=1 TMD=1SCM=0, MCM=1, SCM=0, MCM=1, SCM=1, MCM=1,SCD=0, MCD=1, 44 SCD=0, MCD=1, SCD=0, MCD=0,PCD=1 PCD=1 PCD=1

42 43

46 48 79

Subclock sleep Subclock timer Subclock stopSCS=0, MCS=x, SCS=0, MCS=x, SCS=0, MCS=x,STP=0, SLP=1, 47 STP=0, SLP=0, STP=1, SLP=0,TMD=1 TMD=0 TMD=1SCM=0, MCM=1, SCM=0, MCM=1, SCM=0, MCM=1,SCD=0, MCD=1, SCD=0, MCD=1, SCD=1, MCD=1,PCD=1 PCD=1 PCD=1

49 5253

MS transition sleep 51 MS transition modeSCS=0, MCS=x, SCS=0, MCS=x,STP=0, SLP=1, STP=0, SLP=0,TMD=1 TMD=1SCM=1, MCM=1, SCM=1, MCM=1,SCD=0, MCD=0, SCD=0, MCD=0,PCD=1 50 PCD=1

2354

PM transition sleep 56 PM transition modeSCS=1, MCS=x, SCS=0, MCS=x,STP=0, SLP=1, STP=0, SLP=0,TMD=1 TMD=1SCM=1, MCM=0, SCM=1, MCM=0,SCD=0, MCD=0, SCD=0, MCD=0,PCD=0 55 PCD=0

117


Figure 6.3-4 Status Transition Diagram D for Low-Power Consumption Mode (Two Clocks System Parts)

Note:


PLL mode 60 Pseudo timer transition Pseudo timer modeSCS=1, MCS=0, SCS=1, MCS=0, 61 SCS=1, MCS=0,STP=0, SLP=0, STP=1, SLP=0, STP=1, SLP=0,TMD=1 57

59

TMD=1 TMD=1SCM=1, MCM=0, SCM=1, MCM=1, 62 SCM=1, MCM=1,SCD=0, MCD=0, 58 SCD=0, MCD=0, SCD=0, MCD=0,PCD=0 PCD=0 PCD=1

63

PLL sleep PLL timer transition PSCS=1, MCS=0, SCS=1, MCS=0,STP=0, SLP=1, STP=0, SLP=0,TMD=1 TMD=0SCM=1, MCM=0, SCM=1, MCM=0,SCD=0, MCD=0, SCD=0, MCD=0PCD=1 PCD=0

65

64

16

66 69

MP transition sleep 68 MP transition mode 71 PLL timer transition MSCS=1, MCS=0, SCS=1, MCS=0, SCS=1, MCS=0,STP=0, SLP=1, STP=0, SLP=0, STP=0, SLP=0,TMD=1 TMD=1 TMD=0SCM=1, MCM=1, 67 SCM=1, MCM=1, 70 SCM=1, MCM=1,SCD=0, MCD=0, SCD=0, MCD=0, SCD=0, MCD=0,PCD=0 PCD=0 PCD=1

7873 17 72

SP transition sleep 75 SP transition mode 77 PLL timerSCS=1, MCS=0, SCS=1, MCS=0, SCS=1, MCS=0,STP=0, SLP=1, STP=0, SLP=0, STP=0, SLP=0,TMD=1 TMD=1 TMD=0SCM=0, MCM=1, SCM=0, MCM=1, SCM=0, MCM=1,SCD=0, MCD=0, SCD=0, MCD=0, SCD=0, MCD=1,PCD=1 74 PCD=1 76 PCD=1

118


■ Status Transition Diagram for Low-Power Consumption Mode (One Clock System Parts)

Figure 6.3-5 Status Transition Diagram for Low-Power Consumption Mode (One Clock System Parts) 1

Power-on resetSCS=1,MCS=1STP=0,SLP=0TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=1

Main oscillation stabilization timeSCS=1,MCS=1STP=0,SLP=0TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=1

Main modeSCS=1,MCS=1STP=0,SLP=0TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=1

PM transition modeSCS=1,MCS=1STP=0,SLP=0TMD=1SCM=1,MCM=0SCD=0,MCD=0PCD=0

MP transition modeSCS=1,MCS=0STP=0,SLP=0TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=0

PLL modeSCS=1,MCS=0STP=0,SLP=0TMD=1SCM=1,MCM=0SCD=0,MCD=0PCD=0

01

13

05

07

14

2016

119



Main sleepSCS=1,MCS=1STP=0,SLP=1TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=1

PM transition sleepSCS=1,MCS=1STP=0,SLP=1TMD=1SCM=1,MCM=0SCD=0,MCD=0PCD=0

Main stopSCS=1,MCS=1STP=1,SLP=0TMD=1SCM=1,MCM=1SCD=1,MCD=1PCD=1

PM transition modeSCS=1,MCS=1STP=0,SLP=0TMD=1SCM=1,MCM=0SCD=0,MCD=0PCD=0

Main oscillation stabilization timeSCS=1,MCS=1STP=0,SLP=0TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=1

Main modeSCS=1,MCS=1STP=0,SLP=0TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=1

26

31

34

35

38

40 41

33

05

120



Note:

In attempting to switch the clock mode, do not attempt to switch to another clock mode orlow-power consumption mode until the first switching is completed. The MCM bit of the clockselection register (CKSCR) indicates that switching is completed.

PLL modeSCS=1,MCS=0STP=0,SLP=0TMD=1SCM=1,MCM=0SCD=0,MCD=0PCD=0

Pseudo watch transitionSCS=1,MCS=0STP=1,SLP=0TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=1

PLL sleepSCS=1,MCS=0STP=0,SLP=1TMD=1SCM=1,MCM=0SCD=0,MCD=0PCD=0

MS transition sleepSCS=1,MCS=0STP=0,SLP=1TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=0

MP transition modeSCS=1,MCS=0STP=0,SLP=0TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=0

Pseudo watch modeSCS=1,MCS=0STP=1,SLP=0TMD=1SCM=1,MCM=1SCD=0,MCD=0PCD=1

67

6866

1669

62

6160

57

63

59

121


122

CHAPTER 7 MEMORY ACCESS MODES

This chapter explains the functions and operations of the memory access modes.

7.1 "Outline of Memory Access Modes"

7.2 "External Memory Access (Bus Pin Control Circuit)

7.3 "External Memory Access Control Signal Operation

123


7.1 Outline of Memory Access Modes

In the F2MC-16LX, various modes are provided for access methods and access areas.

■ Memory Access Modes

❍ Operation mode

Operation mode means the mode for controlling the device operation status. The operationmode is specified by the MDx mode setting pin and the Mx bit in mode data. By selecting anoperation mode, ordinary operation can be activated and flash memory can be written.

❍ Bus mode

Bus mode means the mode for controlling the internal ROM operation and external accessfunction. The bus mode is specified by the MDx mode setting pin and the Mx bit in mode data.The MDx mode setting pin specifies the bus mode for reading the reset vector and mode data,and the Mx bit in mode data specifies the bus mode for normal operation.

❍ Access mode

Access mode means the mode for controlling the external data bus width. The access mode isspecified by the MDx mode setting pin and the S0 bit in mode data. By selecting an accessmode, an 8- or 16-bit external data bus is specified.

Table 7.1-1 Mode Pins and Modes

Operation mode Bus mode Access mode

RUN

Single chip -

Internal ROM, external bus 8 bits

16 bits

External ROM, external bus 8 bits

16 bits

Flash programming - -

Test functions - -

124


7.1.1 Mode Pins

Table 7.1-2 "Mode Pins and Modes" lists the operations that can be specified by combining the three external pins MD2 to MD0.

■ Mode pins

Table 7.1-2 Mode Pins and Modes

Mode pin settingMode name

Reset vector

access area

External data bus

widthRemarks

MD2 MD1 MD0

0 0 0 External vector mode 0 External 8 bits

0 0 1 External vector mode 1 External 16 bitsReset vector, 16-bit bus width access

0 1 0 Reserved

0 1 1 Internal vector mode Internal (Mode data)

Reset sequence and later segments are controlled based on mode data.

1 0 0Reserved

1 0 1

1 1 0Flash memory serial programming (*1) - - -

1 1 1 Flash memory - -Mode when parallel writer is used

*1: Data cannot be written only by setting the flash serial programming mode by mode pins.Other must be set. For detail, see CHAPTER 24 "EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION".

125


7.1.2 Mode Data

Mode data is stored at FFFFDFH of main memory and used for controlling the CPU

operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence.The setting of this register is valid after the reset sequence.Always set the reserved bits to "0".

■ Mode Data

Figure 7.1-1 Mode Data Configuration

[Bits 7 and 6] M1, M0 (bus mode setting bits)

The M1 and M0 bits are used to specify the operation mode after the reset sequence iscompleted. Table 7.1-3 "M1 and M0 (Bus Mode Setting Bit) Functions" shows therelationship between the M1 and M0 bits and the functions.

[Bit 3] S0 (mode setting bit)

The S0 bit is used to specify the bus mode or access mode after the reset sequence iscompleted. Table 7.1-4 "S0 (Mode Setting Bit) Functions" shows the relationship betweenthe S0 bit and the functions.

Mode data address

7 6 5 4 3 2 1 0

address FFFFDFH M1

Bit No.

Reserved Reserved Reserved Reserved ReservedM0 S0

Table 7.1-3 M1 and M0 (Bus Mode Setting Bit) Functions

M1 M0 Function Remarks

0 0 Single-chip mode

0 1 Internal ROM, external bus mode

1 0 External ROM, external bus mode

1 1 Setting prohibited

Table 7.1-4 S0 (Mode Setting Bit) Functions

S0 Function Remarks

0 External 8-bit data bus mode

1 External 16-bit data bus mode

126


7.1.3 Memory Space in Each Bus Mode

Figure 7.1-2 "Relationship between Access Areas and Physical Addresses for Each Bus Mode" shows the correspondence between the access areas and physical addresses for each bus mode.

■ Memory Space in Each Bus Mode

Figure 7.1-2 Relationship between Access Areas and Physical Addresses for Each Bus Mode

Model Address #1 Address #2 Address #3

MB90437L(S) *1 FF0000H 002000H 000900H

MB90F438L(S)/438L(S) FE0000H 002000H 001100H

MB90F439(S)/439(S) FC0000H 002100H 001900H

MB90V540G (FC0000H) 002100H 002100H

*1: Under development

FFFFFFH

Address #1

010000H

ROM area (FF bank image)

003900H

Address #3

Address #2

RAM

000100H0000C0H

000000H

Single chip

ROM area

ROM area (FF bank image)

RAM RAM

Internal ROM, external bus External ROM, external bus

: Internal

: External

: No access

ROM area

I/O I/O I/O

I/O I/O I/O

004000H

127


■ Recommended Setting

Table 7.1-5 "Example of Recommended Settings for Mode Pins and Mode Data" lists anexample of recommended settings for mode pins and mode data.

External pins have signal functions that depend on each mode.

Table 7.1-5 Example of Recommended Settings for Mode Pins and Mode Data

Sample setting MD1 MD1 MD0 M1 M0 S0

Single chip 0 1 1 0 0 x

Internal ROM and external bus mode, 16-bit bus 0 1 1 0 1 1

Internal ROM and external bus mode, 8-bit bus 0 1 1 0 1 0

External ROM and external bus mode, 16-bit bus, vector 16 bus width

0 0 1 1 0 1

External ROM and external bus mode, 8-bit bus 0 0 0 1 0 0

Table 7.1-6 External Pin Functions for Each Mode

Pin name

Function

Single chipExternal bus expansion Flash

programming8 bits 16 bits

P07 to 00

Port

AD07 to 00 D07 to 00

P17 to 10 A15 to 08 AD15 to 08 A15 to 08

P27 to 20 A23 to 16* A07 to 00

P30 ALE A16

P31 RD CEX

P32 WR * WRL * OEX

P33 Port WRH * PGMX

P34 HRQ* Unused

P35 HAK *

P36 RDY*

P37 CLK*

Note: The upper address output pins and the WRL/WR, WRH, HRQ, HAK, RDY, and CLK pins can be used as ports through function selection. See Section 7.2 "External Memory Access (Bus Pin Control Circuit)" for details.

128

7.2 External Memory Access (Bus Pin Control Circuit)


The external bus pin control circuit controls the external bus pins for external expansion of the CPU address and data buses.

■ External Memory Access (Bus Pin Control Circuit)

The following address, data, and control signals are used to access external memory andperipherals of the device:

• CLK (P37): Machine cycle clock (KBP) output pin

• RDY (P36): External ready input pin

• WRH (P33): Write signal for upper 8 bits of data bus

• WRL/WR (P32): Write signal for lower 8 bits of data bus in 16-bit access mode, for 8-bit access mode

• RD (P31): Read signal

• ALE (P30): Address latch enable signal

The external bus pin control circuit is used to control the external bus pins to enable externalexpansion of the CPU address and data buses.

■ Block Diagram of External Memory Access

Figure 7.2-1 External Bus Controller

P3P2

P1 P3P0

P0 data P0

P0 direction

RB

Data control

Address control

Access controlAccess control

129


7.2.1 External Memory Access (External Bus Pin Control Circuit) Registers

External memory access (external bus pin control circuit) uses the following three types of registers:• Automatic ready function selection register• External address output control register• Bus control signal selection register

■ External Memory Access Registers

Figure 7.2-2 External memory access (external bus pin control circuit) registers

Automatic ready function selection register

15 14 13 12 11 10 9 8

Address:0000A5H IOR1 IOR0 HMR1 HMR0 LMR1 LMR0 ARSR

Read/write (W) (W) (W) (W) (-) (-) (W) (W)Initial value (0) (0) (1) (1) (-) (-) (0) (0)

External address output control register

7 6 5 4 3 2 1 0

Address:0000A6H E23 E22 E21 E20 E19 E18 E17 E16 HACR

(W) (W) (W) (W) (W) (W) (W) (W)Initial value (0) (0) (0) (0) (0) (0) (0) (0)

Bus control signal selection register

15 14 13 12 11 10 9 8

Address:0000A7H CKE RYE HDE IOBS HMBS WRE LMBS ECSR

(W) (W) (W) (W) (W) (W) (W) (-)Initial value (0) (0) (0) (0) (0) (0) (0) (-)

Read/write

Read/write

Bit No.

Bit No.

Bit No.

130


7.2.2 Automatic Ready Function Selection Register (ARSR)

The automatic ready function selection register (ARSR) is used to set the automatic wait time for memory access for each area during external access.

■ Automatic Ready Function Selection Register (ARSR)

Figure 7.2-3 Automatic Ready Function Selection Register Configuration

[Bits 15 and 14] IOR1, IOR0

The IOR1 and IOR0 bits are used to specify the automatic wait function for external accessto the area from 0000C0H to 0000FFH. Table 7.2-1 "IOR1 and IOR0 (Automatic WaitFunction Specification Bit) Functions" lists the settings that can be specified by combiningthe IOR1 and IOR0 bits.

[Bits 13 and 12] HMR1, HMR0

The HMR1 and HMR0 bits are used to specify the automatic wait function for externalaccess to the area from 800000H to FFFFFFH. Table 7.2-2 "HMR1 and HMR0 (AutomaticWait Function Specification Bit) Functions" lists the settings that can be specified bycombining the HMR1 and HMR0 bits.

Automatic ready function selection register

15 14 13 12 11 10 9 8

Address:0000A5H IOR1 IOR0 HMR1 HMR0 LMR1 LMR0 ARSR

Read/write (W) (W) (W) (W) (-) (-) (W) (W)Initial value (0) (0) (1) (1) (-) (-) (0) (0)

Bit No.

Table 7.2-1 IOR1 and IOR0 (Automatic Wait Function Specification Bit) Functions

IOR1 IOR0 Function

0 0 Automatic wait disabled [initial value]

0 1 Automatic wait of 1 cycle is inserted for external access

1 0 Automatic wait of 2 cycles is inserted for external access


Table 7.2-2 HMR1 and HMR0 (Automatic Wait Function Specification Bit) Functions

HMR1 HMR0 Function

0 0 Automatic wait disabled



1 1 Automatic wait of 3 cycles is inserted for external access [initial value]

131


[Bits 9 and 8] LMR1, LMR0

The LMR1 and LMR0 bits are used to specify the automatic wait function for external accessto the areas between 002000H and 7FFFFFH. Table 7.2-3 "LMR1 and LMR0 (Automatic WaitFunction Specification Bit) Functions" lists the settings that can be specified by combiningthe LMR1 and LMR0 bits.

Table 7.2-3 LMR1 and LMR0 (Automatic Wait Function Specification Bit) Functions

LMR1 LMR0 Function

0 0 Automatic wait disabled [initial value]




132


7.2.3 External Address Output Control Register (HACR)

The external address output control register (HACR) controls the external output of addresses (A19 to A16). The bits correspond to addresses A19 to A16, which control address output pins, as shown in Figure 7.2-4 "External Address Output Control Address Configuration".

■ External Address Output Control Register (HACR)

Figure 7.2-4 External Address Output Control Address Configuration

The HACR register controls output of addresses (A23 to A16) to the external circuit. Theaddress output pin is controlled as follows with the eight bits that correspond to address bitsA32 to A16.

The HACR register cannot be accessed when the device is in single-chip mode, since all pinsfunction as I/O ports whatever the value of this register.

All bits of this register are write-only bits, and the value read from the bits is 1.

External address output control register

7 6 5 4 3 2 1 0

Address:0000A6H E23 E22 E21 E20 E19 E18 E17 E16 HACR

(W) (W) (W) (W) (W) (W) (W) (W)Initial value (0) (0) (0) (0) (0) (0) (0) (0)Read/write

Bit No.

Table 7.2-4 External Address Output Control Register (E16 to E32 bits) Functions

0 The corresponding pin is used for address output (AXX) [initial value].

1 The corresponding pin is used as an I/O port (PXX).

133


7.2.4 Bus Control Signal Selection Register (ECSR)

The bus control signal selection register sets the bus operation control function in external bus mode. This register cannot be accessed when the device is in single-chip mode, since all pins function as I/O ports whatever the value of this register. All bits of the bus control signal selection register are write-only bits, and the value from the bits is 1.

■ Bus Control Signal Selection Register (ECSR)

Figure 7.2-5 Bus Control Signal Selection Register Configuration

[Bit 15] CKE

The CKE bit controls output of the external clock signal pin (CLK), as shown in Table 7.2-5"CKE (External Clock (CLK) Output Control Bit) Functions".

[Bit 14] RYE

The RYE bit controls input of the external ready (RDY) signal pin, as shown in Table 7.2-6"RYE (External Ready (RDY) Input Control Bit) Functions".

[Bit 13] HDE

The HDE bit specifies that input-output of hold signals is enabled. The hold request inputsignal (HRQ) and hold acknowledge output signal (HAK) are controlled according to thesetting of the HDE bit, as shown in Table 7.2-7 "HDE (Hold Signal Input-Output EnableSpecification Bit) Functions".

Bus control signal selection register

15 14 13 12 11 10 9 8

Address:0000A7H CKE RYE HDE IOBS HMBS WRE LMBS ECSR

(W) (W) (W) (W) (W) (W) (W) (-)Initial value (0) (0) (0) (0) (0) (0) (0) (-)Read/write

Bit No.

Table 7.2-5 CKE (External Clock (CLK) Output Control Bit) Functions

0 I/O port (P37) operation (clock output disabled) [initial value]

1 Clock signal (CLK) output enabled

Table 7.2-6 RYE (External Ready (RDY) Input Control Bit) Functions

0 I/O port (P36) operation (external RDY input disabled) [initial value]

1 External ready (RDY) input enabled

Table 7.2-7 HDE (Hold Signal Input-Output Enable Specification Bit) Functions

0 I/O port (P35, P34) operation (hold function input-output disabled) [initial value]

1 Hold request (HRQ) input/hold acknowledge (HAK) output enabled

134


[Bit 12] IOBS

The IOBS bit is used to specify the bus width for external access to the area from 0000C0Hto 0000FFH in external 16-bit data bus mode Control is based on the setting of this bit, asshown in Table 7.2-8 "IOBS (Bus Width Specification Bit)".

[Bit 11] HMBS

The HMBS bit is used to specify the bus width for external access to the area from 800000Hto FFFFFFH in external 16-bit data bus mode. Control is based on the setting of this bit, asshown in Table 7.2-9 "HMBS (Bus Width Specification Bit".

[Bit 10] WRE

The WRE bit controls output of external write signals (both WRH and WRL pins in external16-bit data bus mode and WR pin in external 8-bit data bus mode), as shown in Table 7.2-10"WRE (External Write Signal Output Control Bit) Functions".

In external 8-bit data bus mode, P33 functions as the I/O port regardless of the setting valueof this bit.

Table 7.2-8 IOBS (Bus Width Specification Bit)

0 16-bit bus width access [initial value]

1 8-bit bus width access

Table 7.2-9 HMBS (Bus Width Specification Bit)



Table 7.2-10 WRE (External Write Signal Output Control Bit) Functions

0 I/O port (P33, P32) operation (write signal output disabled) [initial value]

1 Write strobe signal (WRH/WRL or WR only) output enabled

135


[Bit 9] LMBS

The LMBS bit is used to specify the bus width for external access to the area from 002000Hto 7FFFFFH in external 16-bit data bus mode. Control is based on the setting of this bit, asshown in Table 7.2-11 "LMBS (Bus Width Specification Bit)".

Notes:

• To use the WRE bit to enable the WR, WRH, and WRL functions in external 16-bit data busmode, place P33 and P32 in input mode (set bits 3 and 2 of the DDR3 register to 0).

• To use the WRE bit to enable the WR function in external 8-bit data bus mode, place P32 ininput mode (set bit 2 of the DDR3 register to 0).

• If the RYE and HDE bits are used to enable the RDY and HRQ signals, the I/O port functionof the port is also enabled. Be sure to write 0 (input mode) to the DDR3 register thatcorresponds to the port.

Table 7.2-11 LMBS (Bus Width Specification Bit)



136

7.3 External Memory Access Control Signal Operation


If the ready function is not used, external memory is accessed in three cycles. The 8-bit bus width access function is used to read and write the 8-bit width peripheral chip when the 8- and 16-bit width peripheral chips are connected together to the external bus.

■ External Memory Access Control Signal

The HMBS, LMBS, and IOBS bits are used to specify whether 16-bit bus width access or 8-bitbus width access is to be used in external 16-bit data bus mode.

Actually, bus operation may not be performed by providing only address output and assertoutput of the ALE signal without asserting RD, WR, WRL, and WRH. Be sure that access to aperipheral chip using only the ALE signal is not executed.

Figure 7.3-1 Access Timing Chart for External 8-bit data bus mode)

Read Write Read

P37/CLK

P33/WRH

P32/WRL/WR

P31/RD

P30/ALE

P27 to 20/A23 to 16

P17 to 10/A15 to 08

P07 to 00/AD07 to 00

(Port data)

Read address

Read address

Read address

Read data

Write address

Write address

Read address

Read address

Read address

Write data

Write address

137


Figure 7.3-2 Access Timing Chart for External 16-bit data bus mode (At 16-bit bus width access, 8-bit bus width access)

8-bit bus width byte readEven address byte read

P37/CLK

P33/WRH

P32/WRL/WR

P31/RD

P30/ALE

P27 to 20/A23 to 16 Read address Read address

P17 to 10/AD15 to 08 Read address Invalid (Undefined)

P07 to 00/AD07 to 00

Write data

Odd address byte writeP37/CLK

P33/WRH

P32/WRL/WR

P31/RD

P30/ALE

P27 to 20/A23 to 16

P17 to 10/AD15 to 08

P07 to 00/AD07 to 00 Invalid

Even address word read Even address word write

P37/CLK

P33/WRH

P32/WRL/WR

P31/RD

P30/ALE

P27 to 20/A23 to16

P17 to 10/AD15 to 08

P07 to 00/AD07 to 00

Read address

Read address

Read address

Write address

Write address

Write address

Read data

Read address

Read address

Odd address byte read

Read address

Read data

Write address

Write address

Write address

Write data

(Undefined)

Read address

Read address

Read address

Read address

Read address

Read address

Write dataRead data

Read address

Read address

Read address

Write address

Write address

Write address

8-bit bus width byte writeEven address byte write

Note: Set the external circuit so that data is always read in word mode. The setting of P36/RDY pin or the automatic ready function selection register (ARSR) enables access to low-speed memory and peripheral circuits.

138


7.3.1 Ready Function

The setting of P36/RDY pin or the automatic ready function selection register (ARSR) enables access to the low-speed memory and peripheral circuits.If the RYE bit of the bus control signal selection register (EPCR) is set to 1, the wait cycle is entered to enable extension of the access cycle while the L level is input to P36/RDY signal during access to the external circuit.

■ Ready Function

Figure 7.3-3 Timing Chart for Ready Function

Even address word read

P37/CLK

P33/WRH

P32/WRL/WR

P31/RD

P30/ALE

P27 to 20/A23 to 16 Read address

P17 to 10/AD15 to 08

P07 to 00/AD07 to 00

P36/RDY

RDY pin fetch

Even address word write

P37/CLK

P33/WRH

P32/WRL/WR

P31/RD

P30/ALE

P27 to 20/A23 to 16

P17 to 10/AD15 to 08

P07 to 00/AD07 to 00

Write data

Read address

Read address

Even address word write

Write address

Write address

Write address

Write dataRead data

Write address

Write address

Write address

Even address word read

Read address

Read address

Read address

Cycle extended by auto ready

139


The MB90435 series has two types of auto ready functions for external memory access. Theauto ready function can automatically insert 1 to 3 wait cycles to extend the access cyclewithout an external circuit for access to the external areas at lower addresses 002000H to7FFFFFH and at upper addresses 800000H to FFFFFFH. This function is activated according tothe setting of the LMR1 and LMR0 bits (external areas at lower addresses) of ARSR and theHMR1 and HMR0 bits (external area at upper addresses) of ARSR.

The MB90435 series also has an auto ready function for I/O that is independent of the autoready function for memory. When the IOR1 and IOR0 bits of the ARSR register are set to 0, 1to 3 wait cycles can be automatically inserted to extend the access cycle without an externalcircuit for access to the external area from addresses 0000C0H to 0000FFH.

If the RYE bit of the EPCR is set to 1 and the L level is continues to be input to P36/RDY pinafter the wait cycle using the auto ready function for external memory and for external I/O iscompleted, the wait cycle continues.

140


7.3.2 Hold Function

If the HDE bit in the bus control signal selection register (EPCR) is set to 1, the external bus hold function specified by the P34/HRQ and P35/HAK pins is enabled.

■ Hold Function

If the high level is applied to the P34/HRQ pin, the hold state is set up at termination of a CPUinstruction (for a string instruction, at termination of 1-element data processing). The P35/HAKpin outputs the low level to place the following pins in a high-impedance state:

• Address output: P27/A23 to P20/A16

• Address/data I/O: P17/D15 to P00/D00

• Bus control signal: P30/ALE, P31/RD, P32/WRL/WR, P33/WRH

Thus, an external bus can be used from a device external circuit. When the low level is input tothe P34/HRQ pin, the P35/HAK pin outputs the high-level, thereby restoring the external pinstate and restarting the CPU operation. In the stop status, hold request input is not accepted.

Figure 7.3-4 "Hold Timing (in an External Bus 16-Bit Mode)" shows the hold timing (in anexternal 16-bit bus mode).

Figure 7.3-4 Hold Timing (in an External Bus 16-Bit Mode)

P37/CLK

P34/HRQ

P35/HAK

P33/WRH

P32/WRL/WR

P31/RD

P30/ALE

P27 to 20/A23 to 16

P17 to 10/AD15 to 08

P07 to 00/AD07 to 00

Read cycle Hold cycle Write cycle

(Address)

(Address)

(Address)

(Address)

Read data Write data

141


142

CHAPTER 8 I/O PORTS

This chapter explains the functions and operations of the I/O ports.

8.1 "I/O Port"

8.2 "I/O Port Registers"

143

CHAPTER 8 I/O PORTS

8.1 I/O Ports

Each pin of the ports can be specified as input or output using the port direction register (DDR) if the corresponding peripheral does not use the pin.

■ Outline of I/O ports

When a pin is specified as input, the logic level at the pin is read. When a pin is specified asoutput, the data register value is read. The above also applies to a read operation for the read-modify-write instructions.

However, When a pin is used as an output for another peripheral, the logic level at the pin isread regardless of the value of the data register.

It is generally recommended that the read-modify-write instructions not be used for setting thedata register before a port is set for output and the output of the peripheral resource is switchedoff. The reason is that a read-modify-write instruction in this case reads the logic level at theport instead of the register value.

Figure 8.1-1 "I/O Port Block Diagram" is a block diagram of the I/O ports.

Figure 8.1-1 I/O Port Block Diagram

Internal data bus

Data register read

Data register write

Direction register write

Direction register read

Data register

Direction register

Pin

144

8.2 I/O Port Registers


Figure 8.2-1 "I/O Port Registers" shows the bit configuration of the I/O port registers.

■ I/O Port Registers

Figure 8.2-1 I/O Port Registers

15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0

Address 000000H

Address 000001H

Address 000002H

Address 000003H

Address 000004H

Address 000005H

Address 000006H

Address 000007H

Address 000008H

Address 000009H

Address 00000AH

Address 000010H

Address 000011H

Address 000012H

Address 000013H

Address 000014H

Address 000015H

Address 000016H

Address 000017H

Address 000018H

Address 000019H

Address 00001AH

Address 00001CH

Address 00001DH

Address 00001EH

Address 00001FH

Address 00001BH

P07 P06 P05 P04 P03 P02 P01 P00

P17 P16 P15 P14 P13 P12 P11 P10

P27 P26 P25 P24 P23 P22 P21 P20

P37 P36 P35 P34 P33 P32 P31 P30

P47 P46 P45 P44 P43 P42 P41 P40

P54 P53 P52 P51 P50

P67 P66 P65 P64 P63 P62 P61 P60

P77 P76 P75 P74 P73 P72 P71 P70

P87 P86 P85 P84 P83 P82 P81 P80

P97 P96 P95 P94 P93 P92 P91 P90

PA0

Bit No.

Bit No.

Bit No.

Bit No.

Port 0 data register (PDR0)










Port A data register (PDRA)

15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0

D07 D06 D05 D04 D03 D02 D01 D00

D17 D16 D15 D14 D13 D12 D11 D10

D27 D26 D25 D24 D23 D22 D21 D20

D37 D36 D35 D34 D33 D32 D31 D30

D47 D46 D45 D44 D43 D42 D41 D40

D54 D53 D52 D51 D50

D67 D66 D65 D64 D63 D62 D61 D60

D77 D76 D75 D74 D73 D72 D71 D70

D87 D86 D85 D84 D83 D82 D81 D80

D97 D96 D95 D94 D93 D92 D91 D90

DA0

Port 0 direction register (DDR0)










Port A direction register (DDRA)

15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0

PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00



Port 0 pull-up control register (PUCR0)




15 14 13 12 11 10 9 8

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Port 6 analog input enable register (ADER)

P57 P56 P55

D57 D56 D55


145

CHAPTER 8 I/O PORTS

8.2.1 Port Data Register (PDR)

Figure 8.2-2 "Port Data Registers (PDR)" shows the detailed bit configuration of the port data register (PDR).

■ Port data Register (PDR)

Figure 8.2-2 Port Data Registers (PDR)

7 6 5 4 3 2 1 0 Initial value AccessPDR0

P07 P06 P05 P04 P03 P02 P01 P00 Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

R/WAddress : 000000H

Address : 000001H

15 14 13 12 11 10 9 8

PDR1 P17 P16 P15 P14 P13 P12 P11 P10 R/W

7 6 5 4 3 2 1 0PDR2

P27 P26 P25 P24 P23 P22 P21 P20 R/W

15 14 13 12 11 10 9 8PDR3

P37 P36 P35 P34 P33 P32 P31 P30 R/W

7 6 5 4 3 2 1 0PDR4

P47 P46 P45 P44 P43 P42 P41 P40 R/W

15 14 13 12 11 10 9 8PDR5

P54 P53 P52 P51 P50 R/W

7 6 5 4 3 2 1 0PDR6

P67 P66 P65 P64 P63 P62 P61 P60 R/W

15 14 13 12 11 10 9 8PDR7

P77 P76 P75 P74 P73 P72 P71 P70 R/W

7 6 5 4 3 2 1 0PDR8

P87 P86 P85 P84 P83 P82 P81 P80 R/W

15 14 13 12 11 10 9 8PDR9

P97 P96 P95 P94 P93 P92 P91 P90 R/W

7 6 5 4 3 2 1 0PDRA

PA0 R/W

Bit No.

Bit No.

Address : 000002H

Bit No.

Address : 000003H

Bit No.

Address : 000004H

Bit No.

Address : 000005H

Bit No.

Address : 000006H

Bit No.

Address : 000007H

Bit No.

Address : 000008H

Bit No.

Address : 000009H

Bit No.

Address : 00000AH

Bit No.

P57 P56 P55

*

*

*

*

*

*

*

*

*

*

*

*: Note the following differences between R/W for the I/O ports and R/W for memory:- Input mode

Read: The level at the corresponding pin is read.Write: Data is written to an output latch.

- Output modeRead: The pin output value is read.Write: Data is written to an output latch and output to the corresponding pin.

146


8.2.2 Port Direction Register (DDR)

Figure 8.2-3 "Port Direction Registers (DDR)" shows the bit configuration of the port direction register (DDR).

■ Port Direction Register (DDR)

Figure 8.2-3 Port Direction Registers (DDR)

7 6 5 4 3 2 1 0 Initial value Access

DDR0 D07 D06 D05 D04 D03 D02 D01 D00 00000000B R/WAddress : 000010H

15 14 13 12 11 10 9 8

DDR1 D17 D16 D15 D14 D13 D12 D11 D10 00000000B R/W

7 6 5 4 3 2 1 0

DDR2 D27 D26 D25 D24 D23 D22 D21 D20 00000000B R/W

15 14 13 12 11 10 9 8

DDR3 D37 D36 D35 D34 D33 D32 D31 D30 00000000B R/W

7 6 5 4 3 2 1 0

DDR4 D47 D46 D45 D44 D43 D42 D41 D40 00000000B R/W

15 14 13 12 11 10 9 8

DDR5 D54 D53 D52 D51 D50 00000000B R/W

7 6 5 4 3 2 1 0

DDR6 D67 D66 D65 D64 D63 D62 D61 D60 00000000B R/W

15 14 13 12 11 10 9 8

DDR7 D77 D76 D75 D74 D73 D72 D71 D70 00000000B R/W

7 6 5 4 3 2 1 0

DDR8 D87 D86 D85 D84 D83 D82 D81 D80 00000000B R/W

15 14 13 12 11 10 9 8

DDR9 D97 D96 D95 D94 D93 D92 D91 D90 00000000B R/W

7 6 5 4 3 2 1 0

DDRA DA0 - - - - - - - 0B R/W

Bit No.

Address : 000011H

Address : 000012H

Address : 000013H

Address : 000014H

Address : 000015H

Address : 000016H

Address : 000017H

Address : 000018H

Address : 000019H

Address : 00001AH

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

D57 D56 D55

When a pin functions as a port, the corresponding pin is controlled as follows:0: Input mode1: Output modeThe bits are set to 0 by a reset.

147

CHAPTER 8 I/O PORTS

8.2.3 Pull-up Control Register (PUCR)

Figure 8.2-4 "Bit Configuration of Pull-up Control Register (PUCR)" shows the bit configuration of the pull-up control register (PUCR), and Figure 8.2-5 "lock Diagram of Pull-up Control Register (PUCR)" is the block diagram.

■ Pull-up Control Register (PUCR)

Figure 8.2-4 Bit Configuration of Pull-up Control Register (PUCR)

Address : 00001CH PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00

15 14 13 12 11 10 9 8

Address : 00001DH PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10

Address : 00001EH PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20

Bit No.Pull-up control register

7 6 5 4 3 2 1 0

Address : 00001FH PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30

Bit No.

Bit No.

Bit No.

Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value

Read/writeInitial value



(0) (0) (0) (0) (0) (0) (0) (0)(R/W)

PUCR0

PUCR1

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (0) (0)

(R/W)

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (0) (0)

(R/W)

PUCR2

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (0) (0)

(R/W)

PUCR3

7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8

148


■ Block Diagram of Pull-up Control Register (PUCR)

Figure 8.2-5 Block Diagram of Pull-up Control Register (PUCR)

Note:

In input mode, the pull-up resistor is controlled.

0: No pull-up resistor in input mode

1: Pull-up resistor in input mode

In output mode, this register has no meaning (no pull-up resistor).

The direction register (DDR) determines the input-output mode.

In hardware standby mode and stop mode (SPL=1), the state with no pull-up resistor isentered (high impedance).

If the port is used as an external bus, this function is disabled and data is not written to theregister.

Pull-up resistor (about 50KΩ)

Data register Port input-output

Direction register

Resistor register

Internal data bus

149

CHAPTER 8 I/O PORTS

8.2.4 Analog Input Enable Register (ADER)

Figure 8.2-6 "Bit Configuration of Analog Input Enable Register (ADER)" shows the bit configuration of the analog input enable register (ADER).

■ Analog Input Enable Register (ADER)

Figure 8.2-6 Bit Configuration of Analog Input Enable Register (ADER)

The analog input enable register (ADER) controls the pins of port 6 as follows:

• 0: Port input mode

• 1: Analog input mode

If an external pin is used as analog input of the A/D converter, set the corresponding bit to 1.

15 14 13 12 11 10 9 8

Address : 00001BH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Read/write

Bit No.

(1) (1) (1) (1) (1) (1) (1) (1)Initial value

Analog Input Enable Register

ADER

150

CHAPTER 9 TIMEBASE TIMER

This chapter explains the functions and operations of the timebase timer.

9.1 "Outline of Timebase Timer"

9.2 "Timebase Timer Control Register (TBTC)"

9.3 "Operations of Timebase Timer"

151


9.1 Outline of Timebase Timer

The timebase timer consists of an 18-bit timer and a circuit that controls an interval interrupt. The timebase timer uses the main clock signal regardless of the MSC and SCS bits of the clock selection register (CKSCR).

■ Timebase Timer Registers

Figure 9.1-1 Timebase Timer Registers

Time base timer control register

15 14 13 12 11 10 9 8 Bit No.

Address : 0000A9H Reserved TBIE TBOF TBR TBC1 TBC0 TBTC

Read/write (-) (-) (R/W) (R/W) (R/W) (R/W)

Initial value (1) (-) (-) (0) (0) (0) (0)

(R/W)

(1)(R/W)

152

9.1 Outline of Timebase Timer

■ Block Diagram of Timebase Timer

Figure 9.1-2 Block Diagram of Timebase Timer

Main clock

TBTC212 Clock input

TBC1 214Selector 216 Timebase timer

TBC0 219

TBTRES 214 216 219

TBR

TBIE AND

TBOF

Time base interrupt

WDTC

WT1 2-bit counter Watch-dog reset generation circuitSelector OF WDGRST

WT0 CLR CLR To internal reset generation circuit

WTE

PONR From power-on generation

STBR From hardware standby control circuit

WRST

ERST RST pin

SRST From RST bit of LPMCR register

Selector

Clock input

Watch timer

WTRES

214 215213210

WTC

WDCS AND

WTR

WTIE

WTOF

SCE

WTC2

WTC0

SRQ

AND SRQ

SRQ

Timer interrupt

WDTC

Subclock/4

SCMPower-on reset*Subclock stop

Inte

rnal

dat

a bu

s

212

WTC1

153


9.2 Timebase Timer Control Register (TBTC)

The timebase timer control register (TBTC) controls the operation of the timebase timer and the interval interrupt time.

■ Timebase Timer Control Register (TBTC)

Figure 9.2-1 Timebase Timer Control Register (TBTC)

[Bit 15] Reserved bit

Ensure that "1" is always written to this bit.

[Bits 14 and 13] Unused bits

Bits 14 and 13 are unused.

[bit 12] TBIE

This bit is used to enable interval interrupts based on the timebase timer. Writing "1" to thisbit enables interrupts, and writing "0" disables interrupts. This bit is initialized to "0" upon areset. This bit is readable and writable.

[bit 11] TBOF

This is an interrupt request flag for the timebase timer. While the TBIE bit is "1", an interruptrequest is issued when "1" is written to TBOF. This bit is set to "1" for each interval specifiedwith the TBC1 and TBC0 bits.

This bit is cleared by writing "0", transition to stop or hardware standby mode, or a reset.Writing "1" has no effect.

"1" is always read by a read-modify-write instruction.

[bit 10] TBR

This bit clears all bits of the timebase timer counter to "0".

Writing "0" clears the timebase counter.

Writing "1" has no effect.

"1" is always read from this bit.

Time base timer control register

15 14 13 12 11 10 9 8 Bit No.

Address : 0000A9H Reserved TBIE TBOF TBR TBC1 TBC0 TBTC

Read/write (-) (-) (R/W) (R/W) (R/W) (R/W)

Initial value (1) (-) (-) (0) (0) (0) (0)

(R/W)

(1)(R/W)

154

9.2 Timebase Timer Control Register (TBTC)

[bits 9 and 8] TBC1 and TBC0

These bits are used to set the timebase timer interval. These bits are initialized to 00 by areset. These bits can be read and written to.

Table 9.2-1 "Settings for Timebase Timer Interval" lists the settings for the timebase timerinterval.

Table 9.2-1 Settings for Timebase Timer Interval

TBC1 TBC0 Interval at 4 MHz source oscillation

0 0 1.024 ms

0 1 4.096 ms

1 0 16.384 ms

1 1 131.072 ms

155


9.3 Operations of Timebase Timer

The timebase timer functions as a watch-dog timer clock source, timer for waiting for main clock and PLL clock oscillation to stabilize, and interval timer for generating interrupts at specified intervals.

■ Timebase Timer

The timebase timer consists of an 18-bit counter that counts the pulses of the oscillation clockused to generate the machine clock. While the oscillation clock is input, the timebase timerkeeps counting.

The timebase timer is cleared by a power-on reset, transition to stop or hardware standbymode, or transition from the main clock to the PLL clock by writing data to the MCS bit of theclock selection register (CKSCR). The timebase timer is also cleared by transition from themain clock to the subclock by writing data to the SCS bit of the clock selection register (CKSCR)or writing 0 to the TBR bit of the timebase timer control register (TBTC).

The watch-dog counter and interval interrupt function using output from the timebase timer areaffected by clearing the timebase counter.

■ Interval Interrupt Function of Timebase Timer

Interrupts are generated at specified intervals according to the carry signals of the timebasecounter. The TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of thetimebase timer control register (TBTC). This flag is set by using as a reference the last time thatthe timebase timer was cleared.

On transition from main clock mode to PLL clock mode, the timebase timer is cleared becausethe timebase timer is used as a timer that waits for PLL clock oscillation to stabilize.

On transition from oscillation clock mode to subclock mode, the timebase timer is clearedbecause the timebase timer is used as a timer that waits for oscillation of the oscillation clock tostabilize.

On transition to stop mode and hardware standby mode, the TBOF flag is immediately clearedwhen mode transition is complete because the timebase timer is used as a timer that waits untiloscillation to stabilize upon recovery.

156

CHAPTER 10 WATCH-DOG TIMER

This chapter explains the functions and operations of the watch-dog timer.

10.1 "Outline of Watch-dog Timer"

10.2 "Watch-dog Timer Control Register (WDTC)"

10.3 "Watch-dog Timer Operation"

157


10.1 Outline of Watch-dog Timer

The watch-dog timer consists of a 2-bit watch-dog counter that uses the carry signal of the 18-bit timebase timer or 15-bit watch timer as a clock source, control register, and watch-dog reset controller.

■ Watch-dog Timer Register

Figure 10.1-1 Watch-dog Timer Register

7 6 5 4 3 2 1 0

Address : 0000A8H PONR STBR WRST ERST SRST WTE WT1 WT0 WDTC

(R) (R) (R) (R) (R) (W) (W) (W)

Initial value (X) (X) (X) (X) (X) (1) (1) (1)

Watch-dog timer control register

Bit No.

Read/write

158

10.1 Outline of Watch-dog Timer

■ Watch-dog Timer Block Diagram

Figure 10.1-2 Block Diagram of Watch-dog Timer

Main clock

TBTC212 Clock input

TBC1 214Selector 216 Timebase timer

TBC0 219

TBTRES 214 216 219

TBR

TBIE AND

TBOF

Time base interrupt

WDTC

WT1 2-bit counter Watch-dog reset generation circuitSelector OF WDGRST

WT0 CLR CLR To internal reset generation circuit

WTE

PONR From power-on generation

STBR From hardware standby control circuit

WRST

ERST RST pin

SRST From RST bit of LPMCR register

Selector

Clock input

Watch timer

WTRES

214 215213210

WTC

WDCS AND

WTR

WTIE

WTOF

SCE

WTC2

WTC0

SRQ

AND SRQ

SRQ

Timer interrupt

WDTC

Subclock/4

SCMPower-on reset*Subclock stop

Inte

rnal

dat

a bu

s

212

WTC1

159


10.2 Watch-dog Timer Control Register (WDTC)

The watch-dog timer control register (WDTC) consists of the bits that control the watch-dog timer and bits that identify reset causes.

■ Watch-dog Timer Control Register (WDTC)

Figure 10.2-1 Watch-dog Timer Control Register (WDTC)

[bits 7 to 3] PONR, STBR, WRST, ERST, and SRST

These flags indicate the reset causes. The flags are set upon a reset as described in Table10.2-1 "Reset Cause Bits and Reset Causes".

All bits are cleared to "0" after the WDTC register is read. These bits are read-only bits. Atpower-on, the values of reset cause bits other than PONR bit are not defined. When thePONR bit is 1, ensure that the values of the bits other than PONR bit are ignored.

[bit 2] WTE

While the watch-dog timer is stopped, writing 0 to this bit activates the watch-dog timer.Subsequently, writing 0 clears the watch-dog timer counter. Writing 1 has no effect.

The watch-dog timer is stopped by power-on, hardware standby, or reset by watch-dogtimer. "1" is always read from this bit.

7 6 5 4 3 2 1 0

Address : 0000A8H PONR STBR WRST ERST SRST WTE WT1 WT0 WDTC

(R) (R) (R) (R) (R) (W) (W) (W)

Initial value (X) (X) (X) (X) (X) (1) (1) (1)

Watch-dog timer control register

Bit No.

Read/write

Table 10.2-1 Reset Cause Bits and Reset Causes

Reset cause PONR STBR WRST ERST SRST

Power-on 1 - - - -

Hardware standby * 1 * * *

Watch-dog timer * * 1 * *

External pin * * * 1 *

RST bit * * * * 1

(*: The previous value is maintained.)

160

10.2 Watch-dog Timer Control Register (WDTC)

[bits 1 and 0] WT1 and WT0

These bits are used to select the watch-dog timer interval.

Only the data items written during watch-dog timer activation are valid. Data items that arewritten at any other time are ignored. In the two clocks system parts, the clock signal inputto the watch-dog timer is selected according to the values of the WDCS bit of the watch timercontrol register (WTC). Table 10.2-2 "Access to WT1 and WT0 (Read-only)" lists the settingfor the interval.

Table 10.2-2 Access to WT1 and WT0 (Read-only)

WDCS WT1 WT0Interval (match clock: 4 MHz)

Minimum Maximum

1 0 0 About 3.58ms About 4.61ms




0 *1 0 0 About 0.457s About 0.576s

0 *1 0 1 About 3.584s About 4.608s

0 *1 1 0 About 7.167s About 9.216s

0 *1 1 1 About 14.336s About 18.432s

*1: Only the two clocks system parts.Note:

The maximum interval assumes that the timebase counter is not reset during watch-dog operation.

161


10.3 Watch-dog Timer Operation

The watch-dog timer function enables detection of program surge. If 0 is not written to the WTE bit of the watch-dog timer within the specified time due to a program surge, the watch-dog timer issues a watch-dog reset request.

■ Activating the Watch-dog Timer

The watch-dog timer is activated by writing 0 to the WTE bit of the watch-dog timer controlregister (WDTC) while the watch-dog timer is stopped. At the same time, the WT1 and WT0bits are used to set the watch-dog timer interval. Only the interval setting specified duringactivation is valid.

■ Resetting the Watch-dog Timer

When the watch-dog timer is activated, the 2-bit watch-dog counter must be program-cleared.Specifically, 0 must be periodically written to the WTE bit of the watch-dog timer control register(WDTC). The watch-dog timer consists of a 2-bit counter that uses the carry signals of thetimebase timer as a clock source. When the timebase timer is cleared, the watch-dog resetinterval may exceed the setting.

Figure 10.3-1 "Watch-dog Timer Operation" is a diagram of the watch-dog timer operation.

Figure 10.3-1 Watch-dog Timer Operation

■ Stopping the Watch-dog Counter

Once activated, the watch-dog timer is initialized and stopped only by power-on, hardwarestandby, or reset by watch-dog. Reset by an external pin or software merely clears the watch-dog counter without stopping the watch-dog function.

■ Clearing the Watch-dog Counter

The watch-dog counter is cleared by writing 0 to the WTE bit of the watch-dog timer controlregister (WDTC), occurrence of a reset, or transition to sleep mode, stop mode, or holdacknowledge signal.

00 01 10 00 01 10 11 00

Time base

Watch-dog

WTE write

Watch-dog clearWatch-dog reset occurs

Watch-dog activation

162

CHAPTER 11 WATCH TIMER

This chapter explains the functions and operations of the watch timer.Note:

The watch timer can not be used in the one clock system parts.

11.1 "Outline of Watch Timer"

11.2 "Watch Timer Control Register (WTC)"

11.3 "Watch Timer Operation"

163


11.1 Outline of Watch Timer

The watch timer consists of a 15-bit timer and a circuit that controls an interval interrupt. The watch timer uses subclock signals regardless of the MCS bit and SCS bit of the clock selection register (CKSCR).

■ Watch Timer Register

Figure 11.1-1 Watch Timer Control Register (WTC)

7 6 5 4 3 2 1 0

WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(R)

(1) (X) (0) (0) (0) (0) (0) (0)

Address: 0000AAH

Bit No.

Read/write

Initial value

WTC

Watch timer control register

164

11.1 Outline of Watch Timer

■ Block Diagram of Watch Timer

Figure 11.1-2 Block Diagram of Watch Timer

TBTC212

TBC1 214

216

TBC0 219

TBTRES

2-bit counter Watch-dog reset generation circuit

214 216 219

TBR

TBIE AND

TBOF

WDTC

WT1OF WDGRST

Inte

rnal

dat

a bu

s

To internal reset generation circuit

Power-on reset*

Subclock/4

From power-on generation

From hardware standby control circuit

RST pin

From RST bit of LPMCR register

Subclock stop

Main clock

Selector

Clock input

Clock input

Timebase timer

Time base interrupt

Timer interrupt

Selector

SelectorWatch timer

WT0 CLR CLR

WTE

PONR

STBR

WRST

ERST

SRST

WTRES

214 215213210

WTC

WDCS AND

WTR

WTIE

WTOF

SCE

WTC2

WTC0

SRQ

AND SRQ

SRQ

WDTC

SCM

212

WTC1

165


11.2 Watch Timer Control Register (WTC)

The watch timer control register (WTC) controls the operation of the watch timer and the interval interrupt time.

■ Watch Timer Control Register (WTC)

Figure 11.2-1 Watch Timer Control Register (WTC)

[Bit 7] WDCS

The WDCS bit is used to specify whether the clock signal of the watch timer or timebasetimer is used as the input clock of the watch-dog timer when the main clock or PLL clock isselected as the machine clock. When WDCS=0, the clock signal of the watch timer can beselected. When WDCS=1, the clock signal of the timebase timer can be selected. When 1is set in WDCS, the function that selects the main clock or PLL clock uses the timebasetimer output. Functions that include the subclock use output from the watch timer.

This bit is initialized to 1 by a power-on reset.

Note:

If WDCS is set to 1, the watch-dog timer counter may be incremented because the timebasetimer output and watch timer output are asynchronous. If WDCS is set to 1, the watch-dogtimer must be cleared before and after the clock mode is changed.

[Bit 6] SCE

The SCE bit indicates that the subclock oscillation stabilization wait time has elapsed. Whenthis bit is 0, the oscillation stabilization is currently in progress. The oscillation stabilization

time is fixed at 214 cycles (subclock). This bit is initialized to 0 by a power-on reset and stop.

[Bit 5] WTIE

The WTIE bit enables an interval interrupt by the watch timer. When this bit is 1, theinterrupt is enabled. When this bit is 0, the interrupt is disabled. This bit is initialized to 0 bya reset. This bit can be read and written to.

[Bit 4] WTOF

The WTOF bit is the watch timer interrupt flag. When the WTIE bit is 1 and WTOF is set to1, an interrupt request is issued. This bit is set to 1 at each interval specified by the WTC1and WTC0 bits. This bit is cleared by writing 0, transition to stop mode or hardware standbymode, or a reset. Writing 1 has no effect.

During read operation using a read-modify-write instruction, 1 is always read from this bit.

7 6 5 4 3 2 1 0

WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(R)

(1) (X) (0) (0) (0) (0) (0) (0)

Address: 0000AAH

Bit No.

Read/write

Initial value

WTC

Watch timer control register

166

11.2 Watch Timer Control Register (WTC)

[Bit 3] WTR

The WTR bit clears all bits of the watch timer counter to 0. Writing 0 to this bit clears thetimer counter. Writing 1 has no effect. The value read from this bit is always 1.

[Bits 2, 1, and 0] WTC2, WTC1, WTC0

The WTC2, WTC1, and WTC0 bits set the watch timer interval. Table 11.2-1 "Settings forthe Watch Timer Interval" lists the settings for the interval. These bits are initialized to 000by a reset. These bits can be read and written to.

When data is written to these bits, bit 4 (WTOF) should be cleared.

Table 11.2-1 Settings for the Watch Timer Interval

WTC2 WTC1 WTC0 Interval (subclock: 32kHz)

0 0 0 62.5 ms

0 0 1 125 ms

0 1 0 250 ms

0 1 1 500 ms

1 0 0 1.000 s

1 0 1 2.000 s

1 1 0 4.000 s

1 1 1 -

167


11.3 Watch Timer Operation

The watch timer functions as a watch-dog counter clock source, timer for waiting for the subclock oscillation to stabilize, and interval timer for generating interrupts at specified intervals.

■ Watch Timer

The watch timer consists of a 15-bit counter that counts oscillation inputs generated by thesubclock. While the subclock is input, the watch timer keeps counting. The watch timer iscleared by a power-on reset or writing 0 to the WTR bit of the watch timer control register(WTC).

The watch-dog counter and an interval interrupt using the watch timer output are affected byclearing of the timer counter.

■ Interval Interrupt Function of Watch Timer

The interval interrupt function generates interrupts at specified intervals according to the carrysignals of the timer counter. The WTOF flag is set at the intervals specified by the WTC1 andWTC0 bits of the watch timer control register (WTC). This flag is set by using as a reference thelast time that the watch timer was cleared.

On transition to stop or hardware standby mode, the watch timer is used as a timer for subclockoscillation to stabilize upon recovery, and the WTOF flag is immediately cleared upon modetransition.

168

CHAPTER 12 16-BIT I/O TIMER

This chapter explains the functions and operations of the 16-bit I/O timer.

12.1 "Outline of 16-Bit I/O Timer"

12.2 "16-Bit I/O Timer Registers"

12.3 "16-bit Free-running Timer"

12.4 "Output Compare"

12.5 "Input Capture"

169


12.1 Outline of 16-Bit I/O Timer

MB90435 series products contain one 16-bit free-running timer module, two output compare modules, and four input capture modules, and support eight input channels and four output channels. The following sections only describes the 16-bit free-running timer, Output Compare 0/1 and Input Capture 0/1.The remaining modules have the identical functions and the register addresses should be found in the I/O map.

■ 16-bit Free-running Timer

The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. Thevalues output from this timer counter are used as the base timer for input capture and outputcompare.

• Four counter clocks are available.

• Internal clock: φ/4, φ/16, φ/64, φ/256

• An interrupt can be generated upon a counter overflow or a match with compare register 0.

• The counter value can be initialized to "0000H" upon a reset, software clear, or match withcompare register 0.

■ Output Compare (2 Channels per One Module)

The output compare module consists of two 16-bit compare registers, compare output latch, andcontrol register.

When the 16-bit free-running timer value matches the compare register value, the output level isreversed and an interrupt is issued.

❍ The two compare registers can be used independently.

Output pins and interrupt flags corresponding to compare registers

❍ Output pins can be controlled based on pairs of the two compare registers.

Output pins can be reversed by using the two compare registers.

❍ Initial values for output pins can be set.

❍ Interrupts can be generated upon a compare match.

170

12.1 Outline of 16-Bit I/O Timer

■ Input Capture (2 Channels per one Module)

The input capture module consists of two 16-bit capture registers and control registerscorresponding to two independent external input pins. The 16-bit free-running timer value canbe stored in the capture register and an interrupt is issued simultaneously upon detection of anedge of a signal input from an external input pin.

❍ The detection edge of an external input signal can be specified.

Rising, falling, or both edges

❍ Two input channels can operate independently.

❍ An interrupt can be issued upon a valid edge of an external input signal.

The intelligent I/O service can be activated upon an input capture interrupt.

■ Block Diagram of 16-bit I/O Timer

Figure 12.1-1 "Block Diagram of 16-bit I/O Timer" shows a block diagram of the 16-bit I/O timer.

Figure 12.1-1 Block Diagram of 16-bit I/O Timer

OUT0T Q

T Q OUT1

IN0

IN1

Control logic

Interrupt

16-bit free-run timer

16-bit timer

To

each

blo

ck

Clear

Output compare 0

Compare register 0

Inte

rnal

dat

a b

us

Output compare 1

Compare register 1

Input capture 0

Capture register 0

Capture register 1

Edge selection

Edge selectionInput capture 1

171


12.2 16-bit I/O Timer Registers

The 16-bit I/O timer has the following three registers:• 16-bit free-running timer register• 16-bit output compare register• 16-bit input capture register

■ 16-bit I/O Timer Registers

Figure 12.2-1 16-bit I/O Timer Registers

15 0

OCCP0/1

15 0

OCS1

Address : 003928H

00392AH

Address : 000058H

Address : 00006CH TCDTTimer counter data registers

Address : 00006EH TCCS

IPCP0/1

ICS0/1

Address : 003920H

003922H

Address : 00004CH

15 0

7 0

16-bit free-running timer register

16-bit output compare register

16-bit input capture register

Timer counter control status register

Compare registers 0 and 1

Compare control status registers 0 and 1

Input capture data registers 0 and 1

Input capture control status registers 0 and 1

15 0

7 0

OCS0

172

12.3 16-bit Free-running Timer


The 16-bit free-running timer consists of a 16-bit up counter and a control status register. The count values are used as the base timer for the output compares and input captures.• Four counter clock frequencies are available.• An interrupt can be generated upon a counter value overflow.• The counter value can be initialized upon a match with compare register 0,

depending on the mode.

■ 16-bit Free-running Timer Block Diagram

Figure 12.3-1 16-bit Free-running Timer Block Diagram

IVF IVFE STOP MODE CLR CLK1 CLK0

T15toT00

Interrupt request

Comparator 0

Divider

16-bit free-running time Clock

Count value output

Inte

rnal

dat

a bu

s

Machine clock

(TCCS)

φ

173


12.3.1 16-bit Free-running Timer Registers

The data register can read the count value of the 16-bit free-running timer. The counter value is cleared to "0000" upon a reset. The timer value can be set by writing a value to this register. However, ensure that the value is written while the operation is stopped (STOP=1). The data register must be accessed by the word access instructions.

■ Timer Counter Data Register (TCDT)

Figure 12.3-2 Timer Counter Data Register (TCDT)

The 16-bit free-running timer is initialized upon the following factors:

• Reset

• Clear bit (CLR) of control status register

• A match between compare register 0 and the timer counter value (Setting the mode isrequired).

15 14 13 12 11 10 9 8

T15 T14 T13 T12 T11 T10 T09 T08

bit 7 6 5 4 3 2 1 0

T07 T06 T05 T04 T03 T02 T01 T00

Bit No.Address : 00006DH

Read/write (R/W) (R/W)Initial value (0) (0)

Address : 00006CH

(R/W)(0)

Initial value

Bit No.

(R/W) (R/W)(0) (0)

(R/W)(0)

(R/W) (R/W)(0) (0)

(R/W) (R/W)(0) (0)

(R/W)(0)

(R/W) (R/W)(0) (0)

(R/W)(0)

(R/W) (R/W)(0) (0)

TCDT

Timer counter data register (TCDT)

Read/write

174


12.3.2 Timer Counter Control Status Register

The timer counter control status register sets the operation mode of the 16-bit free-running timer, starts and stops the 16-bit free-running timer, and controls interrupts.

■ Timer Counter Control Status Register

Figure 12.3-3 Timer Counter Control Status Register

[bit 7] Reserved bit

Always write "0" to this bit.

[bit 6] IVF

This bit is an interrupt request flag of the 16-bit free-running timer.

If the 16-bit free-running timer overflows, or if the counter is cleared by a match withcompare register 0, "1" is set to this bit.

An interrupt is issued if the interrupt request enable bit (bit 5: IVFE) is set.

This bit is cleared by writing "0". Writing "1" has no effect.

"1" is always read by a read-modify-write instruction.

[bit 5] IVFE

IVFE is an interrupt enable bit of the 16-bit free-run timer. While this bit is "1", an interrupt isissued if "1" is set to the interrupt flag (bit 5: IVF).

7 6 5 4 3 2 1 0

Reserved IVF IVFE STOP MODE CLR CLK1 CLK0Address : 00006EH TCCS

Initial value (0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

Timer Counter Control Status Register (TCCS)

Read/write

Bit No.

0 No interrupt request (initial value)

1 Interrupt request

0 Interrupt disabled (initial value)

1 Interrupt enabled

175


[bit 4] STOP

The STOP bit is used to stop the 16-bit free-running timer.

Writing "1" to this bit stops the timer. Writing "0" starts the timer.

Note:

The output compare operation stops when the 16-bit free-running timer stops.

[bit 3] MODE

The MODE bit is used to set the reset condition of the 16-bit free-running timer.

When "0" is set, the counter value can be initialized by RESET or a clear bit (bit 2: CLR).

When "1" is set, the counter value can be initialized by a match with compare register 0 inaddition to RESET and a clear bit (bit 2: CLR).

Note:

The clear bit and a match with the compare register initialize the timer when the timer valuechanges.

[bit 2] CLR

The CLR bit initializes the operating 16-bit free-running timer value to "0000".

When "1" is set, the counter value is initialized to "0000". Writing "0" has no effect. "0" isalways read from this bit. The counter value is initialized when the count value changes.

Note:

To initialize the counter value while the timer is stopped, write "0000" to the data register.

[bits 1 and 0] CLK1 and CLK0

CLK1 and CLK0 are used to select the count clock for the 16-bit free-run timer. The clock isupdated immediately after a value is written to these bits. Therefore, ensure that the outputcompare and input capture operations are stopped before a value is written to these bits.

0 Counter enabled (operation) (initial value)

1 Counter disabled (stop)

0 Initialization by reset or clear bit (initial value)

1 Initialization by reset, clear bit, or compare register 0

0 No effect (initial value)

1 The counter value is initialized to "0000".

CLK1 CLK0 Count clock φ=16 MHz φ=8 MHz φ=4 MHz φ=2 MHz

0 0 φ/4 0.25 μs 0.5 μs 1 μs 2 μs

0 1 φ/16 1 μs 2 μs 4 μs 8 μs

1 0 φ/64 4 μs 8 μs 16 μs 32 μs

1 1 φ/256 16 μs 32 μs 64 μs 128 μs

φ = Machine clock

176


12.3.3 16-bit Free-running Timer Operation

The 16-bit free-running timer starts counting from counter value "0000" after the reset is released. The counter value is used as the reference time for the 16-bit output compare and 16-bit input capture operations.

■ 16-bit Free-running Timer Operation

The counter value is cleared in the following conditions:

• When an overflow occurs.

• When a match with the output compare register 0 occurs. (This depends on the mode.)

• When "1" is written to the CLR bit of the TCCS register during operation.

• When "0000" is written to the TCDT register during stop.

• Reset

An interrupt can be generated when an overflow occurs or when the counter is cleared by amatch with the compare register 0. (Compare match interrupts can be used only in anappropriate mode.)

Figure 12.3-4 Clearing the Counter by an Overflow

Figure 12.3-5 Clearing the Counter upon a Match with Output Compare Register 0

FFFFH

BFFF H

7FFFH

3FFFH

0000H

Counter valueOverflow

Time

Reset

Interrupt

FFFFH

BFFF H

7FFFH

3FFFH

0000H

BFFFH

Counter value

Match

Time

Reset

Compare

Interrupt

Match

register value

177


■ 16-bit Free-running Timer Timing

As shown in Figure 12.3-6 "16-bit free-running timer count timing", the 16-bit free-running timeris incremented based on the input clock (internal or external clock). When an external clock isselected, the 16-bit free-running timer is incremented at the rising edge.

Figure 12.3-6 16-bit free-running timer count timing

As shown in Figure 12.3-7 "16-bit free-running timer clear timing (match with the compareregister 0)", the counter can be cleared by a reset, software clear, or match with compareregister 0. For a reset or software clear, the counter is immediately cleared. For a match withcompare register 0, the counter is cleared synchronously with the count timing.

Figure 12.3-7 16-bit free-running timer clear timing (match with the compare register 0)

N N+1Counter value

External clock

Count clock

input

Machine clock φ

N

N 0000

Compareregister value

Compare match

Counter value

Machine clock φ

178

12.4 Output Compare

12.4 Output Compare

The output compare module consists of two 16-bit compare registers, two compare output pins, and control register. If the value written to the compare register of this module matches the 16-bit free-running timer value, the output level of the pin can be reversed and an interrupt can be issued.

■ Output Compare

• Two compare registers exist that can be used independently. Depending on the setting, thetwo compare registers can be used to control pin outputs.

• The initial value for the pin output can be specified.

• An interrupt can be issued upon a match as a result of comparison.

■ Output Compare Block Diagram

Figure 12.4-1 Output Compare Block Diagram

ICP1

T Q OTE0 OUT0

CMOD

T Q OTE1 OUT1

ICP0 ICE1 ICE0

Inte

rnal

dat

a bu

s

16-bit timer counter value (T15 to T00)

Compare control


Compare control

Compare register 1

Controller

Control blocks

Compare 1

Compare 0interrupt

interrupt

Compare register 0

179


12.4.1 Output Compare Register

These 16-bit compare registers are compared with the 16-bit free-running timer. Since the initial register values are undefined, set appropriate value before enabling the operation. These registers must be accessed by the word access instructions. When the value of the register matches that of the 16-bit free-running timer, a compare signal is generated and the output compare interrupt flag is set. If output is enabled, the output level corresponding to the compare register is reversed.

■ Output Compare Register

Figure 12.4-2 Output Compare Register

15 14 13 12 11 10 9 8

C15 C14 C13 C12 C11 C10 C09 C08

7 6 5 4 3 2 1 0

C07 C06 C05 C04 C03 C02 C01 C00

Address : 003929H

00392BH

Address : 003928H

00392AH

Initial value

Bit No.

OCCP0,1

(R/W) (R/W) (R/W) (R/W)(X) (X) (X) (X) (X) (X)

(R/W)(X)(X)

(R/W) (R/W) (R/W)

(R/W) (R/W) (R/W) (R/W)

(X) (X) (X) (X) (X) (X)(R/W)

(X)(X)(R/W) (R/W) (R/W)

Bit No.Compare register (OCCP0 and OCCP1)

Read/write

Initial value

Read/write

180

12.4 Output Compare

12.4.2 Control Status Register of Output Compare

The control status register sets the operation mode of output compare, starts and stops output compare, controls interrupts, and sets the external output pins.

■ Control Status Register of Output Compare

Figure 12.4-3 Control Status Register

[bits 15, 14, and 13] Unused bits

[bit 12] CMOD

CMOD is used to switch the pin output level reverse mode upon a match while pin output isenabled (OTE1=1 or OTE0=1).

• When CMOD=0 (initial value), the output level of the pin corresponding to the compareregister is reversed.

• OUT0: The level is reversed upon a match with compare register 0.


• When CMOD=1, the output level is reversed for the compare register 0 in the same manneras for CMOD=0. The output level of the pin corresponding to compare register 1 (OUT1),however, is reversed upon a match with compare register 0 or 1. If compare registers 0 and1 have the same value, the same operation as with a single compare register is performed.


• OUT1: The level is reversed upon a match with compare register 0 or 1.

[bits 11 and 10] OTE1 and OTE0

These bits are used to enable the output compare output pins. The initial value for these bitsis "0".

15 14 13 12 11 10 9 8

CMOD OTE1 OTE0 OTD1 OTD0

7 6 5 4 3 2 1 0

ICP1 ICP0 ICE1 ICE0 CST1 CST0

Address : 000059H

Read/write (-) (R/W)

Initial value

Read/write

Initial value

(-)(-)(-)

(-)(-) (0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

Address : 000058H

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)(-)

(-)

(-)

(-)

OCS0/1

Compare control status register (0/1)

Bit No.

Bit No.

0 General-purpose port (initial value)

1 Output compare pin output

Note:OTE1: Corresponds to output compare 1 (OUT1). OTE0: Corresponds to output compare 0 (OUT0).

181


[bits 9 and 8] OTD1 and OTD0

These bits are used to change the pin output level when the output compare pin output isenabled. The initial value of the compare pin output is "0". Ensure that the compareoperation is stopped before a value is written. When read, these bits indicate the outputcompare pin output value.

[bits 7 and 6] ICP1 and ICP0

These bits are used as output compare interrupt flags. "1" is set to these bits when thecompare register value matches the 16-bit free-run timer value. While the interrupt requestbits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the ICP1 andICP0 bits are set. These bits are cleared by writing "0".

Writing "1" has no effect. "1" is always read by a read-modify-write instruction.

[bits 5 and 4] ICE1 and ICE0

These bits are used as output compare interrupt enable flags. While the "1" is written tothese bits, an output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set.

[bits 3 and 2] Unused bits

[bits 1 and 0] CST1 and CST0

These bits are used to enable the comparison with 16-bit free-run timer.

Ensure that a value is written to the compare register before the compare operation isenabled.

0 Sets "0" for the compare pin output. (initial value)

1 Sets "1" for the compare pin output.

Note:OTD1: Corresponds to output compare 1. OTD0: Corresponds to output compare 0.

0 No compare match (initial value)

1 Compare match

Note:ICP1: Corresponds to output compare 1. ICP0: Corresponds to output compare 0.

0 Output compare interrupt disabled (initial value)

1 Output compare interrupt enabled

Note:ICE1: Corresponds to output compare 1. ICE0: Corresponds to output compare 0.

0 Compare operation disabled (initial value)

1 Compare operation enabled

182

12.4 Output Compare

Note:

CST1: Corresponds to output compare 1.

CST0: Corresponds to output compare 0.

Since output compare is synchronized with the 16-bit free-running timer clock, stopping the16-bit free-running timer stops compare operation.

183


12.4.3 16-bit Output Compare Operation

In the 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16-bit free-run timer value.

■ Sample of Output Waveform when Compare Registers 0 and 1 are Used (The Initial Output Value is 0.)

Figure 12.4-4 Sample of Output Waveform when Compare Registers 0 and 1 are Used

The output level can be changed using two compare registers (when CMOD=1).

FFFFH

BFFFH

7FFFH

3FFFH

0000H

OUT0

OUT1

BFFFH

7FFFH

Counter value

Time

Reset

Compare register

Compare register

Compare 0

Compare 1

0 value

1 value

interrupt

interrupt

184

12.4 Output Compare

■ Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is 0.)

Figure 12.4-5 Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is 0.)

■ Output Compare Timing

In output compare operation, a compare match signal is generated when the free-running timervalue matches the specified compare register value. The output value can be reversed and aninterrupt can be issued. The output reverse timing upon a compare match is synchronized withthe counter count timing.

When the compare register is updated, comparison with the counter value is not performed.

As shown in Figure 12.4-6 "Compare operation upon update of compare register", when thecompare register is updated, comparison with the counter value is not performed.

Figure 12.4-6 Compare operation upon update of compare register

Figure 12.4-7 "Interrupt timing" shows the output compare interrupt timing, and Figure 12.4-8"Output pin change timing" shows the output compare output pin change timing.

FFFFH

BFFFH

7FFFH

3FFFH

0000H

OUT0

OUT1

BFFFH

7FFFH

Counter value

Time

Reset

Compare register

Compare register

Corresponds tocompare 0 and 1

Compare 0

Compare 1

0 value

1 value

interrupt

interrupt

Corresponds to compare 0

N

M

N+1 N+2 N+3

M

N+1

N+3

Counter valueNo match signal is generated.

Compare register0 valueCompare register0 write

Compare register1 valueCompare register1 write Compare 0 stop Compare 1 stop

185


Figure 12.4-7 Interrupt timing

Figure 12.4-8 Output pin change timing

N

N

N+1Counter value

Compare register

Compare match

Interrupt

value

Machine clock φ

NN+1

N

N N+1Counter value

Compare register

Compare match

Pin output

value

signal

186

12.5 Input Capture

12.5 Input Capture

Input capture detects a rising or falling edge or both edges of an external input signal and stores a 16-bit free-running timer value at that time in a register. In addition, input capture can generate an interrupt upon detection of an edge. Input capture consists of an input capture data register and a control register.

■ Input Capture

Each input capture has a corresponding external input pin.

❍ The valid edge of an external input can be selected from the following three types:

❍ An interrupt can be generated upon detection of a valid edge of an external input.

■ Input Capture Block Diagram

Figure 12.5-1 Input Capture Block Diagram

Rising edge

Falling edge

Both edges

EG11 EG10 EG01 EG00

ICP1

IN0

IN1

Inte

rnal

dat

a bu

s

Capture data register 0


Capture data register 1

Edge detection

Interrupt

Interrupt

Edge detection

ICE0ICE1ICP0

187


12.5.1 Input Capture Register Details

Input capture has the two registers listed. These registers store a value from the 16-bit timer when a valid edge of the corresponding external pin input waveform is detected. (The registers must be accessed in word mode. No values can be written to the registers.)

■ Input Capture Data Register

Figure 12.5-2 Input Capture Data Register

■ Control Status Register

Figure 12.5-3 Input Capture Control Status Register

[bits 7 and 6] ICP1 and ICP0

These bits are used as input capture interrupt flags. "1" is set to this bit upon detection of avalid edge of an external input pin. While the interrupt enable bits (ICE0 and ICE1) are set,an interrupt can be generated upon detection of a valid edge.

These bits are cleared by writing "0". Writing "1" has no effect. "1" is always read by a read-modify-write instruction.

15 14 13 12 11 10 9 8

CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08

bit 7 6 5 4 3 2 1 0

CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00

Bit No.Address : 003919H

00391BH

(R) (R)

(X) (X)

Address : 003918H

00391AH

(R)

(X)

Initial value

Bit No.

(R) (R)

(X) (X)

(R)

(X)

(R) (R)

(X) (X)

(R) (R)

(X) (X)

(R)

(X)

(R) (R)

(X) (X)

(R)

(X)

(R) (R)

(X) (X)

IPCP0/1

Input capture data register 0/1

Read/write

Initial value

Read/write

7 6 5 4 3 2 1 0

ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00

Bit No.

Address : 00004CH ICS0/1

Read/write

Initial value

(R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (0) (0) (0)(R/W)

(0)(0)(R/W) (R/W) (R/W)

Input capture control status register 0/1

0 No valid edge detection (initial value)

1 Valid edge detection

Note:ICP0: Corresponds to input capture 0. ICP1: Corresponds to input capture 1.

188

12.5 Input Capture

[bits 5 and 4] ICE1 and ICE0

These bits are used to enable input capture interrupts. While these bits are "1", an inputcapture interrupt is generated when the interrupt flag (ICP0 or ICP1) is set.

[bits 3, 2, 1, and 0] EG11, EG10, EG01, and EG00

These bits are used to specify the valid edge polarity of the external inputs. These bits arealso used to enable input capture operation.

0 Interrupt disabled (initial value)

1 Interrupt enabled

Note:ICE0: Corresponds to input capture 0.ICE1: Corresponds to input capture 1.

EG11EG01

EG10EG00

Edge detection polarity

0 0 No edge detection (stop) (initial value)

0 1 Rising edge detection

1 0 Falling edge detection

1 1 Both edge detection

Note:EG01 and EG00: Correspond to input capture 0. EG11 and EG10: Correspond to input capture 1.

189


12.5.2 16-bit Input Capture Operation

In 16-bit input capture operation, an interrupt can be generated upon detection of at the specified edge, fetching the 16-bit free-run timer value and writing it to the capture register.

■ Sample of Input Capture Fetch Timing

• Capture 0: Rising edge

• Capture 1: Falling edge

• Capture example: Both edges

Figure 12.5-4 Sample of Input Capture Fetch Timing

FFFF H

BFFF H

7FFF H

3FFF H

0000 H

IN1

IN0

3FFFH

BFFFH 3FFFH

7FFFH

Counter value

Time

Reset

Capture 0

Capture 1Capture example

Capture 0 interruptCapture 1 interrupt

IN exampleUndefined

Undefined

Undefined

Capture interrupt

190

12.5 Input Capture

■ Input Capture Input Timing

Figure 12.5-5 Capture timing for input signals

N

N+1

N+1Counter value

Machine clock

Input capture

Capture signal

Capture register

Interrupt

Valid edgeinput

φ

191


192

CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)

This chapter explains the functions and operations of the 16-bit reload timer (with the event count function).

13.1 "Outline of 16-bit Reload Timer (with Event Count Function)"

13.2 "16-bit Reload Timer (with Event Count Function)"

13.3 "Internal Clock and External Clock Operations of 16-bit Reload Timer"

13.4 "Underflow Operation of 16-bit Reload Timer"

13.5 "Output Pin Functions of 16-bit Reload Timer"

13.6 "Counter Operation State"

193


13.1 Outline of 16-Bit Reload Timer (with Event Count Function)

The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one input pin (TIN) and one output pin (TOUT), and a control register. The input clock can be selected from one external clock and three types of internal clock.

■ Outline of 16-bit Reload Timer (with Event Count Function)

The output pin (TOUT) outputs a toggle output waveform in reload mode and outputs a squarewaveform indicating counting in one-shot mode. The input pin (TIN) is used for event input inevent count mode, and can be used for trigger input or gate input in internal clock mode.

MB90435 series products have two 16-bit reload timers.

■ Intelligent I/O Service (EI2OS) Function and Interrupts

The timer includes a circuit that supports EI2OS. The timer can activate EI2OS when an

underflow occurs. EI2OS can be used with both timers on this product.

194

13.1 Outline of 16-Bit Reload Timer (with Event Count Function)

■ Block Diagram of 16-bit Reload Timer

Figure 13.1-1 "Block Diagram of 16-bit Reload Timer" shows a block diagram of the 16-bitreload timer.

Figure 13.1-1 Block Diagram of 16-bit Reload Timer

16

8

16

2

2

3

3

EXCK

GATE

CSL1

CSL0

IN CTL

MOD2

MOD1

MOD0

UF

φ φ φ

21 23 25

OUTCTL.

RELD

OUTE

OUTL

INTE

UF

CNTE

TRG

IRQ

EI2 OSCLR

16-bit reload register

16-bit down-counter

Reload

Clock selector

Re-trigger

Prescalerclear

Machine clock

Clear

Port (TIN)

Port (TOUT)

UART baud rate (ch0)A/DC (ch1)

Output enable

Inte

rnal

dat

a bu

s

195


13.2 16-Bit Reload Timer (with Event Count Function)

The 16-bit reload timer has the following two types of registers:• Timer control register (TMCSR)• 16-bit timer register (TMR)/16-bit reload register (TMRLR)

■ 16-bit Reload Timer Register

Figure 13.2-1 16-bit Reload Timer Register

15 14 13 12 11 10 9 8

— — — — CSL1 CSL0 MOD2 MOD1

⎫⎬⎭

(—) (—) (—) (—) (R/W) (R/W) (R/W) (R/W)(—) (—) (—) (—) (0) (0) (0) (0)

Bit No.


Timer control status register (upper)

7 6 5 4 3 2 1 0

MOD0 OUTE OUTL RELD INTE UF CNTE TRG

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)

TMCSR⎫⎬⎭ch1 000054H

Bit No.Timer control status register (lower)

Address: ch0 000050H


15 14 13 12 11 10 9 8

ch1 000057H

⎫⎬⎭

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(X) (X) (X) (X) (X) (X) (X) (X)



16-bit timer register (upper)/16-bit reload register (upper)

7 6 5 4 3 2 1 0


(X) (X) (X) (X) (X) (X) (X) (X)

TMR/ch1 00003EH

⎫⎬⎭ TMRLR

Bit No.

Bit No.16-bit timer register (lower)/16-bit reload register (lower)



ch1 000055H


ch1 000056H

196


13.2.1 Timer Control Status Register (TMCSR)

Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other than UF, CNTE, and TRG when CNTE = "0".

■ Timer Control Status Register (TMCSR)

Figure 13.2-2 Timer Control Status Register (TMCSR)

[Bits 11, 10] CSL1, CSL0 (Clock select 1, 0)

The count clock select bits. Table 13.2-1 "Clock Sources for CSL Bit Settings" lists theselected clock sources.

15 14 13 12 11 10 9 8

— — — — CSL1 CSL0 MOD2 MOD1ch1 00003DH

⎫⎬⎭

(—) (—) (—) (—) (R/W) (R/W) (R/W) (R/W)

(—) (—) (—) (—) (0) (0) (0) (0)

Bit No.


Timer control status register (upper)

7 6 5 4 3 2 1 0

MOD0 OUTE OUTL RELD INTE UF CNTE TRG

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)

TMCSR⎫⎬⎭ch1 00003CH

Bit No.Timer control status register (lower)



ch1 000055H


ch1 000054H

Table 13.2-1 Clock Sources for CSL Bit Settings

CSL1 CSL0 Clock Source (Machine cycle φ = 16 MHz)

0 0 φ/21 (0.125 μs)

0 1 φ/23 (0.5 μs)

1 0 φ/25 (2.0 μs)

1 1 External event count mode

197


[Bits 9, 8, 7] MOD2, MOD1, MOD0

These bits set the operation mode and I/O pin functions.

The MOD2 bit selects the I/O functions. When MOD2 = "0", the input pin functions as atrigger input. In this case, the reload register contents is loaded to the counter when anactive edge is input to the input pin and count operation proceeds. When MOD2 = "1", thetimer operates in gate counter mode and the input pin functions as a gate input. In thismode, the counter only counts while an active level is input to the input pin.

The MOD1 and 0 bits set the pin functions for each mode. Table 13.2-2 "MOD2, 1, 0 BitSettings (1)" and Table 13.2-3 "MOD2, 1, 0 Bit Settings (2)" list the MOD2, 1, 0 bit settings.

Internal clock mode (CSL0, 1 = "00", "01", or "10")

• Event counter mode (CSL0,1 = "11")

• Bits marked as × in the table can be set to any value.

[Bit 6] OUTE

Output enable bit. The TOUT pin functions as a general-purpose port when this bit is "0" andas the timer output pin when this bit is "1". In reload mode, the output waveform toggles. Inone-shot mode, TOUT outputs a square waveform that indicates that counting is in progress.

Table 13.2-2 MOD2, 1, 0 Bit Settings (1)

MOD2 MOD1 MOD0 Input Pin Function Active Edge or Level

0 0 0 Trigger disabled -

0 0 1 Trigger input Rising edge

0 1 0 Falling edge

0 1 1 Both edges

1 × 0 Gate input "L" level

1 × 1 "H" level

Table 13.2-3 MOD2, 1, 0 Bit Settings (2)

MOD2 MOD1 MOD0 Input Pin Function Active Edge or Level

×

0 0 - -

0 1 Trigger input Rising edge

1 0 Falling edge

1 1 Both edges

198


[Bit 5] OUTL

This bit sets the output level for the TOUT pin.

[Bit 4] RELD (Reload)

This bit enables reload operations. When RELD is "1", the timer operates in reload mode. Inthis mode, the timer loads the reload register contents into the counter and continuescounting whenever an underflow occurs (when the counter value changes from 0000H toFFFFH). When RELD is "0", the timer operates in one-shot mode. In this mode, the countoperation stops when an underflow occurs due to the counter value changing from 0000H toFFFFH.

[Bit 3] INTE (Interrupt enable)

Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated whenthe UF bit changes to "1". When INTE is "0", no interrupt request is generated, even whenthe UF bit changes to "1".

[Bit 2] UF (Underflow)

Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the countervalue changes from 0000H to FFFFH). Cleared by writing "0" or by the intelligent I/O service.Writing "1" to this bit has no meaning. Read as "1" by read-modify-write instructions.

[Bit 1] CNTE (Count enable)

Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger. Writing "0"stops count operation.

[Bit 0] TRG (Trigger)

Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to loadthe reload register contents to the counter and start counting. Writing "0" has no meaning.Reading always returns "0". Applying a trigger using this register is only valid when CNTE ="1". Writing "1" has no effect if CNTE = "0".

Table 13.2-4 OUTE, RELD, and OUTL Settings

OUTE RELD OUTL Output Waveform

0 × × General-purpose port

1 0 0 Output an "H" level square waveform during counting.

1 0 1 Output an "L" level square waveform during counting.

1 1 0 Toggle output. Starts with "L" level output.

1 1 1 Toggle output. Starts with "H" level output.

199


13.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)

TMR contents (for reading)Reading this register reads the count value of the 16-bit timer. The initial value is undefined. Always read this register using the word access instructions.TMRLR contents (for writing)The 16-bit reload register holds the initial count value. The initial value is undefined. Always write to this register using the word access instructions.

■ 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)

Figure 13.2-3 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)

15 14 13 12 11 10 9 8

ch1 00003FH

⎫⎬⎭

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)


16-bit timer register (upper)/16-bit reload register (upper)

7 6 5 4 3 2 1 0


TMR/⎫⎬⎭ TMRLR

Bit No.

Bit No.16-bit timer register (lower)/16-bit reload register (lower)


ch1 00003EH


ch1 000057H


ch1 000056H

200

13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer

13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer

The machine clock divided by 21, 23, or 25 can be selected as the clock sources for operating the timer from an internal divide clock. The external input pin can be selected as either a trigger input or gate input by a register setting.If an external clock is selected, the TIN pin functions as an external event input pin to count the number of valid edges set in the register.

■ Internal Clock Operation of 16-bit Reload Timer

Writing "1" to both the CNTE and TRG bits in the control register enables and starts counting atone time. Using the TRG bit as a trigger input is always available when the timer is enabled(CNTE = "1"), regardless of the operation mode.

Figure 13.3-1 "Activation and Operation of 16-bit Reload Timer Counter" shows counteractivation and counter operation. A time period T (T: machine cycle) is required from the counterstart trigger being input until the reload register data is loaded into counter.

Figure 13.3-1 Activation and Operation of 16-bit Reload Timer Counter

T

-1 -1-1

Count clock

Counter

Data load

CNTE (bit)

TRG (bit)

Reload data

201


■ Input Pin Functions of 16-bit Reload Timer (in Internal Clock Mode)

The TIN pin can be used as either a trigger input or a gate input when an internal clock isselected as the clock source. When used as a trigger input, input of an active edge causes thetimer to load the reload register contents to the counter and then start count operation afterclearing the internal prescaler. Input a pulse width of at least 2T (T is the machine cycle) to TINpin.

Figure 13.3-2 "Trigger Input Operation of 16-bit Reload Timer" shows the operation of triggerinput.

Figure 13.3-2 Trigger Input Operation of 16-bit Reload Timer

When used as a gate input, the counter only counts while the active level specified by theMOD0 bit of the control register is input to the TIN pin. In this case, the count clock continues tooperate unless stopped. The software trigger can be used in gate mode, regardless of the gatelevel. Input a pulse width of at least 2T (T is the machine cycle) to the TIN pin. Figure 13.3-3"Gate Input Operation of 16-bit Reload Timer" shows the operation of gate input.

Figure 13.3-3 Gate Input Operation of 16-bit Reload Timer

■ External Event Counter

The TIN pin functions as an external event input pin when an external clock is selected. Thecounter counts on the active edge specified in the register. Input a pulse width of at least 4T (Tis the machine cycle) to the TIN pin.

-1 -1-1

2T- 2.5T

TIN pin

Count clock

Prescaler clear

Rising edge detected

Reload dataCounter

Load

0000H

-1 -1-1

TIN pin

Count clock

Counter

When MOD0 = "1" (Count when "H" is input)

202

13.4 Underflow Operation of 16-bit Reload Timer

13.4 Underflow Operation of 16-bit Reload Timer

An underflow is defined for this timer as the time when the counter value changes from 0000H to FFFFH. Therefore, an underflow occurs after (reload register setting + 1)

counts.

■ Underflow Operation of 16-bit Reload Timer

If the RELD bit in the control register is "1" when the underflow occurs, the contents of thereload register is loaded into the counter and counting continues. When RELD is "0", countingstops with the counter at FFFFH.

The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at thistime, an interrupt request is generated.

Figure 13.4-1 "Underflow Operation of 16-bit Reload Timer [RELD=1]" and Figure 13.4-2"Underflow Operation of 16-bit Reload Timer [RELD=0]" show the operation when an underflowoccurs.

Figure 13.4-1 Underflow Operation of 16-bit Reload Timer [RELD=1]

Figure 13.4-2 Underflow Operation of 16-bit Reload Timer [RELD=0]

0000H -1 -1-1

Count clock

Counter

Data load

Underflow set

Reload data

0000H FFFFH

Count clock

Counter

Underflow set

203


13.5 Output Pin Functions of 16-bit Reload Timer

In reload mode, the TOUT pin performs toggle output (inverts at each underflow). In one-shot mode, the TOUT pin functions as a pulse output that outputs a particular level while the count is in progress.

■ Output Pin Functions of 16-bit Reload Timer

The OUTL bit of the control register sets the output polarity. When OUTL = "0", the initial valuefor toggle output is "0" and the one-shot pulse output is "1" while the count is in progress. Theoutput waveforms are opposite when OUTL = "1".

Figure 13.5-1 "Output Pin Function of 16-bit Reload Timer (RELD=1, OUTL=0)"

and Figure 13.5-2 "Output Pin Function of 16-bit Reload Timer (RELD=0, OUTL=0)" show theoutput pin functions.

Figure 13.5-1 Output Pin Function of 16-bit Reload Timer (RELD=1, OUTL=0)

Figure 13.5-2 Output Pin Function of 16-bit Reload Timer (RELD=0, OUTL=0)

TOUT

CNTE

Count start

Underflow

Trigger

General-purpose port

Level is opposite when OUTL = "1".

TOUT

CNTE

Waiting for a trigger

[RELD=0, OUTL=0]

Underflow

Trigger

Level is opposite when OUTL = "1".

General-purpose port

204

13.6 Counter Operation State

13.6 Counter Operation State

The counter state is determined by the CNTE bit in the control register and the internal WAIT signal. Available states are: CNTE = "0" and WAIT = "1" (STOP state), CNTE = "1" and WAIT = "1" (WAIT state for trigger), and CNTE = "1" and WAIT = "0" (RUN state).

■ Counter Operation State

Figure 13.6-1 "Counter State Transitions" shows the transitions between each state.

Figure 13.6-1 Counter State Transitions

STOP

WAIT RUN

CNTE=0, WAIT=1

CNTE=1, WAIT=1 CNTE=1, WAIT=0

CNTE='0'

CNTE='1'TRG='0'

CNTE='0'

CNTE='1'TRG='1'

TRG='1' TRG='1'

RELD·UF

Reset

Counter: Retains the value whilecounting stopped.Value undefined after reset.

Counter: Retains the value whilecounting stopped.Value undefined after reset untilload.

Counter: Running

Load contents of the reloadregister to the counter.

LOAD CNTE=1, WAIT= 0

State transitions by hardware

State transitions by register access

Load complete

RELD·UF

TOUT pin: Input disabled

TOUT pin: General-purpose port

TIN pin: Only trigger input enabled

TOUT pin: Initial value output

TIN pin: Functions as TIN pin

TOUT pin: Functions as TOUT pin

205


206

CHAPTER 14 8/16-BIT PPG

This chapter explains the functions and operation of the 8/16-bit PPG.

14.1 "Outline of 8/16-bit PPG"

14.2 "Block Diagram of 8/16-bit PPG"

14.3 "8/16-bit PPG Registers"

14.4 "Operations of 8/16-bit PPG"

14.5 "Selecting a Count Clock for 8/16-bit PPG"

14.6 "Controlling Pin Output of 8/16-bit PPG Pulses"

14.7 "8/16-bit PPG Interrupts"

14.8 "Initial Values of 8/16-bit PPG Hardware"

207


14.1 Outline of 8/16-bit PPG

The 8/16-bit PPG consists of two eight-bit down counters, four eight-bit reload registers, one 16-bit control register, two external pulse output signals, and two interrupt outputs. The following functions are implemented:

■ Function of 8/16-bit PPG

❍ 8-bit PPG output, 2-channel independent operation mode:

Two independent channels of PPG output operation are implemented.

❍ 16-bit PPG output operation mode:

One channel of 16-bit PPG output operation is implemented.

❍ 8+8-bit PPG output operation mode:

8-bit PPG output operation is implemented at specifies intervals, using channel 0 output aschannel 1 clock input.

❍ PPG output operation:

Pulse waves are output at specified intervals and duty ratio. With an external circuit, this modulecan be used as a D/A converter.

The MB90435 series contains four PPG’s. The following sections only describe the functionalityof the PPG0/1. The remaining PPG’s have the identical function and the register addressshould be found in the APPENDIX A "I/O maps". The channel 0 PPG output signal is notconnected to any external pin.

208

14.2 Block Diagram of 8/16-bit PPG

14.2 Block Diagram of 8/16-bit PPG

Figure 14.2-1 "8-bit PPG ch0 Block Diagram" shows a block diagram of the 8/16-bit PPG (ch0). Figure 14.2-2 "8-bit PPG ch1 Block Diagram" shows a block diagram of the 8/16-bit PPG (ch1).

■ Block Diagram of 8/16-bit PPG

Figure 14.2-1 8-bit PPG ch0 Block Diagram

PPG00

PEN0

IRQSRQ

PRLL0

PRLH0

PIE0

PUF0

PPGC0

L data bus

H data bus

(Operation mode control)

PPG00 output enable

Peripheral clock 16-divisionPeripheral clock 8-divisionPeripheral clock 4-division

Peripheral clock 2-divisionPeripheral clock

PPG0Output latch

Invert Clear

Time base counter output512-division of main clock

Count clockPCNT

Reloadch1-borrow

L/H selection L/H selector

selection(down counter)

In MB90435 series, this signal is notconnected to any external pin.

In MB90435 series, this IRQ signalmerged with the Channel 1 IRQ signalby OR logic.

PRLBH0

209


Figure 14.2-2 8-bit PPG ch1 Block Diagram

Figure 14.2-3 Relationship between PPG Modules and External pins

PPG10

PEN1

SRQ IRQ

PIE

PUF

PRLL1

PRLH1

PPGC1

Peripheral clock

Peripheral clock 16-divisionPeripheral clock 8-division

Peripheral clock 2-divisionPeripheral clock 4-division

PPG10 output enable

PPG1Output latch

Invert

Time base counter output512-division of main clock

ch0 borrow

Count clock

PCNT

selection

(down counter)

Reload

L/H selection L/H selector

L data bus

H data bus

(Operation mode control)

In MB90435 series this pin is connected tothe "PPG0" external pin.

In MB90435 series, this IRQ signalmerged with the Channel 0 IRQ signalby OR logic.

PRLBH1

Clear

PPG0

PPG1

PPG2

PPG3

External pin

PPG 0/1

PPG 2/3

PPG 4/5

PPG 6/7

210

14.3 8/16-bit PPG Registers


The 8/16-bit PPG has the following five types of registers:• PPG0 operation mode control register• PPG1 operation mode control register• PPG0 and PPG1 clock selection register• Reload register H• Reload register L

■ 8/16-bit PPG Registers

Figure 14.3-1 8/16 bit PPG Registers

Address: ch0 003900Hch1 003902H

(R/W) (R/W)(X) (X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

PRLL0/1

PRLH0/1

Bit No.7 6 5 4 3 2 1 0

Bit No.1 5 1 4 1 3 1 2 1 1 1 0 9 8

(R/W)(X) (X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)


Address: ch0, 1 003AH

(R/W)(0) (0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)

Bit No.7 6 5 4 3 2 1 0

PPG0/1PCS2

Bit No.15

Bit No.7 6 5 4 3 2 1 0



(-)(0) (-)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(W)(1)

(R/W)

PEN1

PEN0

(-)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(-)(-)

(-)(-)

(W)(1)

(R/W)

PPGC1

PPGC0

PPG0 operation mode control register






Reserved

Reserved


PPG0/1 clock selection register

Reload register H

Reload register L

(-) (-) (-) (-)

PCS1 PCS0 PCM2 PCM1 PCM0

PE10 PIE1 PUF1 MD1 MD0

14 13 12 11 10 9 8

PE00 PIE0 PUF0

(-)

211


14.3.1 PPG0 Operation Mode Control Register (PPGC0)

The operation mode control register (PPGC0) is a 5-bit control register that selects the operation mode of the block, controls pin outputs, selects a count clock, and controls triggers.

■ PPG0 Operation Mode Control Register (PPGC0)

Figure 14.3-2 PPG0 Operation Mode Control Register (PPGC0)

[bit 7] PEN0 (PPG enable): Operation enable bit

This bit enables PPG count operation.

Setting this bit to "1" enables the counter operation.

This bit is initialized to "0" upon a reset. This bit is readable and writable.

[bit 5] PE00 (PPG output enable 00): PPG00 pin output enable bit

This bit controls the PPG00 pulse output external pin as described below.


For the MB90435 series, this bit should always be set to "0".

PUF0 - - ReservedPIE0

7 6 5 4 3 2 1 0

PE00PEN0 -


Address: ch0, 000038H


Bit No.

(R/W) (0)

(R/W) (0)

(R/W) (0)

(-) (-)

(-) (-)

(R/W) (0)

PPGC0

(-) (-)

(W) (1)

PEN0 Operation

0 Stop ("L" level output maintained)

1 PPG operation enabled

PE00 Operation

0 General-purpose port pin (pulse output disabled)

1 PPG00 = pulse output pin (pulse output enabled)

212


[bit 4] PIE0 (PPG interrupt enable): PPG interrupt enable bit

This bit controls PPG interrupt as described below.

While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No interruptrequest is issued while this bit is set to "0".


[bit 3] PUF0 (PPG underflow flag): PPG counter underflow bit

This bit indicates the PPG counter underflow as described below.

In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" whenan underflow occurs as a result of the ch0 counter value becoming from 00H to FFH. In 16-bitPPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0". Writing "1" tothis bit has not effect. Upon a read operation during a read-modify-write instruction, "1" isread.


[bit 0]

This is a reserved bit. When setting PPGC0, always set this bit to "1".

The value read from this bit is always "1".

PIE0 Operation

0 Interrupt disabled

1 Interrupt enabled

PUF0 Operation

0 PPG counter underflow is not detected.

1 PPG counter underflow is detected.

213


14.3.2 PPG1 Operation Mode Control Register (PPGC1)

The PPG1 operation mode control register (PPGC1) is a 7-bit control register that selects the operation mode of the block, controls pin outputs, selects a count clock, and controls triggers.

■ PPG1 Operation Mode Control Register (PPGC1)

Figure 14.3-3 PPG1 Operation Mode Control Register (PPGC1)

[bit 15] PEN1 (PPG enable): Operation enable bit

This bit enables the counter operation of the PPG.

Setting this bit to "1" enables the counter operation.


[bit 13] PE10 (PPG output enable 10): PPG10 pin output enable bit

This bit controls the PPG10 pulse output external pin as described below.


For the MB90435 series, the pulse signal is output to the "PPG0" external pin.

P U F 1 M D 1 M D 0PIE1

1 5 1 4 1 3 1 2 1 1 1 0 9 8

PE10PEN1 -




Bit No.

(R/W)

(0)

(-)

(-)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(W)

(1)

PPGC1Reserved

PEN1 Operation

0 Stop ("L" level output maintained)

1 PPG operation enabled

PE10 Operation

0 General-purpose port pin (pulse output disabled)

1 PPG10 = pulse output pin (pulse output enabled)

214


[bit 12] PIE1 (PPG interrupt enable): PPG interrupt enable bit

This bit controls PPG interrupt as described below.

While this bit is "1", an interrupt request is issued as soon as PUF1 is set to "1". No interruptrequest is issued while this bit is set to "0".


[bit 11] PUF1 (PPG underflow flag): PPG counter underflow bit

This bit indicates the PPG counter underflow as described below.

In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" whenan underflow occurs as a result of the Channel 1 counter value becoming from 00H to FFH.In 16-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel0 and 1 counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0". Writing"1" to this bit has not effect. Upon a read operation during a read-modify-write instruction, "1"is read.


[bit 10, 9] MD1, 0 (PPG count mode): Operation mode selection bit

These bits selects the PPG timer operation mode as described below.

These bits are initialized to "00" upon a reset. These bits are readable and writable.

Note:

Do not set "10" in these bits.

To write "01" to these bits, ensure that "01" is not written to the PEN0 bit of PPGC0 or PEN1bit of PPGC1. Write "11" or "00" in both the PEN0 and PEN1 bits simultaneously.

To write "11" to these bits, update PPGC0 and PPGC1 by word transfer and write "11" or"00" to both the PEN0 and PEN1 bits simultaneously.

PIE1 Operation

0 Interrupt disabled

1 Interrupt enabled

PUF1 Operation

0 PPG counter underflow is not detected.

1 PPG counter underflow is detected.

MD1 MD0 Operation mode

0 0 8-bit PPG 2ch independent mode

0 1 8-bit prescaler + 8-bit PPG 1ch mode

1 0 Reserved (setting prohibited)

1 1 16-bit PPG 1ch mode

215


[bit 8] This is a reserved bit.

When setting PPGC1, always write "1" to this bit.

The value read from this bit is always "1".

216


14.3.3 PPG0, 1 Clock Selection Register (PPG0/1)

The PPG0/1 clock selection register (PPG0/1) is an 8-bit control register that controls the PPG operation clock.

■ PPG0, 1 Clock Selection Register (PPG0/1)

Figure 14.3-4 PPG0, 1 Clock Selection Register (PPG0/1)

[bits 7 to 5] PCS2 to 0 (PPG count select): Count clock selection bit

These bits select the operation clock for the down counter of Channel 1 as described below.


Note:

In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch1 PPG operates in responseto a counter clock from ch0. Therefore, the setting in these bits has no effect.

PCM1 PCM0PCM2

7

PCS0PCS2 PCS1

PPG0, 1 Clock Selection register

Address: ch0, 1 003AH


Bit No.

(R/W) (0)

(R/W) (0)

(R/W) (0)

(R/W) (0)

(-) (-)

(R/W) (0)

PPG01

(R/W) (0)

(-)(-)

6 5 4 3 2 1 0

PCS2 PCS1 PCS0 Operation mode

0 0 0 Peripheral clock (62.5 ns machine clock, 16 MHz)

0 0 1 Peripheral clock/2 (125 ns machine clock, 16 MHz)



1 0 0 Peripheral clock/16 (1 μs machine clock, 16 MHz)

1 0 1Clock input from the timebase timer (128 μs, 4 MHz source oscillation)

217


[bits 4 to 2] PCM2 to 0 (PPG count mode): Count clock selection bit

These bits select the operation clock for the down counter of Channel 0 as described below.


PCM2 PCM1 PCM0 Operation mode

0 0 0 Peripheral clock (62.5 ns machine clock, 16 MHz)




1 0 0 Peripheral clock/16 (1 μs machine clock, 16 MHz)

1 0 1 Clock input from the timebase timer (128 μs, 4 MHz source oscillation)

218


14.3.4 Reload Register (PRLL/PRLH)

The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for the PCNT down counters. The PRLL and PRLH registers are readable and writable.

■ Reload Register (PRLL/PRLH)

Figure 14.3-5 Reload Register (PRLL/PRLH)


(R/W) (R/W)(X) (X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

PRLL0/1

PRLH0/1

Bit No.7 6 5 4 3 2 1 0

Bit No.1 5 1 4 1 3 1 2 1 1 1 0 9 8

(R/W)( X ) ( X )

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)(X)

(R/W)


Reload register H


Reload register L

Register name Function

PRLL Holds the L side reload value.

PRLH Holds the H side reload value.

Note:In 8-bit prescaler + 8-bit PPG mode, different values in PRLL and PRLH of Channel 0 may cause the PPG waveform of ch1 to vary in each cycle. Write the same value to PRLL and PRLH of ch0.

219


14.4 Operations of 8/16-bit PPG

One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode.

■ Operations of 8/16-bit PPG

Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the Lpulse width (PRLL) and the other is for the H pulse width (PRLH). The values stored in theseregisters are reloaded into the 8-bit down counter (PCNT), from the PRLL and PRLH in turn.The pin output value is inverted upon a reload caused by counter borrow. This operation resultsin the pulses of the specified L pulse width and H pulse width.

Table 14.4-1 "Reload Operation and Pulse Output" lists the relationship between the reloadoperation and pulse outputs.

When "1" is set in bit 4 (PIE0) of PPGC0 or in bit 12 (PIE1) of PPGC1, an interrupt request isoutput upon a borrow from 00H to FFH (from 0000H to FFFFH in 16-bit PPG mode) of eachcounter.

■ Operation Modes of 8/16-bit PPG

This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bitPPG mode, and single-channel 16-bit PPG mode.

❍ Independent two-channel mode

The two channels of 8-bit PPG units operate independently. The PPG00 pin is connected to thech0 PPG output, while the PPG10 pin is connected to the ch1 PPG output.

❍ 8-bit prescaler + 8-bit PPG mode

ch0 is used as an 8-bit prescaler while the count in ch1 is based on borrow outputs from ch0.Thus, 8-bit PPG waveforms can be output with arbitrary length of cycle time. The PPG00 pin isconnected to the ch0 prescaler output, while the PPG10 pin is connected to the ch1 PPGoutput.

Table 14.4-1 Reload Operation and Pulse Output

Reload operation Pin output change

PRLH --> PCNT PPG0/1 [0 --> 1] Rise

PRLL --> PCNT PPP0/1 [1 --> 0] Fall

220

14.4 Operations of 8/16-bit PPG

❍ 16-bit PPG 1ch mode

ch0 and ch1 are connected and used as a single 16-bit PPG. The PPG00 and PPG10 pins areconnected to the 16-bit PPG output.

For the MB90435 series, the output signal from the Channel 0 PPG is not connected to anyexternal pin.

■ 8/16-bit PPG Output Operation

The 8/16-bit channel 0 PPG is activated by setting bit 7 (PEN0) of the PPGC0 (PWM operationmode control) register to "1". The 8/16-bit channel 1 PPG is activated by setting bit 15 (PEN1)of the PPGC1 register to "1". After operation is started, counting is stopped by writing "0" to bit7 (PEN0) of PPGC0 or bit 15 (PEN1) of PPGC1. After counting is stopped, the pulse output ismaintained at the L level. In the MB90435 series, the output signal from the channel 0 PPG isnot connected to any external pin.

In 8-bit prescaler + 8-bit PPG mode, do not set ch1 to be in operation while ch0 operation isstopped.

In 16-bit PPG mode, ensure that bit 7 (PEN0) of PPGC0 register and bit 15 (PEN1) of PPGC1register are started or stopped simultaneously. The figure below is a diagram of PPG outputoperation. During PPG operation, a pulse wave is continuously output at a frequency and dutyratio (the ratio of the H-level period of the pulse wave to the L-level period). PPG continuesoperation until stop is specified explicitly.

Figure 14.4-1 PPG Output Operation, Output Waveform

■ Relationship Between 8/16-bit PPG Reload Value and Pulse Width

The width of the output pulse is determined by adding 1 to the reload register value andmultiplying it by the count clock cycle. Note that when the reload register value is 00H during 8-bit PPG operation or 0000H during 16-bit PPG operation, the pulse width is equivalent to onecount clock cycle. In addition, note that when the reload register value is FFH during 8-PPGoperation, the pulse width is equivalent to 256 count clock cycles. When the reload registervalue is FFFFH during 16-bit PPG operation, the pulse width is equivalent to 65536 count clockcycles. The following is an example of calculating the pulse width:

PEN

PPG

(Start)

T (L+1) T (H+1) L : PRLL value

H : PRLH value

T : Input from peripheral clock (

or timer base counter (depending on the

clock selection by PPGC)

Output pinStarts operation based on PEN (from Lside).

L : PRLL value

H : PRLH value

T : Input clock cycle

Ph: High pulse width

Pl : Low pulse width

P1=T (L+1)Ph=T (H+1)

221


14.5 Selecting a Count Clock for 8/16-bit PPG

The count clock used for the operation is supplied from the peripheral clock or the timebase timer. The count clock can be selected from six choices.

■ Selecting a Count Clock for 8/16-bit PPG

Select ch0 clock at bit 4 to 2 (PCM2 to 0) of the PPG01 register, and ch1 clock at bit 7 to 5(PCS2 to 0) of the PPG01 register.

The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or aninput clock from the timebase timer.

In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the setting in the PCS2 to 0has no effect.

When the timebase timer input is used, the first count cycle after a trigger or a stop may beshifted. The cycle may also be shifted if the timebase counter is cleared during operation of thismodule.

In 8-bit prescaler + 8-bit PPG mode, if ch1 is activated while ch0 is in operation and ch1 isstopped, the first count cycle may be shifted.

222

14.6 Controlling Pin Output of 8/16-bit PPG Pulses

14.6 Controlling Pin Output of 8/16-bit PPG Pulses

The pulses generated by this module can be output from external pins PPG00 and PPG10.

■ Controlling Pin Output of 8/16-bit PPG Pulses

To output the pulses from an external pin, write "1" to the bit corresponding to each pin. When"0" is written to these bits (default), the pulses are not output from the corresponding externalpins; the pins work as general-purpose ports.

In 16-bit PPG mode, the same waveform is output from PPG00 and PPG10. Thus, the sameoutput can be obtained by enabling both external pin.

In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle output waveform is output fromPPG00, while the 8-bit PPG waveform is output from PPG10. Figure 14.6-1 "8+8 PPG OutputOperation Waveform" is a diagram of output waveforms in this mode.

For the MB90435 series, the output signal from the Channel 0 PPG is not connected to anyexternal pin.

Figure 14.6-1 8+8 PPG Output Operation Waveform

Note:

Set the same value in ch0 PRLL and ch0 PRLH.

L0 :ch0 PRLL value and ch0 PRLH value

L1 :ch1 PRLL value

H1 :ch1 PRLH value

T : Input clock cycle

Ph0 :PPG00 high pulse width

Pl0 :PPG00 low pulse width

Ph1 :PPG10 high pulse width

Pl1 :PPG10 low pulse width

Ph0 Pl0

Ph1 Pl1

PPG0

PPG1

Pl0 = T (L0+1)

Ph0 = T (L0+1)

Pl1 = T (L0+1) (Ll+1)

Ph1 = T (L0+1) (Hl+1)

223


14.7 8/16-bit PPG Interrupts

For the 8/16-bit PPG, an interrupt becomes active when the reload value counts out and a borrow occurs.

■ 8/16-bit PPG Interrupts

In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by aborrow in each counter. In 16-bit PPG mode, PUF0 and PUF1 are simultaneously set by aborrow in the 16-bit counter. Therefore, enable only PIE0 or PIE1 to unify the interrupt causes.In addition, simultaneously clear the interrupt flags for PUF0 and PUF1.

224

14.8 Initial Values of 8/16-bit PPG Hardware

14.8 Initial Values of 8/16-bit PPG Hardware

The hardware components of this block are initialized to the following values when reset:

■ Initial Values of 8/16-bit PPG Hardware

❍ <Registers>

• PPGC0 --> 0X000001B

• PPGC1 --> 00000001B

• PPG10 --> XXXXXX00B

❍ <Pulse outputs>

• PPG00 --> "L"

• PPG10 --> "L"

• PE00 --> PPG00 output disabled

• PE10 --> PPG10 output disabled

❍ <Interrupt requests>

• IRQ0 --> "L"

• IRQ1 --> "L"

Hardware components other than the above are not initialized.

Note:

Write timing for 8/16-bit PPG reload registers (PRLL and PRLH)

In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instructionto write data in reload registers PRLL and PRLH. If two byte transfer instructions are used towrite a data item to these registers, a pulse of unexpected cycle time may be outputdepending on the timing.

Figure 14.8-1 Write Timing for 8/16-bit PPG Reload Registers (PRLL and PRLH)

Assume that PRLL is updated from A to C before point 1 in the time chart above, and PRLH isupdated from B to D after point 1. Since the PRL values at point 1 are PRLL = C and PRLH = B,a pulse of L side count value C and H side count value B is output only once.

Similarly, to write data in PRL of ch0 and ch1 in 16-bit PPG mode, use a long word transferinstruction, or use word transfer instructions in the order of ch0 and then ch1. In this mode, thedata is only temporarily written to ch0 PRL. Then, the data is actually written into ch0 PRL whenthe ch1 PRL is written to.

PPG0

B B C CA A D D

C B

225


As shown in Figure 14.8-2 "PRL Write Operation Block Diagram" in a mode other than 16-bitPPG mode, channel 0 PRL and channel 1 PRL can be written independently.

Figure 14.8-2 PRL Write Operation Block Diagram

ch0 PRL write data

ch0 write in a mode other

Temporary latch

Transferred in synchronization

ch1 PRL write data

ch0 PRL

ch1 write

ch1 PRL

than 16-bit PPG mode

with ch1 write in 16-bitPPG mode

226

CHAPTER 15 DELAYED INTERRUPT

This chapter explains the functions and operations of the delayed interrupt.

15.1 "Outline of Delayed Interrupt Module"

15.2 "Delayed Interrupt Register"

15.3 "Delayed Interrupt Operation"

227


15.1 Outline of Delayed Interrupt Module

The delayed interrupt source module is used to generate interrupts for switching

tasks. Using this module, interrupt requests to the F2MC-16LX CPU can be issued and canceled by software.

■ Block Diagram of Delayed Interrupt

Figure 15.1-1 "Block Diagram" is a block diagram of the delayed interrupt source module.

Figure 15.1-1 Block Diagram

■ Notes on Operation

This lock is set by writing "1" to the corresponding bit of DIRR, and is cleared by writing "0" tothe same bit. Therefore, interrupt processing is reactivated immediately after control returnsfrom interrupt processing, unless the software is designed so that the cause of the interrupt iscleared within the interrupt processing routine.

Delayed interrupt cause issuance/cancellation decoder

Cause latch

Inte

rnal

dat

a bu

s

228

15.2 Delayed Interrupt Register

15.2 Delayed Interrupt Register

DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to this register issues a delayed interrupt request, and writing "0" cancels the delayed interrupt request. Upon a reset, the request is canceled.

■ Delayed Interrupt Cause Issuance/Cancellation Register (DIRR)

In DIRR, either "0" or "1" can be written to the reserved bit area. However, it is recommendedthat a set bit or clear bit instruction be used to access this register for future expansions.

Figure 15.2-1 Delayed Interrupt Cause Issuance/Cancellation Register (DIRR)

Delayed Interrupt Cause Issuance/Cancellation Register

15 14 13 12 11 10 9 8 Bit No.

Address : 00009FH R0 DIRR

Read/write (-) (-) (-) (-) (-) (-) (-) (R/W)

Initial value (-) (-) (-) (-) (-) (-) (-) (0)

229


15.3 Delayed Interrupt Operation

When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller.

■ Delayed Interrupt Occurrence

When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in thedelayed interrupt source module is set and an interrupt request is issued to the interruptcontroller. If this interrupt has the highest priority or if there is no other interrupt request, the

interrupt controller issues an interrupt request to the F2MC-16LX CPU. The F2MC-16LX CPUcompares the ILM bit of its internal CCR register and the interrupt request, and starts thehardware interrupt processing microprogram as soon as the current instruction is completed ifthe interrupt level of the request is higher than that of the ILM bit. The interrupt processingroutine for this interrupt is thus executed.

Figure 15.3-1 Delayed Interrupt Issuance

Writing "0" to the relevant DIRR bit in the interrupt processing routine clears the cause of thisinterrupt and switches between tasks.

DIRR ICR xx

ICR yy

CMP

ILM

IL

NTA

CMP

WRITEDelayed interrupt source module Interrupt controller

Other requests

F2MC-16LX CPU

230

CHAPTER 16 DTP/EXTERNAL INTERRUPTS

This chapter explains the functions and operations of the DTP/external interrupts.

16.1 "Outline of DTP/External Interrupts"

16.2 "DTP/External Interrupt Registers"

16.3 "Operations of DTP/External Interrupts"

16.4 "Switching Between External Interrupt and DTP Requests"

16.5 "Notes on Using DTP/External Interrupts"

231


16.1 Outline of DTP/External Interrupts

The data transfer peripheral (DTP) is located between an external peripheral and the

F2MC-16LX CPU. The DTP receives a DMA request or interrupt request from the

external peripheral, transfers the request to the F2MC-16LX CPU to activate the intelligent I/O service or interrupt processing.

■ Outline of DTP/External Interrupts

For the intelligent I/O service, "H" and "L" request levels are available. For an external interruptrequest, four request levels are available: "H", "L", rising edge, and falling edge.

■ Block Diagram of DTP/External Interrupts

Figure 16.1-1 Block Diagram of DTP/External Interrupts

8

8

8

16

8

Interrupt/DTP enable register

Gate Cause F/F Edge detection circuit Request input

Interrupt/DTP cause register

Request level setting register

Inte

rnal

dat

a bu

s

232

16.1 Outline of DTP/External Interrupts

■ DTP/External Interrupts Registers

EN3 EN2 EN1 EN0EN4

7 6 5 4 3 2 1 0

EN5EN7 EN6Address : 000030H

15 14 13 12 11 10 9 8

Address : 000031H ER4 ER3 ER2 ER1 ER0ER5ER7 ER6

ENIR

EIRR

Bit No.

Read/write

Initial value

Read/write

Initial value

Bit No.

(R/W) (R/W)(R/W) (R/W) (R/W) (R/W) (R/W)(R/W)(0) (0) (0) (0) (0) (0) (0)(0)



(R/W) (R/W)(R/W) (R/W) (R/W) (R/W) (R/W)(R/W)(X) (X) (X) (X) (X) (X) (X)(X)

LA2

7 6 5 4 3 2 1 0

Address : 000032HLB1 LA1 LB0 LA0LB2LB3 LA3 ELVR

Bit No.

Read/write

Initial value

Address : 000033H

15 14 13 12 11 10 9 8

LA6 LB5 LA5 LB4 LA4LB6LB7 LA7 ELVR

Read/write

Initial value

Bit No.




233


16.2 DTP/External Interrupt Registers

The DTP/external interrupts has the following three types of registers:• Interrupt/DTP enable register (ENIR: Interrupt request enable register)• Interrupt/DTP flag (EIRR: External interrupt request register)• Request level setting register (ELVR: External level register)

■ Interrupt/DTP Enable Register (ENIR: Interrupt request enable register)

Figure 16.2-1 Interrupt/DTP Enable Register (ENIR)

ENIR enables the function to issue a request to the interrupt controller using a device pin as anexternal interrupt/DTP request input. A pin corresponding to a "1" bit of this register is used asan external interrupt/DTP request input. A pin corresponding to a "0" bit holds the externalinterrupt/DTP request input cause, but does not issue a request to the interrupt controller.

■ Interrupt/DTP Cause Register (EIRR: External interrupt request register)

Figure 16.2-2 Interrupt/DTP Cause Register (EIRR)

The EIRR indicates the presence of external interrupt/DTP requests at the pins correspondingto the "1" bits of this register. Writing "0" to a bit of this register clears the corresponding requestflag. Writing "1" has no effect. "1" is always read from this register by a read-modify-writeinstruction.

Note:

If more than one external interrupt request output is enabled (EN7 to EN0 of ENIR are set to1), clear to 0 only the bit for which the CPU accepted an interrupt (any of bits ER7 to ER0that are set to 1). Do not clear the other bits without a valid reason.

Address : 000030H ENIR

7 6 5 4 3 2 1 0

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0


Bit No.

Read/write

Initial value


Address : 000031H EIRRER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

15 14 13 12 11 10 9 8

Read/write

Initial value

Bit No.

(R/W) (R/W)(R/W) (R/W) (R/W) (R/W) (R/W)(R/W)

(X) (X) (X) (X) (X) (X) (X)(X)


234

16.2 DTP/External Interrupt Registers

■ Request Level Setting Register (ELVR: External level register)

Figure 16.2-3 Request Level Setting Register (ELVR)

ELVR defines the request event at the external pin. Each pin is assigned two bits as describedin Table 16.2-1 "Interrupt Request Detection Factor for LBx and LAx Pins". If a request isdetected by the input level, the interrupt flag is set as long as the input is at the specified leveleven after the flag is reset by software.

Address : 000032 H

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4Address : 000033 H

7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8

LA2 LB1 LA1 LB0 LA0LB2 LB3 LA3

Bit No.

Read/write

Initial value

Read/write

Initial value

Bit No.

ELVR




Table 16.2-1 Interrupt Request Detection Factor for LBx and LAx Pins

LBx LAx Interrupt request detection factor

0011

0101

L level pin inputH level pin inputRising edge pin inputFalling edge pin input

235


16.3 Operations of DTP/External Interrupts

When the interrupt flag is set, this block signals an interrupt to the interrupt controller. The interrupt controller judges the priority levels of the simultaneous interrupts, and

issues an interrupt request to the F2MC-16LX CPU if the interrupt from this block has

the highest priority. The F2MC-16LX CPU compares the ILM bits of its internal CCR register and the interrupt request. If the interrupt level of the request is higher than

that indicated by the ILM bits, the F2MC-16LX CPU activates the hardware interrupt processing microprogram as soon as the currently executing instruction is terminated.

■ External Interrupt Operation

In the hardware interrupt processing microprogram, the CPU reads the ISE bit information fromthe interrupt controller, identifies that the request is for interrupt processing based on thatinformation, and branches to the interrupt processing microprogram. The interrupt processingmicroprogram reads the interrupt vector area and issues an interrupt acknowledgment signal forthe interrupt controller. Then, the microprogram transfers the jump destination address of themacro instruction generated from the vector to the program counter, and executes the userinterrupt processing program.

Figure 16.3-1 External Interrupt

ELVR

EIRR

ENIR ICRxx

ICRyy

CMP

ILM

IL

NTA

CMP

F2MC-16LX CPUDTP/External interruptOther request


Cause

236

16.3 Operations of DTP/External Interrupts

■ DTP operation

To activate the intelligent I/O service, the user program initially sets the address of a register,assigned between 000000H and 0000FFH, in the I/O address pointer of the intelligent I/Oservice descriptor. Then, the user program sets the start address of the memory buffer in thebuffer address pointer.

The DTP operation sequence is almost the same as for external interrupts. The operation isidentical until the CPU activates the hardware interrupt processing microprogram. Then, for theDTP, control is transferred to the intelligent I/O service processing microprogram, since the ISEbit read by the CPU within the hardware interrupt processing microprogram indicates the DTP.Once the intelligent I/O service is activated, a read or write signal is sent to the addressesexternal peripheral, and data is transferred between the peripheral and the chip. The externalperipheral must cancel the interrupt request to this chip within three machine cycles after thetransfer is made. When the transfer is completed, the descriptor is updated, and the interruptcontroller generates a signal that clears the transfer cause. Upon receiving the signal to clearthe transfer cause, this resource clears the flip-flop holding the cause and prepares for the nextrequest from the pin. For details of the intelligent I/O service processing, refer to the MB90500Programming Manual.

Figure 16.3-2 Timing to Cancel the External Interrupt at the End of DTP Operation

Figure 16.3-3 Sample Interface to the External Peripheral

Interrupt cause

Internal operation

Address bus pin

Data bus pin

Read signal

Write signal

Selecting andreading

descriptor

Edge request or H level request

* When data is transferred from the I/O register to memory

Read address Write address

Read data Write data

Cancel within three machine cycles.

in the intelligent I/O service

➀

➁

Data, address

DTP CORE MEMORY

MB90435

INTIRQ

➀ ➁

Ext

erna

l per

iphe

ral

Reg

iste

r

Internal bus

Cancel within three machinecycles after transfer.

bus

237


16.4 Switching between External Interrupt and DTP Requests

To switch between external interrupt and DTP requests, use the ISE bit in the ICR register corresponding to this block, which is in the interrupt controller. Each pin is individually assigned ICR. Thus, a pin is used for a DTP request if "1" is written to the ISE bit of the corresponding ICR, and is used for an external interrupt request if "0" is written to the bit.

■ Switching Between External Interrupt and DTP Requests

Figure 16.4-1 Switching Between External Interrupt and DTP Requests

DTP

ICR xx

ICR yy 1

0

F MC-16 LX CPU

PinDTP/

External interrupt


2

External interrupt

238

16.5 Notes on Using DTP/External Interrupts

16.5 Notes on Using DTP/External Interrupts

Note carefully the following items when using DTP/external interrupts:• Conditions on the externally connected peripheral when DTP is used• Recovery from standby• External interrupt/DTP operation procedure• External interrupt request level

■ Notes on Using DTP/External Interrupts

❍ Conditions on the externally connected peripheral when DTP is used

DTP supports only external peripherals that automatically clear a request once a transfer iscompleted. The system must be designed so that a transfer request is canceled within threemachine cycles (provisional) after transfer operation starts. Otherwise, this resource assumesthat a transfer request is issued.

❍ External interrupt/DTP operation procedure

To set registers in the external interrupt/DTP, follow the steps below:

1. Disable the bits corresponding to the enable register.

2. Set the bits corresponding to the request level setting register.

3. Clear the bits corresponding to the cause register.

4. Enable the bits corresponding to the enable register.

(Steps 3. and 4. can be simultaneously performed by word specification.)

To set a register in this resource, ensure that the enable register is disabled. Before enablingthe enable register, ensure that the cause register is cleared. Clearing the cause registerprevents a false interrupt cause from being determined while registers are set or interrupts areenabled.

239


❍ External interrupt request level

To detect an edge for an edge request level, the pulse width must be at least three machinecycles.

As shown in Figure 16.5-1 "Clearing the Cause Hold Circuit Upon Level Set", when the requestinput level is related to the level setting, a request that is input from an external device to theinterrupt controller is kept active even if the request is later canceled because a cause holdcircuit has been installed. To cancel the request to the interrupt controller, the cause hold circuitmust be cleared as shown in Figure 16.5-2 "Interrupt Cause and Interrupt Request to theInterrupt Controller While Interrupts are Enabled".

Figure 16.5-1 Clearing the Cause Hold Circuit Upon Level Set

Figure 16.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts are Enabled

Level detection Cause F/F (cause hold circuit)

The cause is kept held unless cleared.

Enable gate To interruptcontrollerInterrupt cause

Interrupt cause

Interrupt request to

H level

Set inactive when the cause F/F is cleared.the interrupt controller

240

CHAPTER 17 A/D CONVERTER

This chapter explains the functions and operations of the A/D converter.

17.1 "Features of A/D Converter"

17.2 "Block Diagram of A/D Converter"

17.3 "A/D Converter Registers"

17.4 "Operations of A/D Converter"

17.5 "Conversion Using EI2OS"

17.6 "Conversion Data Protection"

241


17.1 Features of A/D Converter

The A/D converter converts analog input voltages into digital values. The A/D converter has the following features:

■ Features of A/D converter

❍ Conversion time:

26.3 μs min. per channel (at 16 MHz machine clock)

❍ RC sequential compare conversion with sample and hold circuit

❍ 10-bit or 8-bit resolution

❍ Analog input selected from eight channels by programming

Single conversion mode: One channel is selected for conversion.

Scan conversion mode: Voltages in multiple consecutive channels are converted. Up to eightchannels can be programmed.

Continuous conversion mode: Voltages at the specified channel are converted repeatedly.

Stop conversion mode: Voltages at the one channel is converted, then the system pauses andstands by for the next activation. (The conversion start points can be synchronized.)

❍ Interrupt request

At the end of A/D conversion, a relevant interrupt request can be issued to the CPU. This

interrupt can be used to activate the EI2OS, which automatically transfers A/D conversion resultto memory. This feature is suitable for continuous processing.

❍ Selectable activation cause

The activation can be done by software, external trigger (falling edge), or timer (rising edge).

242

17.1 Features of A/D Converter

■ Analog Input Enable Register

Always write "1" to the ADER bit corresponding to a pin used as analog input.

Figure 17.1-1 Analog Input Enable Register

Port 6 pins are controlled as described below.

0: Port input/output mode

1: Analog input mode

"1" is set upon a reset.

■ Input Impedance

The sampling circuit of the A/D Converter can be represented with the equivalent circuit shownbelow.

Driving impedance to an analog input should be lower than 15.5 KΩ when the sampling time isset to 4μs (ST=0 and ST0=0 at 16MHz machine clock). Otherwise the conversion accuracy willbe worsened. If this is the case, set the sampling time longer (ST1=1 and ST0=1) or addexternal capacitor in order to compensate the driving impedance.

ADE3 ADE2 ADE1 ADE0ADE4

15 14 13 12 11 10 9 8

ADE5ADE7 ADE6Address: 00001BH


Bit No.

Read/writeInitial value (1) (1) (1) (1) (1) (1) (1) (1)

ADER

Analog Input Enable Register

ADCAnalog input

30p F max.

243


17.2 Block Diagram of A/D Converter

Figure 17.2-1 "Block Diagram of A/D Converter" shows a block diagram of the A/D converter.

■ Block Diagram of A/D Converter

Figure 17.2-1 Block Diagram of A/D Converter

ADTG pinADCS0/1

ADCR0/1

AVCC

AVRH/L

AVSS

MPX

AN0AN1AN2AN3AN4AN5AN6AN7

Inpu

t circ

uit

Sample and hold circuit

Comparator

D/A converter

Sequential compare register

Dec

oder Data register

Inte

rnal

dat

a bu

s

A/D control register 0

A/D control register 1Activation by external trigger

Activation by timer16-bit Reload Timer 1 Operation clock

Prescaler

244

17.3 A/D Converter Registers


The A/D converter has the following two types of registers:• Control status resister• Data register

■ A/D Converter Registers

The A/D converter has the following registers:

Figure 17.3-1 A/D Converter Register Configuration

Figure 17.3-2 A/D Converter Registers

ADCS1

ADCR1

SSR

ADCR0

15 8 7 0

8 bit 8 bit

ADCS0

Address : 000037HD8

D7 D6 D5 D4 D3 D2 D1 D0

Address : 000034H

Address : 000036H

15

(0) (0) (0) (0) (0) (0) (0) (0)

14 13 12 11 10 9 8

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Address : 000035H

SI0 ST0 CT1 CT0 D9ST1

Bit No.


Read/write

Initial value

Bit No.

A/D control status register (upper)


(0) (0) (0) (0) (0) (0) (0) (0)


(0) (0) (0) (0) (1) (-) (X) (X)

(W) (W) (W) (W) (W) (R) (R)

(X) (X)

(R) (R)

(X) (X)

(R) (R)

(X) (X)

(R) (R)

(X) (X)

(R) (R)

(-)

BUSY INT INTE PAUS STS1 STS0 STRT Reserved

MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

ADCS1

ADCS0

ADCR1

ADCR0

A/D control status register (lower)

Data register (upper)

Data register (lower)

Bit No.


Read/write

Initial value

Bit No.

245


17.3.1 Control Status Registers (ADCS0)

The control status register (ADCS0) controls the A/D converter and indicates the status. Do not rewrite ADCS0 during A/D conversion.

■ Control Status Registers (ADCS0)

Figure 17.3-3 Control Status Register (ADCS0)

[bits 7 and 6] MD1 and MD0 (A/D converter mode set):

Use the MD1 and MD0 bits to set the operation mode.

❍ Single mode:

A/D conversion is continuously performed from the channel specified with ANS2 to ANS0 to thechannel specified with ANE2 to ANE0. The conversion stops once it has been done for all thesechannels.

❍ Continuous mode:

A/D conversion is repeatedly performed from the channel specified with ANS2 to ANS0 to thechannel specified with ANE2 to ANE0.

ANS0 ANE2 ANE1 ANE0ANS1

7 6 5 4 3 2 1 0

ANS2MD1 MD0Address: 000034H ADCS0


(0) (0) (0) (0) (0) (0) (0) (0)Read/writeInitial value

Bit No.

A/D control status register (lower)

MD1 MD0 Operation mode

0 0 Single mode. Reactivation during operation is allowed.

0 1 Single mode. Reactivation during operation is not allowed.

1 0 Continuous mode. Reactivation during operation is not allowed.

1 1 Stop mode. Reactivation during operation is not allowed.

246


❍ Stop mode:

A/D conversion is performed from the channel specified with ANS2 to ANS0 to the channelspecified with ANE2 to ANE0, pausing for each channel. The A/D conversion is resumed uponan activation.

Upon a reset, these bits are initialized to "00".

Note:

When activated in the continuous or stop mode, A/D conversion continues until it is stoppedby the BUSY bit.

The conversion is stopped by writing "0" to the BUSY bit.

Reactivation disabled in single mode, continuous mode, and stop mode applies to all kindsof activation by software, an external trigger, and a timer.

[bits 5, 4, and 3] ANS2, ANS1, and ANS0 (Analog start channel set):

Use these bits to specify the start channel for A/D conversion.

When the A/D converter is activated, A/D conversion starts from the channel selected withthese bits.

Note:

* Read

During A/D conversion, the current conversion channel is read from these bits. If the systemis stopped in the stop mode, the last conversion channel is read.

* Upon a reset, these bits are initialized to "000".

ANS2 ANS1 ANS0 Start channel

0 0 0 AN0

0 0 1 AN1

0 1 0 AN2

0 1 1 AN3

1 0 0 AN4

1 0 1 AN5

1 1 0 AN6

1 1 1 AN7

247


[bits 2, 1, and 0] ANE2, ANE1, and ANE0 (Analog end channel set):

Use these bits to set the A/D conversion end channel.

Note:

When the same channel is written to ANE2 to ANE0 and ANS2 to ANS0, conversion isperformed for one channel only (single conversion).

In the continuous or stop mode, operation returns to the start channel specified in ANS2 toANS0 after the conversion is completed for the channel specified in ANE2 to ANE0.

If the ANS value is greater than the ANE value, conversion starts from the ANS channel.Then, once conversion is complete up to channel 7, operation returns to channel 0 andconversion is performed up to the ANE channel.


Example: ANS=6, ANE=3, single mode

Conversion is performed in the following sequence: CH6, CH7, CH0, CH1, CH2, CH3

ANE2 ANE1 ANE0 End channel

0 0 0 AN0

0 0 1 AN1

0 1 0 AN2

0 1 1 AN3

1 0 0 AN4

1 0 1 AN5

1 1 0 AN6

1 1 1 AN7

248


17.3.2 Control Status Register (ADCS1)

The control status register (ADCS1) controls the A/D converter and indicates the status.

■ A/D Control Status Register (ADCS1)

Figure 17.3-4 A/D Control Status Register (ADCS1)

[bit 15] BUSY (busy flag and stop):

- Read

This bit indicates the A/D converter operation.

This bit is set when A/D conversion starts and is cleared when the conversion ends.

- Write

Writing "0" to this bit during A/D conversion forces the conversion to terminate.

The above feature is used for forced stop in continuous or stop mode.

"1" cannot be written to the BUSY bit. With a read-modify-write (RMW) instruction, "1" isread from this bit. In single mode, this bit is cleared at the end of A/D conversion.

In continuous or stop mode, this bit is not cleared until conversion is stopped by writing "0".

This bit is initialized to "0" upon a reset.

Do not perform a forced stop and activation by software simultaneously (BUSY = 0, STRT =1).

[bit 14] INT (Interrupt):

This bit is set when conversion data is written to ADCR.

An interrupt request is issued if this bit is set while bit 5 (INTE) is "1". In addition, the EI2OSis activated if it is enabled. Writing "1" has no effect.

This bit is cleared by writing "0" or by the EI2OS interrupt clear signal.

Note: To clear this bit by writing "0", ensure that A/D conversion is not in progress.

This bit initialized to "0" upon a reset.

STS1 STS0 STRT ReservedPAUS

15 14 13 12 11 10 9 8

INTEBUSY INTAddress: 000035H ADCS1


(0) (0) (0) (0) (0) (0) (0) (0)Read/writeInitial value

Bit No.

A/D control status register (upper)

249


[bit 13] INTE (Interrupt enable):

This bit is used to enable or disable interrupts at the end of conversion.

- 0: Interrupts are disabled.

- 1: Interrupts are enabled.

Set this bit when using the EI2OS. The EI2OS is activated when an interrupt request isissued.

Upon a reset, this bit is initialized to "0".

[bit 12] PAUS (A/D conversion pause):

This bit is set when the A/D conversion is paused.

Only one register is available for storing the A/D conversion result. Therefore, unless the

conversion results are transferred by the EI2OS, the result data would be continuouslyupdated and destroyed in continuous conversion.

To prevent the above condition, the system is designed so that a data register value must be

transferred by the EI2OS before the next conversion data is saved. A/D conversion pauses

during that period. A/D conversion is resumed at the end of transfer by the EI2OS.

This register is valid only when the EI2OS is used.

Note:

For the conversion data protection function, see Section 17.4 "Operations of A/D Converter".


[bits 11 and 10] STS1 and STS0 (Start source select):


These bits are used to select the A/D conversion activation source.

In a mode allowing two or more activation factors, A/D conversion is activated by the sourcethat occurs first.

The activation source setting changes as soon as it is updated. Thus, take care whenupdating it during A/D conversion.

Note:

The external pin trigger is detected by the falling edge. If this bit is updated to external triggeractivation while the external trigger input level is "L", A/D may be activated at once.

When timer is selected, the 16-bit Reload Timer 1 is selected.

STS1 STS0 Function

0 0 Activation by software

0 1 Activation by external pin trigger and software

1 0 Activation by timer and software

1 1 Activation by external pin trigger, timer, and software

250


[bit 9] STRT (Start):

A/D conversion is activated when "1" is written to this bit.

To reactivate A/D conversion, write "1" to this bit again.


In the stop mode, a reactivation during the operation is not supported. Check the BUSY bitbefore writing "1".

Do not perform a forced stop and activation by software simultaneously. (BUSY=0, STRT=1)

[bit 8] Reserved bit


251


17.3.3 Data Registers (ADCR1 and ADCR0)

These registers are used to store the digital values produced as a result of the conversion. ADCR1 stores the most significant two bits of the conversion result, while ADCR0 stores the lower eight bits. These register values are updated each time conversion is completed. Usually, the final conversion value is stored in these bits.

■ Data Registers (ADCR1 and ADCR0)

Figure 17.3-5 Data Registers (ADCR1 and ADCR0)

"0" is always read from the bits 10 to 15 of ADCR1.

The conversion data protection function is available. See Section 17.4 "Operations of A/DConverter" for details. Ensure that no data is written to these registers during A/D conversion.

[bits 15] S10

This bit specifies the resolution of the conversion. When it is set to "0", the 10-bit A/Dconversion is performed. Otherwise the 8-bit A/D conversion is performed and the result isstored in the D7 to D0.

Reading this bit always returns "0".

Address : 000037 H

Address : 000036 H ADCR0

ADCR1SI0 ST1 ST0 CT1 CT0 D9 D8

(R) (R) (R) (R) (R) (R) (R) (R)

(X) (X) (X) (X) (X) (X) (X) (X)

(W) (W) (W) (W) (W) (-) (R) (R)

(0) (0) (0) (0) (1) (-) (X) (X)


Bit No.


Bit No.

D6D7 D5 D4 D3 D2 D1 D0

7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8

Data register (lower)

Data register (upper)

252


[bits 14 and 13] ST1 and ST0 (Sampling time):

These bits determines the duration of the voltage sampling time at the input.

Reading these bits always returns "00".

[bits 12 and 11] CT1 and CT0 (Compare time):

These bits determines the duration of the compare operation time.

Do not set to "00" unless the machine clock is 8MHz. Otherwise the conversion accuracy isnot guaranteed.

Reading these bits always returns "00".

ST1 ST0 Function

0 0 64 machine cycles (4μs at 16MHz)

0 1 Reserved

1 0 Reserved


CT1 CT0 Function



1 0 Reserved

1 1 Reserved

253


17.4 Operations of A/D Converter

The A/D converter operates employs the sequential compare technique, and has a 10-bit resolution.Since the A/D converter has only one register (16 bits) for storing the conversion result, the conversion data registers (ADCR0 and ADCR1) are updated each time conversion is completed. Thus, the A/D converter alone must not be used for the

continuous conversion. Use the Extended intelligent I/O service (EI2OS) function to transfer converted data to memory while conversion is in progress.The operation modes are explained below.

■ Single Mode

In this mode, the converter sequentially converts the analog inputs specified with the ANS andANE bits. The converter stops operation after the conversion is completed for the end channelspecified with the ANE bits. If the start and end channels are the same (ANS = ANE),conversion is performed only for one channel.

Example:

ANS = 0 0 0, ANE = 0 1 1

Start -> AN0 -> AN1 -> AN2 -> AN3 -> End

ANS = 0 1 0, ANE = 0 1 0

Start -> AN2 -> End

■ Continuous Mode

In this mode, the converter sequentially converts the analog inputs specified with the ANS andANE bits. After the conversion is completed for the end channel specified with the ANE bits,conversion is repeated from the analog inputs of the ANS. If the start and end channels are thesame (ANS = ANE), conversion for one channel is repeated.

Example:

ANS = 0 0 0, ANE = 0 1 1

Start -> AN0 -> AN1 -> AN2 -> AN3 -> AN0 -> Repeat

ANS = 0 1 0, ANE = 0 1 0

Start -> AN2 -> AN2 -> AN2 -> Repeat

In continuous mode, conversion is repeated until "0" is written to the BUSY bit. (Writing "0" tothe BUSY bit forces the operation to end.) If the operation is terminated forcibly, conversionstops before conversion is completed. (Upon a forced stop, the conversion register stores thelast data that has been converted completely.)

254

17.4 Operations of A/D Converter

■ Stop Mode

In this mode, the converter sequentially converts the analog inputs specified with the ANS andANE bits, pausing each time conversion for one channel is completed. To release pausing,activate the converter again.

After the conversion is completed for the end channel specified with the ANE bits, conversion isrepeated from the analog inputs of the ANS. If the start and end channels are the same (ANS =ANE), conversion is performed only for one channel.

Example:

ANS = 0 0 0, ANE = 0 1 1

Start -> AN0 -> End -> Restart -> AN1 -> End -> Restart -> AN2 -> End ->

-> Restart -> AN3 -> End -> Restart --->AN0 Repeat

ANS = 0 1 0, ANE = 0 1 0

Start -> AN2 -> End -> Restart -> AN2 -> End -> Restart -> AN2 Repeat

Only the activation sources specified with STS1 and STS0 are used.

Using this mode, start of conversion can be synchronized with the activation source.

255


17.5 Conversion Using EI2OS

Figure 17.5-1 "A/D conversion processing flow from the start to converted data transfer (in continuous mode)" shows the processing flow from the start of A/D conversion to the transfer of converted data (in continuous mode).

■ Conversion Using EI2OS

Figure 17.5-1 A/D conversion processing flow from the start to converted data transfer (in continuous mode)

Starting A/D conversion

Sample and hold

Conversion

End of conversion

Issuing interrupt

Starting EI2

2

OS

Transferring data

Clearing interrupt

Interrupt processing

The portion indicated by the star ( ) is determined according to the EI OS setting.

256


17.5.1 Starting EI2OS in Single Mode

Follow the steps below to start the EI2OS in single mode.• To terminate conversion after analog inputs AN1 to AN3 are converted• To transfer conversion data sequentially to addresses 200H to 205H

• To start conversion by software• To use the highest interrupt level

■ Starting EI2OS in Single Mode

Table 17.5-1 Example of Starting EI2OS in Single Mode

Settings Sample program Function

EI2OS setting MOV ICR3, #08H Specifies the highest interrupt level, EI2OS activation upon an interrupt, and the descriptor address.

MOV BAPL, #00H Specifies the transfer destination address of converted data.

MOV BAPM, #02H

MOV BAPH, #00H

MOV ISCS, #18H Specifies word data transfer. The transfer destination address is incremented after transfer. Data is transferred from I/O to memory. Transfer is not terminated in response to a request from a resource.

MOV I / OA, #36H

MOV DCT, #03H EI2OS transfer is performed three times. This count is the same as the conversion count.

A/D converter setting

MOV ADCS0 #0BH Specifies single mode, start channel AN1, and end channel AN3.

MOV ADCS1 #A2H Specifies activation by software and start of A/D conversion.

Interrupt sequence

RET Specifies return from an interrupt.

ICR3: Interrupt control registerBAPL: Buffer address pointer, low-orderBAPM: Buffer address pointer, medium-orderBAPH: Buffer address pointer, high-orderISCS: EI2OS status registerI/OA: I/O address counterDCT: Data counter

257


Figure 17.5-2 Example of Starting EI2OS in Single Mode

Activation AN1 Interrupt EI2OS transfer

AN2 Interrupt EI2OS transfer


End Interrupt sequenc

Parallel processing

258


17.5.2 Starting EI2OS in Continuous Mode

Follow the steps below to start the EI2OS in continuous mode.• To convert analog inputs AN3 to AN5 and obtain two conversion data items for each

channel• To transfer conversion data sequentially to addresses 600H to 60BH

• To start conversion by external edge input• To use the highest interrupt level

■ Starting EI2OS in Continuous Mode

Table 17.5-2 Example of Starting EI2OS in Continuous Mode




MOV BAPM, #06H

MOV BAPH, #00H


MOV I / OA, #36H Transfer source address

MOV DCT, #06H EI2OS transfer is performed six times. Data is transferred for three channels x 2.

A/D converter setting MOV ADCS0 #9DH Specifies continuous mode, start channel AN3, and end channel AN5.

MOV ADCS1 #A4H Specifies activation by external edge and start of A/D conversion.

Interrupt sequence MOV ADCS1 #00H Specifies return from an interrupt.

RET


259


Figure 17.5-3 Example of Starting EI2OS in Continuous Mode

Activation AN3 Interrupt 2OS transfer


AN5 Interrupt 2OS transfer Interrupt sequenc

End

After six transfers

EI

EI

260


17.5.3 Starting EI2OS in Stop Mode

Follow the steps below to start the EI2OS in stop mode.• To convert analog input AN3 12 times at fixed intervals• To transfer conversion data sequentially to addresses 600H to 617H

• To start conversion by external edge input• To use the highest interrupt level

■ Starting EI2OS in Stop Mode

Table 17.5-3 Example of Starting EI2OS in Stop Mode




MOV BAPM, #06H

MOV BAPH, #00H


MOV I / OA, #36H Transfer source address

MOV DCT, #0CH EI2OS transfer is performed 12 times.

A/D converter setting MOV ADCS0 #DBH Specifies stop mode, start channel AN3, and end channel AN3 (one-channel conversion).

MOV ADCS1 #A4H Specifies activation by external edge and start of A/D conversion.

Interrupt sequence for terminating EI2OS

MOV ADCS1 #00H Specifies return from an interrupt.

RET


261


Figure 17.5-4 Example of Starting EI2OS in Stop Mode

Activation AN3 → Interrupt → EI2OS transfer

Stop

Activation by external edgeInterrupt sequenc

After 12 transfers

End

262

17.6 Conversion Data Protection

17.6 Conversion Data Protection

The A/D converter has a conversion data protection function that enables continuous

conversion and preservation of multiple data items using EI2OS.One conversion data register is provided, and its value is updated after conversion. When continuous A/D conversion is performed, conversion data is stored upon completion of each conversion and the previous data is lost. To prevent this situation, the A/D converter pauses without storing conversion data in the register if the

previous data has not been transferred to memory by EI2OS, even though conversion has been completed.

■ Conversion Data Protection

The pause is released after data is transferred to memory by EI2OS.

If the previous data has been transferred to memory, the A/D converter continues operationwithout pausing.

Note:

This function is related to the INT and INTE bits of ADCS1.

The data protection function operates only when interrupts are enabled (INTE=1).

If interrupts are disabled (INTE=0), this function is disabled. Continuous A/D conversionresults in loss of previous data, since the converted data items are saved to the register oneafter another.

If EI2OS is not used while interrupts are enabled (INTE=1), the INT bit is not cleared. Thus,the data protection function works and the A/D converter pauses. In this case, clearing theINT bit in the interrupt sequence releases the pause.

If the A/D converter is pausing during EI2OS operation, disabling interrupts may restart theA/D converter. In this case, the value in the conversion data register may be changedwithout being transferred.

Restarting the A/D converter while it is pausing destroys the standby data.

263


■ Flow of Data Protection Function (When EI2OS is Used)

Figure 17.6-1 Flow of Data Protection Function (When EI2OS Is Used)

■ Notes on using the conversion data protection function

To start the A/D converter upon an external trigger or internal timer, A/D activation factor bitsSTS1 and STS0 of the ADCS2 register are used. Ensure that the input values of the externaltrigger or internal timer are inactive. If the values are active, A/D conversion may startimmediately.

When setting STS1 and STS0, ensure that "1" (input) is specified for ADTG and "0" (output) isspecified for the internal timer (timer 2).

NO

YESYES NO

*

Setting EI2OS

Starting continuous A/D conversion

Ending first conversion

Saving the result in the data register

Ending second conversion

End EI2OS?

Saving the result in the data register

Ending third conversion

Continued

Ending the last conversion

End

Starting EI2OS

Pausing A/D conversion

Interrupt routineStooping A/D conversion

*: If the converter is restarted when it is pausing, standby conversion data is lost.

Starting EI2OS

Starting EI2OS

End EI2OS?

264

CHAPTER 18 UART0

This chapter explains the UART0 functions and operations.

18.1 "Feature of UART0"

18.2 "UART0 Block Diagram"

18.3 "UART0 Registers"

18.4 "UART0 Operation"

18.5 "Baud Rate"

18.6 "Internal and External Clock"

18.7 "Transfer Data Format"

18.8 "Parity Bit"

18.9 "Interrupt Generation and Flag Set Timings"

18.10 "UART0 Application Example"

265

CHAPTER 18 UART0

18.1 Feature of UART0

UART0 is a serial I/O port for asynchronous (start-stop) or CLK synchronous communication with external devices.

■ Feature of UART0

UART0 has the following features.

• Full duplex double buffer

• Supports CLK synchronous and CLK asynchronous start-stop data transfer.

• Multiprocessor mode support (mode 2)

• Internally dedicated baud rate generator (12 types)

• Supports flexible baud rate setting using an external clock input or internal timer.

• Variable data length (7 to 9 bits, [no parity]; 6 to 8 bits [with parity]).

• Error detect function (framing, overrun, and parity)

• Interrupt function (receive and transmit interrupts) Error detect function (framing, overrun,and parity)

• NRZ type transfer format

266

18.2 UART0 Block Diagram


Figure 18.2-1 "Overall Block Diagram" shows a block diagram of the UART0.

■ UART0 Block Diagram

Figure 18.2-1 Overall Block Diagram

Control signal

SCK0

SIN0

SCK0

SOT0

UIDR0

Control signal

PENSBLMC1MC0SMDERFCSCKESOE

RDRFORFEPETDRERIETIERBFTBF

BCHRC3RC2RC1RC0BCH0PD8

UMC0 USR0 URD0

Dedicated baud rate clock

16-bit reload timer 0Clock selectcircuit

Receive clock

Transmit clock

Receive interrupt(to CPU)

Transmit interrupt(to CPU)

Receive control circuit

Start bit detectcircuit

Receive bit counter

Receive paritycounter

Transmit control circuit

Transmit start circuit

Transmit bit counter

Transmit paritycounter

Receive statusevaluation circuit

Receive shifter

Receivecomplete

Transmit shifter

Transmit start

Receive errorindication signalfor EI2OS (to CPU)

Internal data bus

register register register

UODR0

267

CHAPTER 18 UART0

18.3 UART0 Registers

The UART0 has the following four registers:• Serial mode control register• Status register• Input data register/output data register• Rate and data register

■ UART0 Registers

Figure 18.3-1 UART0 Register

7 6 5 4 3 2 1 0

PEN SBL MC1 MC0 SMDE RFC SCKE SOE UMC0

(R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) (0) (0) (0) (0) (0) (1) (0) (0)

Bit No.Serial mode control register 0

Address: 000020H


15 14 13 12 11 10 9 8

RDRF ORFE PE TDRE RIE TIE RBF TBF

(R) (R) (R) (R) (R/W) (R/W) (R) (R)

(0) (0) (0) (1) (0) (0) (0) (0)

USR0

Bit No.


Status register 0

Address: 000021H

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0


UIDR0 (read)UODR0 (write)

Bit No.


Input data register 0/

Address: 000022H

Output data register 0

15 14 13 12 11 10 9 8

BCH RC3 RC2 RC1 RC0 BCH0 P D8URD0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (X)

Bit No.


Rate and data register 0

Address: 000023 H

268


18.3.1 Serial Mode Control Register 0 (UMC0)

UMC0 specifies the operation mode of UART0. Set the operation mode while operation is halted. However, the RFC bit can be accessed during operation.

■ Serial Mode Control Register 0 (UMC0)

Figure 18.3-2 Serial Mode Control Register 0 (UMC0)

[Bit 7] PEN (Parity enable)

Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O.Set to "0" in mode 2.

0: Do not use parity

1: Use parity

[Bit 6] SBL (Stop bit length)

Specifies the number of stop bits for transmit data. For receive data, the first stop bit only isrecognized and any second stop bit is ignored.

0: 1 bit length

1: 2 bits length

[Bits 5, 4] MC1, MC0 (Mode control)

These bits control the length of the transferred data. Table 18.3-1 "UART0 OperationModes" lists the four transfer modes (data lengths) selectable by these bits.

7 6 5 4 3 2 1 0

PEN SBL MC1 MC0 SMDE RFC SCKE SOE UMC0

(R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W)

(0) (0) (0) (0) (0) (1) (0) (0)

Bit No.Serial mode control register 0

Address: 000020H

Read/write

Initial value

Table 18.3-1 UART0 Operation Modes

Mode MC1 MC0 Data Length*1

0 0 0 7 (6)

1 0 1 8 (7)

2*2 1 0 8 + 1

3 1 1 9 (8)

*1: The figures enclosed in parentheses indicate the data length with parity.*2: Mode 2 is used when a number of slave CPUs are connected to a single host CPU. As the receive parity check function cannot be used, set PEN in the UMC0 register to "0" (see Section 18.4 "UART0 Operation" for details). The transmit data length is 9 bits and no parity bit can be added.

269

CHAPTER 18 UART0

[Bit 3] SMDE (Synchro mode enable)

This bit selects the transfer method.

0:Start-stop CLK synchronous transfer (clocked synchronous transfer using start and stopbits.)

1:Start-stop CLK asynchronous transfer

[Bit 2] RFC (Receiver flag clear)

Writing "0" to this bit clears the RDRF, ORFE, and PE flags in the USR0 register. Writing "1"has no effect. Reading always returns "1".

Note:

When receive interrupts are enabled during UART0 operation, only write "0" to RFC wheneither RDRF, ORFE, or PE is "1".

[Bit 1] SCKE (SCLK enable)

Writing "1" to this bit in CLK synchronous mode switches the port pin to the UART0 serialclock output pin and outputs the synchronizing clock. Set to 0 in CLK asynchronous mode orexternal clock mode.

0: The pin functions as a general purpose I/O port and does not output the serial clock. Thepin functions as the external clock input pin when the port is set to input mode (DDR=0)and RC3 to 0 are set to "1111".

1: The pin functions as the UART0 serial clock output pin.

[Bit 0] SOE (Serial Output Enable)

Writing 1 to this bit switches the port pin to the UART0 serial data output pin, enabling serialoutput.

0: The pin functions as a port pin and does not output serial data.

1: The pin functions as the UART0 serial data output pin (SOT).

270


18.3.2 Status Register 0 (USR0)

USR0 indicates the current state of the UART0 port.

■ Status Register 0 (USR0)

Figure 18.3-3 Status Register 0 (USR0)

[Bit 15] RDRF (Receiver data register full)

This flag indicates the state of the UIDR0 (input data register). The flag is set when thereceive data is loaded into UIDR0. Reading UIDR0 or writing "0" to RFC in the UMC0register clears the flag. If RIE is active, a receive interrupt request is generated when RDRFis set.

0: No data in UIDR0

1: Data present in UIDR0

[Bit 14] ORFE (Over-run/framing error)

The flag is set when an overrun or framing error occurs in receiving. Writing "0" to RFC in theUMC0 register clears the flag. When this flag is set, the data in UIDR0 is invalid and the loadfrom the receive shifter to UIDR0 is not performed. If RIE is active, a receive interruptrequest is generated when ORFE is set.

0: No error

1: Error

Table 18.3-2 "UIDR0 State after Receive Completion" lists the UIDR0 states after receivecompletion by RDRF or ORFE.

The data in UIDR0 is invalid if an overrun or framing error has occurred. Next data can bereceived after clearing the flag(s).

15 14 13 12 11 10 9 8

RDRF ORFE PE TDRE RIE TIE RBF TBF

(R) (R) (R) (R) (R/W) (R/W) (R) (R)

(0) (0) (0) (1) (0) (0) (0) (0)

USR0

Bit No.


Status register 0

Address: 000021H

Table 18.3-2 UIDR0 State after Receive Completion

RDRF ORFE UIDR0 Data State

0 0 Empty

0 1 Framing error

1 0 Valid data

1 1 Overrun error

271

CHAPTER 18 UART0

[Bit 13] PE (Parity error)

The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC0 registerclears the flag. When this flag is set, the data in UIDR0 is invalid and the load from thereceive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request isgenerated when PE is set.

0: No parity error

1: Parity error

[Bit 12] TDRE (Transmitter data register empty)

This flag indicates the state of the UODR0 (output data register). Writing transmit data to theUODR0 register clears the flag. The flag is set when the data is loaded to the transmit shifterand the transmission is started. If TIE is active, a transmit interrupt request is generatedwhen TDRE is set.

0: Data present in UODR0

1: No data in UODR0

[Bit 11] RIE (Receiver interrupt enable)

Enables receive interrupt requests.

0: Disable interrupts.

1: Enable interrupts.

[Bit 10] TIE (Transmitter interrupt enable)

Enables transmit interrupt requests. A transmit interrupt is generated immediately if transmitinterrupts are enabled when TDRE is "1".

0: Disable interrupts.

1: Enable interrupts.

[Bit 9] RBF (Receiver busy flag)

This flag indicates that UART0 is receiving input data. The flag is set when the start bit isdetected and cleared when the stop bit is detected.

0: Receiver idle

1: Receiver busy

[Bit 8] TBF (Transmitter busy flag)

This flag indicates that UART0 is transmitting input data. The flag is set when transmit datais written to the UODR0 register and cleared when transmission completes.

0: Transmitter idle

1: Transmitter busy

272


18.3.3 Input Data Register 0 (UIDR0) and Output Data Register 0 (UODR0)

UIDR0 (input data register 0) is the serial data input register. UODR0 (output data register 0) is the serial data output register.The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and the most significant bit (D7) is ignored if the data length is 7 bits. Write to UODR0 only when TDRE = "1" in the USR0 register. Read UIDR0 only when RDRF = "1" in the USR0 register.

■ Input Data Register 0 (UIDR0) and Output Data Register 0 (UODR0)

Figure 18.3-4 Input Data Register 0 (UIDR0) and Output Register 0 (UODR0)

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0


(X) (X) (X) (X) (X) (X) (X) (X)

UIDR0 (read)UODR0 (write)

Bit No.


Address: 000022H

Serial input data register 0Serial output data register 0

273

CHAPTER 18 UART0

18.3.4 Rate and Data Register 0 (URD0)

URD0 selects the data transfer speed (baud rate) for UART0. The register also holds the most significant bit (bit 8) of the data when the transmit data length is 9 bits. Set the baud rate and parity when UART0 is halted.

■ Rate and Data Register 0 (URD0)

Figure 18.3-5 Rate and Data Register 0 (URD0)

[Bits 15, 10] BCH, BCH0 (Baud rate clock change)

Specifies the machine cycles for the baud rate clock (see Section 18.4 "UART0 Operation"for details).

Note:

Do not set BCH and BCH0 to "00".

[Bits 14 to 11] RC3, RC2, RC1, RC0 (Rate control)

Selects the clock input for the UART0 port (see Section 18.4 "UART0 Operation" for details).

Note:

Do not set the rate control bits to "1100" "1110".

15 14 13 12 11 10 9 8

BCH RC3 RC2 RC1 RC0 BCH0 P D8 URD0


(0) (0) (0) (0) (0) (0) (0) (X)

Bit No.


Rate and data register 0

Address: 000023H

Table 18.3-3 Clock Input Selection

BCH BCH0 Divider ratio Setting Example for Each Machine Cycle

0 0 - - Prohibited setting -

0 1 Divide by 4 For a 16 MHz machine cycle: 16/4 = 4 MHz



Table 18.3-4 Clock Input Selection

RC3 to RC0 Clock Input

"0000" to "1011" Dedicated baud rate generator

"1101" 16-bit Reload Timer 0

"1111" External clock

274


[Bit 9] P

Sets even or odd parity when parity is active (PEN = "1").

0: Even parity

1: Odd parity

[Bit 8] D8

Holds the bit 8 of the transfer data in mode 2 or 3 (9-bit data length) and no parity. Treatedas bit 8 of the UIDR0 register for reading. Treated as bit 8 of the UODR0 register for writing.The bit has no meaning in the other modes. Write to D8 only when TDRE = "1" in the USR0register.

275

CHAPTER 18 UART0

18.4 UART0 Operation

Table 18.4-1 "UART0 Operating Modes" lists the operating modes for UART0. Set the UMC0 register to switch between modes.

■ UART0 Operation Modes

Note:

UART0 uses start-stop clock synchronous transfer. Therefore, a start and stop bit are addedto the data even in clock synchronous transfer.

Table 18.4-1 UART0 Operating Modes

Mode Parity Data Length Clock Mode Length of Stop Bits*

0On 6

CLK asynchronous or CLK synchronous

1 bit or 2 bits

Off 7

1On 7

Off 8

2 Off 8+1

3On 8

Off 9

*: The number of stop bits can only be set for transmission. The number of receive stop bits is always set to one. Do not set modes other than those listed above. UART0 does not operate if an invalid mode is set.

276

18.5 Baud Rate

18.5 Baud Rate

When the dedicated baud rate generator is used, the following two types of baud rates are available:• CLK synchronous baud rate• CLK asynchronous baud rate

■ CLK Synchronous Baud Rate

The five URD0 register bits: BCH, BCH0 and RC3, RC2, RC1 select the baud rate for CLKsynchronous transfer.

First select the machine clock divider ratio using BCH and BCH0.

Then, set the division ratio for the clock selected above in RC3, RC2, and RC1. The followingthree settings are available for CLK synchronous transfer. Other settings are prohibited.

■ CLK Asynchronous Baud Rate

The six URD0 register bits: BCH, BCH0 and RC3, RC2, RC1, RC0 select the baud rate for CLKasynchronous transfer.

First select the machine clock divider ratio using BCH and BCH0.

Then, set the asynchronous transfer clock division ratio for the clock selected above in RC3,RC2, RC1, and RC0. The following settings are available.

BCH BCH0

0 1 ⇒ Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]



RC3 RC2 RC1

0 1 0 ⇒ Divide by 2 [For example, at 4 MHz: 4/2 = 2.0 M (bps)]

0 1 1 ⇒ Divide by 4 [For example, at 4 MHz: 4/4 = 1.0 M (bps)]

1 0 0 ⇒ Divide by 8 [For example, at 4 MHz: 4/8 = 0.5 M (bps)](At 2 MHz, the speed becomes half the above examples.)

BCH BCH0




277

CHAPTER 18 UART0

The above 12 baud rates can be selected. The following formula shows how to calculate theCLK synchronous baud rate.

where φ is a machine cycle and m is in decimal notation for RC3 to 1.

Note:

The above formula for m=0 or m=1 cannot be calculated.

Data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1%. Thebaud rate is the CLK synchronous baud rate divided by 8 x 13, 8 x 12, or 8.

Table 18.5-1 "Baud Rate" shows examples for 16 MHz, 12 MHz, and 10 MHz machinecycles. However, do not use the settings marked as "-" in the table.

RC3 RC2 RC1 RC0

0 0 0 ⇒ Divide by 8 × 1

0 1 0 ⇒ Divide by 8 × 2 0 ⇒ Divide by 12

0 1 1 ⇒ Divide by 8 × 4 1 ⇒ Divide by 13

1 0 0 ⇒ Divide by 8 × 8

0 0 1 ⇒ Not divided 0 ⇒ Prohibited setting

1 0 1 ⇒ Divide by 8 1 ⇒ Divide by 8

⎧⎪⎨⎪⎪⎩

⎧⎪⎨⎪⎪⎩⎧

⎪⎪⎨⎪⎩

⎧⎪⎪⎨⎪⎩

×

×

Baud rate =

Baud rate =

Baud rate =

φ/42m-1

φ/3

2m-1

φ/52m-1

[bps] (machine cycle = 16 MHz)



278

18.5 Baud Rate

Table 18.5-1 Baud Rate

CLK asynchronous (μs/Baud)CLK

asynchronous divider ratio

CLK synchronous (μs/Baud)

16 MHz 12 MHz 10 MHz 16 MHz 12 MHz 10 MHz

RC3

RC2

RC1

RC0

BCH/0=01 BCH/0=10 BCH/0=11 BCH/0=01 BCH/0=10 BCH/0=11

0 0 0 0 - - 48/ 20833 8 x 12 - - -

0 0 0 1 26/ 38460 26/ 38460 52/ 19230 8 x 13 - - -

0 0 1 0 - - - 8 - - -

0 0 1 1 2/500000 2/500000 4/250000 8 - - -

0 1 0 0 48/ 20833 48/ 20833 96/10417 8 x 12 - - -

0 1 0 1 52/ 19230 52/ 19230 104/ 9615 8 x 13 0.5 / 2M 0.5 / 2M 1 / 1M

0 1 1 0 96/10417 96/10417 192/ 5208 8 x 12 - - -

0 1 1 1 104/ 9615 104/ 9615 208/ 4808 8 x 13 1 / 1M 1 / 1M 2 / 500K

1 0 0 0 192/ 5208 192/ 5208 - 8 x 12 - - -

1 0 0 1 208/ 4808 208/ 4808 416/ 2404 8 x 13 2 / 500K 2 / 500K 4 / 250K

1 0 1 0 - - - 8 - - -

1 0 1 1 16/ 62500 16/ 62500 32/ 31250 8 - - -

279

CHAPTER 18 UART0

18.6 Internal and External Clock

Setting RC3 to 0 to "1101" selects the clock signal from the 16-bit Reload Timer. Setting RC3 to 0 to "1111" selects the external clock.

■ Internal and External Clock

The CLK asynchronous baud rate is the CLK synchronous baud rate divided by 8. Also, datatransfer is possible if the CLK asynchronous baud rate is in the range -1% to +1% of theselected baud rate. Table 18.6-1 "Baud Rate and Reload Value" lists the baud rates when theinternal timer is selected as the clock. The values in this table are calculated for a machine cycleof 7.3728 MHz. However, do not use the settings marked as "-" in the table.

The values in the table are the reload values (decimal) for reload count operation of the 16-bitReload Timer.

Table 18.6-1 Baud Rate and Reload Value

Baud Rate

Reload Value

X = 21

(divide machine cycle by 2)X = 23

(divide machine cycle by 8)

76800 2 -

38400 5 -

19200 11 2

9600 23 5

4800 47 11

2400 95 23

1200 191 47

600 383 95

300 767 191

Baud rate=φ / X

8 × 2 (n+1)[bps]

φ: Machine cycle

X: Divider ratio for the count clock source forthe internal timer

n: Reload value (decimal)

⎛⎜⎜⎜⎜⎝

⎞⎟⎟⎟⎟⎠

280

18.7 Transfer Data Format

18.7 Transfer Data Format

UART0 only handles NRZ (non-return-to-zero) type data. Figure 18.7-1 "Transfer Data Format" shows the relationship between the transmit/receive clock and the data for CLK synchronous mode.

■ Transfer Data Format

Figure 18.7-1 Transfer Data Format

As shown in Figure 18.7-1 "Transfer Data Format", the transfer data always starts with the startbit (L level data), the specified number of data bits are transmitted with the LSB first, thentransmission ends with the stop bit ("H" level data). Always input a clock if external clockoperation is selected. When an internal clock (the dedicated baud rate generator or 16-bitReload Timer) is selected, the clock is output continuously. When using CLK synchronoustransfer, do not start data transfer until the selected baud rate clock has stabilized (for two baudrate clock cycles).

When using CLK asynchronous transfer, set the SCKE bit in the UMC0 register to "0" to disableclock output. The transfer data format of SIN0 and SOUT0 is the same as shown in Figure 18.7-1 "Transfer Data Format".

SCK0

SIN0, SOT0

0 1 0 1 1 0 1 00 1 1Start LSB MSB Stop

D8 Stop⎫⎬⎭

Dependson the mode.

The transferred data is 01001101B (mode 1) or 101001101B (mode 3).

281

CHAPTER 18 UART0

18.8 Parity Bit

The P bit in the URD0 register specifies whether to use even or odd parity when parity is enabled. The PEN bit in the UMC0 register enables parity.

■ Parity Bit

Inputting the data shown in Figure 18.8-1 "Serial Data with Parity Enabled" to SIN0 when evenparity is set causes a receive parity error. Figure 18.8-1 "Serial Data with Parity Enabled" alsoshows the data transmitted when sending 001101B with even parity and odd parity.

Figure 18.8-1 Serial Data with Parity Enabled

SIN0

0 1 0 1 1 0 0 10Start LSB MSB Stop

(Parity)

SOT0


(Parity)

SOT0


(Parity)

(Receive parity error occurs P = 0)

(Even parity transmission P = 0)

(Odd parity transmission P = 1)

282

18.9 Interrupt Generation and Flag Set Timings


UART0 has two interrupt causes and six flags. The two interrupt causes are the receive and transmit interrupts. The six flags are RDRF, ORFE, PE, TDRE, RBF, and TBF. For reception, the RDRF, ORFE, and PE flags request an interrupt. For transmission, the TDRE flag requests an interrupt.

■ Set Timings of the Six Flags

❍ RDRF flag

The RDRF flag is set when receive data is loaded into the UIDR0 register. The flag is clearedby writing "0" to RFC in the UMC0 register or by reading the UIDR0 register.

❍ ORFE flag

The ORFE flag is an overrun or framing error flag. The flag is set when a receive error occursand is cleared by writing "0" to RFC in the UMC0 register.

❍ PE flag

The PE flag is a reception parity error flag. The flag is set when a receive parity error occursand is cleared by writing "0" to RFC in the UMC0 register. Note that the parity detect function isnot available in mode 2.

❍ TDRE flag

The TDRE flag is set when the UODR0 register becomes empty and is available for writing. Theflag is cleared by writing to the UODR0 register. The above four flags (RDRF, ORFE, PE, andTDRE) trigger transmit or receive interrupts.

❍ RBF and TBF flags

The RBF and TBF flags indicate that reception or transmission is in progress. The RBF flagbecomes active during reception, and the TBF flag becomes active during transmission.

283

CHAPTER 18 UART0

18.9.1 Flag Set Timings for a Receive Operation (in Mode 0, 1, or 3)

The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated when the final stop bit is detected indicating the end of reception transfer. The data in UIDR0 is invalid when either the ORFE or PE bit is active.

■ Flag set Timings for a Receive Operation (in Mode 0, 1, or 3)

Figure 18.9-1 "RDRF Set Timing (Mode 0, 1, or 3)", Figure 18.9-2 "ORFE Set Timing (Mode 0,1, or 3)", and Figure 18.9-3 "PE Set Timing (Mode 0, 1, or 3)" show the set timings of the RDRF,ORFE, and PE flags respectively.

Figure 18.9-1 RDRF Set Timing (Mode 0, 1, or 3)

Figure 18.9-2 ORFE Set Timing (Mode 0, 1, or 3)

Figure 18.9-3 PE Set Timing (Mode 0, 1, or 3)

Stop (Stop)

RDRF

Data

Receive interrupt

Stop

RDRF = 1

ORFE

Stop

RDRF = 0

ORFE

Data

Receive interrupt

(Overrun error) (Framing error)

Receive interrupt

Data

Stop (Stop)

PE

Data

Receive interrupt

284


18.9.2 Flag Set Timings for a Receive Operation (in Mode 2)

The RDRF flag is set when the final stop bit is detected and reception transfer ends with the last data bit (D8) having the value "1".The ORFE flag is set when the final stop bit is detected, irrespective of the value of the last data bit (D8). The data in UIDR0 is invalid when the ORFE bit is active.The interrupt request to the CPU is generated when either of the flags are set (see Section 18.10 "UART0 Application Example" for details on using mode 2).

■ Flag Set Timings for a Receive Operation (in Mode 2)

Figure 18.9-4 RDRF Set Timing (Mode 2)

Figure 18.9-5 ORFE Set Timing (Mode 2)

Stop (Stop)

RDRF

D6 D7 D8Data

Receive interrupt

Stop

RDRF = 1

ORFE

Stop

RDRF = 0

ORFE

D7 D8 D7 D8Data Data

Receive interrupt Receive interrupt

(Overrun error) (Framing error)

285

CHAPTER 18 UART0

18.9.3 Flag Set Timings for a Transmit Operation

TDRE is set and an interrupt request to the CPU is generated when the data written in UODR0 register is transferred to the internal shift register and the next data can be written to UODR0.

■ Flag Set Timings for a Transmit Operation

Figure 18.9-6 TDRE Set Timing (Mode 0)

ST: Start bit D0 to D7: Data bits SP: Stop bit

ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3

TDRE

UODR0 write

Transmit interrupt

SOT0 output

Interrupt request to the CPU

286


18.9.4 Status Flag During Transmit and Receive Operation

RBF is set when the start bit is detected and cleared when a stop bit is detected. The receive data in UIDR0 at the RBF clear timing is not yet valid. The data in UIDR0 becomes valid at the RDRF set timing.

■ Status Flag during Transmit and Receive Operation

Figure 18.9-7 "RBF Set Timing (Mode 0)" shows the relationship between the RBF and receiveinterrupt flag timing.

Figure 18.9-7 RBF Set Timing (Mode 0)

Writing the transmission data to UODR0 sets TBF. TBF is cleared when transmissioncompletes.

Figure 18.9-8 TBF Set Timing (Mode 0)

Note:

Receive operation starts after releasing a reset unless the SIN0 input pin is fixed at "1".Therefore, before setting the mode, write "0" to RFC in the UMC0 register to clear anyreceive flags that have been set.

Set the communication mode when the RBF and TBF flags in the USR0 register are "0". Thedata transmitted and received during mode setting cannot be guaranteed.

■ EI2OS (Extended intelligent I/O service)

See Section 3.6 "Extended Intelligent I/O Service (EI2OS)" for details about the extended

intelligent I/O service (EI2OS).

ST D0 D1 D2 D3 D4 D5 D6 D7 SP

RBF

RDRF, PE, ORFE

SIN0 input

ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP

TBF

UODR write

SOT0 output

287

CHAPTER 18 UART0

18.10 UART0 Application Example

Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure 18.10-1 "Example System Configuration Using Mode 2".)

■ Application Example of UART0

As shown in Figure 18.10-1 "Example System Configuration Using Mode 2", communicationstarts with the host CPU transmitting address data. The ninth bit (D8) of the address data is setto "1". The address selects the slave CPU with which communication will be established. Theselected slave CPU communicates with the host CPU using a protocol determined by the user.In normal data, D8 is set to "0". Unselected slave CPUs wait in standby until the nextcommunication session starts. Figure 18.10-2 "Communication Flowchart for Mode 2Operation" shows a flowchart of operation in this mode.

Because the parity check function is not available in this mode, set the PEN bit in the UMC0register to "0".

Figure 18.10-1 Example System Configuration Using Mode 2

SOT0

SIN0

SOT0 SIN0 SOT0 SIN0Host CPU

Slave CPU #0 Slave CPU #1

288

18.10 UART0 Application Example

Figure 18.10-2 Communication Flowchart for Mode 2 Operation

No

Yes

(Host CPU) (Slave CPU)

Start

Set the transfer mode to 3

Set the slave CPU selectionin D0 to D7. Set D8 to "1".Transfer the byte.

Set D8 to "0" and performcommunications

End

Start

Set the transfer mode to 2

Receive a byte

Selected?

Set the transfer mode to 3and enable SOT0 output

Perform communicationswith the master CPU

Use the status flag toconfirm transfer completion,then set the transfer mode to2 and disable SOT0 output

289

CHAPTER 18 UART0

290

CHAPTER 19 UART1 (SCI)

This chapter explains the UART1 (SCI) functions and operation.

19.1 "Features of UART1"

19.2 "UART1 Block Diagram"

19.3 "UART1 Registers"

19.4 "UART1 Operating Modes and Clock Selection"

19.5 "UART1 Flags and Interrupt Sources"

19.6 "UART1 Interrupts and Flag Set Timing"

19.7 "Negative Clock Operation"

19.8 "UART1 Sample Applications and Precautionary Information"

291


19.1 Features of UART1

The UART1 is a serial I/O port used for asynchronous (start-stop synchronized) communication as well as for CLK-synchronized communication.

■ Features of UART1

UART provides the following features.

• Full-duplex double buffer

• Asynchronous (start-stop synchronized) and CLK-synchronous communication capability

• Multi-processor mode support

• On-chip dedicated baud rate generator

At internal machine clock speeds of 6, 8, 10, 12, 16MHz.

• Asynchronous: 9615/31250/4808/2404/1202 bps

• CLK synchronous: 1M/500K/250K/125K/62.5 Kbps

• Automatic baud rate setting from external clock input or internal timer

• Error detection function (parity, framing, overrun)

• Transfer communication in NRZ transfer format

• Intelligent I/O service support

292



Figure 19.2-1 "UART1 Block Diagram" shows the UART1 block diagram.

■ UART1 Block Diagram

Figure 19.2-1 UART1 Block Diagram

Receive shifter

Receive

SIDR1

Dedicated baud

16-bit reload timer 0

External clock

Receive clock

Receive control circuit

Start bit detect circuit

Receive bit counter

Receive parity counter

Receive status decision circuit

I2OS receive error

Receive interrupt

Transmit clockTransmit

Transmit

Clockselector

Transmit shifter

SODR1

Start

Internal data bus

SIN1

indication signal (to CPU)

SOT1

SCK1

(to CPU)

interrupt(to CPU)

Control signals

SMR1register

MD1MD0CS2CS1CS0

SCKESOE

SCR1register

PENPSBLCLA/DRECRXETXE

SSR1register

PEOREFRERDRFTDRE

RIETIE

Control bus

rate generator

circuit

Transmit control circuit

Transmit start circuit

Transmit bit counter

Transmit parity counter

complete

293



Figure 19.3-1 "UART1 Register Configuration" lists the UART1 registers.

■ UART1 Registers

Figure 19.3-1 UART1 Register Configuration

Figure 19.3-2 UART1 Registers

15 8 7 0

SCR1 SMR1

SSR1 SIDR1(R)/SODR1(W)

– U1CDCR

(R/W)

(R/W)

(R/W)

8bit 8bit

7 6 5 4 3 2 1 0Address: 000024H MD1 MD0 CS2 CS1 CS0 Reseved SCKE SOE

Serial mode register 1

SMR1

15 14 13 12 11 10 9 8Address: 000025H PEN P SBL CL A/D REC RXE TXE SCR1

7 6 5 4 3 2 1 0Address: 000026H D7 D6 D5 D4 D3 D2 D1 D0 SIDR1(Read)

SODR1(Write)

15 14 13 12 11 10 9 8

Address: 000027HPE ORE FRE RDRF TDRE – RIE TIE SSR1

7 6 5 4 3 2 1 0

Address: 000028HMD – – – DIV3 DIV2 DIV1 DIV0 U1CDCR

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (0) (0)

Serial control register

(R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W)(0) (0) (0) (0) (0) (1) (0) (0)

Serial input data registerSerial output data register

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(X) (X) (X) (X) (X) (X) (X) (X)

Serial status register

(R) (R) (R) (R) (R) (-) (R/W) (R/W)(0) (0) (0) (0) (1) (-) (0) (0)

Prescaler control register

(R/W) (-) (-) (-) (R/W) (R/W) (R/W) (R/W)(0) (-) (-) (-) (1) (1) (1) (1)


Bit No.

Bit No.


Bit No.




Bit No.

Bit No.

294


19.3.1 Serial Mode Register 1 (SMR1)

The serial mode register 1 (SMR1) sets the operating mode of the UART1. Operating mode settings should be entered when the unit is not in operation. Do not write to this register during operation.

■ Serial Mode Register 1 (SMR1)

The SMR1 register has the following bit configuration.

Figure 19.3-3 Serial Mode Register 1(SMR1)

[bit 7, 6] MD1, MD0 (MoDe select)

These bits select the UART1 operation mode, according to the settings listed in Table 19.3-1"Operating Mode Selections".

Note:

Mode 1, CLK-asynchronous multi-processor mode, is used when one host CPU is connectedto multiple slave CPUs. This UART1 resource is not able to determine the data format ofincoming data, and therefore in multi-processor mode supports only the master processor.

Also, in this configuration the receive parity check function cannot be used, and therefore thePEN bit in the UMC1 register should be set to "0".

7 6 5 4 3 2 1 0Address: 000024H MD1 MD0 CS2 CS1 CS0 Reseved SCKE SOE

(R/W)

SMR1

Serial Mode Register 1

(R/W)(R/W)(R/W)(R/W)(R/W)(R/W)(R/W)

(0) (0) (0) (0) (0) (0) (0) (0)

Bit No.


Table 19.3-1 Operating Mode Selections

Mode MD1 MD0 Operating mode

0 0 0 Asynchronous (start-stop synchronized) normal mode

1 0 1 Asynchronous (start-stop synchronized) multi-processor mode

2 1 0 CLK synchronous mode

− 1 1 Prohibited

295


[bit 5 to bit 3] CS2, CS1, CS0 (Clock Select)

These bits select the baud rate clock source. The baud rate is determined at the same timeas selection of the baud rate generator. Table 19.3-2 "Clock Input Selection Settings" showsthe clock input selection settings.

[bit 2] Reserved


[bit 1] SCKE (SCLK Enable)

For communication in CLK synchronous mode (mode 2), this bit determines whether theSCK1 pin is used as a clock input pin or a clock output pin.

In CLK asynchronous modes or external clock mode, this bit should be set to "0".

0: SCK1 pin functions as clock input pin

1: SCK1 pin functions as clock output pin

Note:

When the pin functions as a clock input, an external clock source must be selected.

[bit0] SOE (Serial Output Enable)

This bit determines whether external pins that also can be used as general purpose I/O portpins will function as serial output pins (SOT1) or as I/O port pins.

0: General purpose I/O port pin function

1: Serial data output pin (SOT1) function

Table 19.3-2 Clock Input Selection Settings

CS2 to CS0 Clock input

000B to 100B Dedicated baud rate generator

101B Reserved

110B Internal timer*

111B External clock

*1: When the internal timer is selected, the MB90435 series selects 16-bit reload timer 0 output.

296


19.3.2 Serial Control Register 1 (SCR1)

The serial control register (SCR1) register controls the transfer protocol used for serial transmission.

■ Serial Control Register 1 (SCR1)

The SCR1 register has the following bit configuration.

Figure 19.3-4 Serial Control Register (SCR1)

[bit 15] PEN (Parity Enable)

This bit determines whether parity bits are attached to data in serial transmission.

0: No parity

1: Parity

Note:

Parity bit attachment is available only in asynchronous (start-stop synchronized)communications in normal mode (mode 0). In multi-processor mode (mode 1) and all CLK-synchronous communication (mode 2), no parity bits may be attached.

[bit 14] P (Parity)

This bit selects even or odd parity for data communications in which a parity bit is used.

0: Even parity

1: Odd parity

[bit 13] SBL (Stop Bit Length)

This bit sets the length of the stop bit that marks the frame end in asynchronous (start-stopsynchronized) communication.

0: 1 stop bit

1: 2 stop bits

[bit 12] CL (Character Length)

This bit sets the data length of one frame.

0: 7-bit data

1: 8-bit data

Note:

7-bit data handling is available only in asynchronous (start-stop synchronized)communications in normal mode (mode 0). In multi-processor mode (mode 1) and all CLK-synchronous communication (mode 2), 8-bit data should be used.

15 14 13 12 11 10 9 8Address: 000025H PEN P SBL CL A/D REC RXE TXE

(R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W)

Bit No.

Read/writeInitial value (0) (0) (0) (0) (0) (1) (0) (0)

Serial Control Register

SCR1

297


[bit 11] A/D (Address/Data)

This bit determines the data format of transmit frames in asynchronous (start-stopsynchronized) communication in multi-processor mode (mode 1).

0: Data frame

1: Address frame

[bit 10] REC (Receiver Error Clear)

This bit clears the error flags (PE, ORE, FRE) in the SSR1 register.

A write value of "1" is not valid, and the read value is "1" at all times.

[bit 9] RXE (Receiver Enable)

This bit controls UART1 receiver operations.

0: Receiver operation prohibited

1: Receiver operation enabled

Note:

If receiver operation is prohibited while reception is in progress (while data is present in thereceive shift register), the receiver will not stop operating until reception of the current frameis completed, and the data has been stored in the receive data buffer SIDR1 register.

[bit 8] TXE (Transmit Enable)

This bit controls UART1 transmit operation.

0: Transmit operation prohibited

1: Transmit operation enabled

Note:

If transmit operation is prohibited while transmission is in progress (while data is being outputfrom the transmit register), the transmitter will not stop operating until there is no more dataremaining in the transmit data buffer SODR1 register.

298


19.3.3 Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1)

These registers function as receive and transmit data buffer registers.

■ Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1)

The SIDR1 and SODR1 registers have the following bit configuration.

Figure 19.3-5 Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1)

The serial input data register 1 (SIDR1) functions as a data buffer register for receiving serialdata. The serial output data register 1 (SODR1) functions as a data buffer register fortransmitting serial data. When using 7-bit data length, the top bit (D7) contains invalid data. Besure the DTRE bit in the SSR1 register is set to "1" before writing to the SODR1 register.

Note:

Writing to these addresses refers to writing to the SODR1 register, and reading refers toreading from the SIDR1 register.

7 6 5 4 3 2 1 0Address: 000026H D7 D6 D5 D4 D3 D2 D1 D0


(X) (X) (X) (X) (X) (X) (X) (X)

Serial input data registerSerial output data register

Bit No.


SIDR1 (read)SODR1 (write)

299


19.3.4 Serial Status Register 1 (SSR1)

The serial status register (SSR1) is composed of flags that indicate the operating status of the UART1.

■ Serial Status Register 1 (SSR1)

The SSR1 register has the following bit configuration.

Figure 19.3-6 Serial Status Register 1 (SSR1)

[bit 15] PE (Parity Error)

This interrupt request flag is set when a parity error occurs during receive. Once set, thisflag is cleared by writing "0" to the REC bit (bit 10) in the SCR1 register.

When this bit is set, data in the SIDR1 register is invalid.

0: No parity error

1: Parity error occurred

[bit 14] ORE (Over Run Error)

This interrupt request flag is set when an overrun error occurs during receive. Once set, thisflag is cleared by writing ‘0" to the REC bit (bit 10) in the SCR1 register.


0: No overrun error

1: Overrun error occurred

[bit 13] FRE (Framing Error)

This interrupt request flag is set when a framing error occurs during receive. Once set, thisflag is cleared by writing ‘0" to the REC bit (bit 10) in the SCR1 register.


0: No framing error

1: Framing error occurred

[bit 12] RDRF (Receiver Data Register Full)

This interrupt request flag is set to indicate that data is present in the SIDR1 register.

This flag is set when receive data is loaded into the SIDR1 register, and is automaticallycleared when the data is read from the SIDR1 register.

0: No receive data

1: Receive data present

15 14 13 12 11 10 9 8

Address: 000027HPE ORE FRE RDRF TDRE – RIE TIE

(R) (R/W)(R/W)(-)(R)(R)(R)(R)

(0) (0) (0) (0) (0) (0)(1) (-)

SSR1

Serial Status RegisterBit No.


300


[bit 11] TDRE (Transmit Data Register Empty)

This interrupt request flag is set to indicate that outgoing data can be written to the SODR1register.

This flag is cleared when outgoing data is written to the SODR1 register. It is then resetwhen the written data starts loading into the transmit shifter to indicate that the next data canbe written to the SODR1 register.

0: Prohibits writing of send data

1: Enables writing of send data

[bit 9] RIE (Receiver Interrupt Enable)

This bit controls receiver interrupts.

0: Interrupt prohibited

1: Interrupt enabled

Note:

Receiver interrupt sources include PE, ORE and FRE errors, as well as normal receive asindicated by the RDRF flag.

[bit 8] TIE (Transmit Interrupt Enable)

This bit controls transmit interrupts.

0: Interrupt prohibited

1: Interrupt enabled

Note:

Transmit interrupt sources include transmission requests indicated by the TDRE flag.

301


19.3.5 UART1 Prescaler Control Register (U1CDCR)

The prescaler control register (U1CDCR) controls the machine clock frequency divider. The UART1 operating clock signal can be generated by dividing the machine clock signal pulse. The prescaler is designed to enable constant baud rates from a variety of machine clock speeds.The output from the prescaler is used by the I/O expanded serial interface.

■ UART1 Prescaler Control Register (U1CDCR)

The U1CDCR register has the following bit configuration.

[bit 7] MD (Machine clock divide MoDe select)

This bit enables the prescaler operation.

0: Prescaler stopped

1: Prescaler operating

[bit 3, 2, 1, 0] DIV3-0 (DIVide 3-0)

These bits determine the division of the machine clock frequency as shown in Table 19.3-3"Machine Clock Division Ratios".

Note:

After changing the division ratio, allow an interval of two cycles for the clock frequency tostabilize before starting communication.

Address: 000028HMD – – – DIV3 DIV2 DIV1 DIV0

(R/W) (-) (-) (-) (R/W) (R/W) (R/W) (R/W)(0) (-) (-) (-) (1) (1) (1) (1)

U1CDCR

Prescaler control register

Bit No.


15 14 13 12 11 10 9 8

Table 19.3-3 Machine Clock Division Ratios

DIV3 DIV2 DIV1 DIV0 Division ratio *1

1 1 1 0 Divide by 2

1 1 0 1 Divide by 3

1 1 0 0 Divide by 4

1 0 1 1 Divide by 5

1 0 1 0 Divide by 6

1 0 0 1 Divide by 7

1 0 0 0 Divide by 8

302

19.4 UART1 Operating Modes and Clock Selection


The UART1 has two types of operating mode, asynchronous mode and CLK-synchronous mode. Changes of mode are controlled by settings in the SMR1 register and SCR1 register.

■ UART1 Operating Modes

Table 19.4-1 "UART1 Operating Modes" shows the UART1 operating modes.

Note:

In asynchronous (start-stop synchronized) normal mode, stop bit length can be set foroutgoing transmission only. For receive, the setting is always 1-bit. The unit does not operatein modes other than those shown, and only these settings should be used.

Table 19.4-1 UART1 Operating Modes

Mode Parity bit Data length

Operating mode Stop bit length

0 Y/N 7 Asynchronous (start-stop synchronized) normal mode

1-bit or 2-bitY/N 8

1 N 8+1 Asynchronous (start-stop synchronized) multi-processor mode

2 N 8 CLK synchronous mode N

303


■ UART1 Clock Selection

❍ Dedicated baud rate generator

When the dedicated baud rate generator is selected, the baud rate settings listed in Table 19.4-2 "Baud Rates (Asynchronous communication)" and Table 19.4-3 "Baud Rates (CLK-synchronized communication)" are available. Also, prescaler settings are shown in Table 19.4-4"Prescaler Settings".

φ in the tables indicates the machine clock.

Table 19.4-2 Baud Rates (Asynchronous communication)

CS2 CS1 CS0 φ/div=2MHz φ/div=4MHz φ/div=8MHz Calculation formula

0 0 0 9615 19230 38460 (φ/div) / (8×13×2)

0 0 1 4808 9615 19230 (φ/div) / (8× 3×22)

0 1 0 2404 4808 9615 (φ/div) / (8×13×23)

0 1 1 1202 2404 4808 ((φ/div) / (8×13×24)

1 0 0 31250 62500 - (φ/div) / 26

Table 19.4-3 Baud Rates (CLK-synchronized communication)

CS2 CS1 CS0 φ/div=2MHz φ/div=4MHz φ/div=8MHz Calculation formula

0 0 0 1 MHz - - (φ/div) / 2

0 0 1 500 kHz 1 MHz - (φ/div) / 22

0 1 0 250 kHz 500 kHz 1 MHz (φ/div) / 23

0 1 1 125 kHz 250 kHz 500 kHz (φ/div) / 24

1 0 0 62.5 kHz 125 kHz 250 kHz (φ/div) / 25

304


❍ Internal timer

When bits CS2-0 are set to "110", the internal timer signal is selected, and the 16-bit (timer0)operates in reload mode. In this case, baud rates are determined as follows.

Asynchronous (start-stop synchronized): (φ / N) / (16 × 2 × (n + 1))

CLK synchronous: (φ / N) / ( 2 × (n + 1))

N: timer count clock source

n: timer reload value

Table 19.4-5 "Baud Rates and Reload Values" shows the relation between baud rates andreload values (decimal values) at a machine cycle speed of 7.3728MHz.

Table 19.4-4 Prescaler Settings

Recommended machine clock speed (φ)

div DIV3 DIV2 DIV1 DIV0 φ/div

4 MHz 4 1 1 0 0

1 MHz6 MHz 6 1 0 1 0

8 MHz 8 1 0 0 0

6 MHz 3 1 1 0 1

2 MHz

8 MHz 4 1 1 0 0

10 MHz 5 1 0 1 1

12 MHz 6 1 0 1 0

14 MHz 7 1 0 0 1

16 MHz 8 1 0 0 0

8 MHz 2 1 1 1 0

4 MHz12 MHz 3 1 1 0 1

16 MHz 4 1 1 0 0

16 MHz 2 1 1 1 0 8 MHz

305


When selecting the internal timer (16-bit timer0) as the baud rate clock source, note that the 16-bit timer0 output signal TOUT0 is already connected to the MB90435 controller internally.Therefore, it is not necessary to make an external connection from the 16-bit timer0 externaloutput pins TOUT0 to the UART1 external clock input pin SCK1. Also, this means that unlessused in some other fashion, the timer pins are available for use as I/O port pins.

❍ External clock

When bits CS2-0 are set to "111" the external clock source is selected and baud rates aredetermined by the following formula, in which f represents the external clock frequency.

Asynchronous (start-stop synchronized) mode: f/16

CLK synchronous: f

Note that f has a maximum value of 2 MHz.

Table 19.4-5 Baud Rates and Reload Values

Baud rate

Reload value

N=21

(machine cycle division by 2)N=23

(machine cycle division by 8)

38400 2 −

19200 5 −

9600 11 2

4800 23 5

2400 47 11

1200 95 23

600 191 47

300 383 95

306


19.4.1 Asynchronous (Start-Stop Synchronized) Mode

The UART1 handles only data in NRZ (non-return to zero) format.

■ Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format

Figure 19.4-1 "Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format (Mode 0,1)" shows ttransfer data format.

Figure 19.4-1 Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format (Mode 0, 1)

As shown in Figure 19.4-1 "Asynchronous (Start-Stop Synchronized) Mode Data TransferFormat (Mode 0, 1)", transfer data must begin with a start bit ("L" level data value), followed byLSB-first data of the designated bit-length, and ending with a stop bit ("H" level data value).When an external clock signal is selected, the clock should be input at all times.

In normal mode (mode 0), data length may be set to 7 bits or 8 bits, however in multi-processormode (mode 1) the data length must be 8 bits. Also, no parity bit may be attached in multi-processor mode. Instead, an A/D bit must be attached.

■ Asynchronous (Start-Stop Synchronized) Mode Receive Operation

Whenever the RXE bit (bit 9) in the SCR1 register is set to "1", UART1 is receiving.

Appearance of a start bit on the receive line allows one frame of data to be received in the dataformat determined by the SCR1 register. After the frame is received, error flags are set if thecorresponding errors have occurred, and then the RDRF flag (SST register bit 12) is set. If theRIE bit (bit 9) in the SSR1 register is set to "1", a receive interrupt is sent to the CPU. The CPUchecks each flag in the SSR1 register and reads the SIDR1 register to see if the data has beenreceived correctly. If any errors have occurred, take the required action.

The RDRF flag is cleared when the SIDR1 register is read.

■ Asynchronous (Start-Stop Synchronized) Mode Transmit Operation

Whenever the TDRE flag (bit 11) in the SSR1 register is set to "1" the UART1 is writing outgoingdata to the SODR1 register. If the TXE bit (bit 8) is set to "1" transmit operation is in progress.

As soon as data in the SODR1 register starts to be transferred to the transmit shift register fortransmission, the TDRE flag is reset. This enables the next unit of outgoing data to be placed inthe SODR1 register. At this time if the TIE bit (bit 8) in the SSR1 register is set to "1" atransmission interrupt is sent to the CPU, causing outgoing data to be placed into the SODR1register.

The TDRE flag is momentarily cleared each time data is placed into the SODR1 register.

0 1 0 1 1 0 0 1 0 1 1

Start LSB MSB Stop........(Mode 0)A/D Stop........(Mode 1)

SIN1,SOT1

Transferred data `01001101B'

307


19.4.2 CLK Synchronous Mode

The UART1 handles only data in NRZ (non-return to zero) format.

■ CLK Synchronous Mode Data Transfer Format

Figure 19.4-2 "CLK Synchronous Mode Data Transfer Format (Mode 2)" shows the relationbetween the transmit and receive clock and data in CLK synchronous mode.

Figure 19.4-2 CLK Synchronous Mode Data Transfer Format (Mode 2)

When an internal clock signal source (dedicated baud rate generator or internal timer) isselected, a receive clock signal is automatically generated each time data is transmitted.

When an external clock source is selected it is necessary to provide an accurate 1-byte clocksignal after data is confirmed present in the transmit data buffer register SODR1 (indicated bythe TDRE flag = "0"). Note also that the signal must return to mark level before and aftertransmit operation.

Data length is 8-bit only, and no parity bit may be attached. Also, there is no start/stop bit so thatno error detection is enabled except for overrun errors.

■ Control Register Settings for CLK Synchronous Mode

When using CLK synchronous mode, the following settings are made to each of the controlregisters.

❍ SMR1 register

MD1, MD0: 10

CS2, CS1, CS0: Indicate clock input

SCKE: 1 for dedicated baud rate generator or internal timer, 0 for external clock

SOE: 1 to send, 0 to receive only

1 0 1 1 0 0 1 0

LSB MSB...................(Mode 2)

Transferred data `01001101B'

Mark

SODRwrite

SCLK

RXE,TXE

SIN1,SOT1

308


❍ SCR1 register

PEN: 0

P, SBL, A/D: These bits have no significance

CL: 1

REC: 0 (to initialize)

RXE, TXE: At least one must be "1"

❍ SSR1 Register

RIE: 1 if interrupts are used, 0 if interrupts are not used

TIE: 0

■ Start of Communication in CLK Synchronous Mode

Communication starts by writing to the SODR1 register. Even if data is to be only received (notsent), it is first necessary to write dummy data to the SODR1 register.

■ End of Communication in CLK Synchronous Mode

The end of communication can be verified by the change of the RDRF flag in the SSR1 registerto "1". To determine whether the communication was performed normally, read the ORE bit inthe SSR1 register.

309


19.5 UART1 Flags and Interrupt Sources

The UART1 has five flags, PE, ORE, FRE, RDRF and TDRE, and two interrupt sources, one for transmit and one for receive.

■ UART1 Flags

The five flags are the PE, ORE, FRE, RDRF and TDRE flags. The first three are set whentransmit errors occur, the PE flag for a parity error, the ORE flag for an overrun error, and theFRE flag for a framing error, and are released by writing "0" to the REC bit in the SCR1 register.The RDRF flag is set when receive data is loaded into the SIDR1 register, and cleared when thedata is read out of the SIDR1 register. Note however that there is no parity detect function inmode 1, and no parity detect function or framing error detect function in mode 2. The TDRE flagis set when the SODR1 register is empty and ready for data write access, and is cleared whendata is written to the SODR1 register.

■ UART1 Interrupt Sources

The UART1 has two interrupt sources, one for receive and one for transmit. During receive,interrupt requests are initiated by setting the PE, ORE, FRE or RDRF flags. During transmit,interrupt requests are initiated by setting the TDRE flag.

Interrupt flag set timing in each operating mode is described in section 19.6 "UART1 Interruptsand Flag Set Timing".

310

19.6 UART1 Interrupts and Flag Set Timing


This section describes the timing of interrupts and flag setting in each UART1 operating mode.

■ UART1 Interrupts and Flag Set Timing

❍ Mode 0 Receive

The PE, ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPUfollowing the end of a receive transfer, when the final stop bit is detected. If any one of the PE,ORE or FRE flags is active, the data in the SIDR1 register will be invalid.

Figure 19.6-1 "PE, ORE, FRE, RDRF Flag Set Timing (Mode 0)" shows the timing of the PE,ORE, FRE, and RDRF flags (mode 0).

Figure 19.6-1 PE, ORE, FRE, RDRF Flag Set Timing (Mode 0)

❍ Mode 1 Receive

The ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU afterthe end of a receive transfer, when the final stop bit is detected. Also, if the receive data lengthis 8 bits, the 9th bit indicating address/data will be invalid. If either the ORE or FRE flags isactive, the data in the SIDR1 register will be invalid.

Figure 19.6-2 "ORE, FRE, RDRF Flag Set Timing (Mode 1)" shows the timing of the ORE, FRE,and RDRF flags (mode 1).

Figure 19.6-2 ORE, FRE, RDRF Flag Set Timing (Mode 1)

D6 D7 StopData

Receiving interrupt

PE,ORE,FRE

RDRF

D7 Address/data StopData

Receiving interrupt

ORE,FRE

RDRF

311


❍ Mode 2 Receive

The ORE and RDRF flags are set and the interrupt request signal is sent to the CPU after theend of a receive transfer, when the final data (D7) is detected. If the ORE flag is active, the datain the SIDR1 register will be invalid.

Figure 19.6-3 "ORE, RDRF Flag Set Timing (Mode 2)" shows the timing of the ORE and RDRFflags (mode 2).

Figure 19.6-3 ORE, RDRF Flag Set Timing (Mode 2)

❍ Mode 0, Mode 1, and Mode 2 Transmit

The TDRE flag is cleared when data is written to the SODR1 register. The TDRE flag is set (andan interrupt request sent to the CPU) as soon as the data in the SODR1 register is transferredto the internal shift register, to ready the SODR1 register for the next data write cycle. During atransmit operation, if "0" is written to the TXE bit in the SCR1 register (including the RXE bit inmode 2), the TDRE bit in the SSR1 register will be set to "1" and the UART1 transmit operationwill be disabled as soon as the transmit shifter stops. The data written to the SODR1 registerwill be sent, however, between the writing of "0" to the TXE bit in the SCR1 register (includingthe RXE bit in mode 2), and the end of the transmit operation. Figure 19.6-4 "TDRE Flag SetTiming (Mode 0, 1) " shows the timing of the TDRE flag (mode 0, 1), and Figure 19.6-5 "TDREFlag Set Timing (Mode 2)" shows the timing of the TDRE flag (mode 2).

Figure 19.6-4 TDRE Flag Set Timing (Mode 0, 1)

D5 D6 D7Data

Receiving interrupt

ORE

RDRF

SODR write

SOT1 interrupt

SOT1 output

Interrupt request to CPU

TDRE

ST: Start bit D0 to D7: Data bits SP: Stop bit A/D: Address/data multiplexer

ST STSPSPD0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3A/D

312


Figure 19.6-5 TDRE Flag Set Timing (Mode 2)

SODR write

SOT1 interrupt

SOT1 output

Interrupt request to CPU

TDRE

DO to D7: Data bits

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

313


19.7 Negative Clock Operation

The MB90435 series supports the negative clock operation of UART1. In this operation, an inverter can invert the shift clock signal. The definition for the shift clock signal in an active section in UART1 is inverted from the logic L level to the logic H level, from the negative edge to the positive edge, or vice versa. This is the same for serial clock input and output. Thus, the edge selector register is prepared.

■ Negative Clock Operation

Figure 19.7-1 Serial Edge Select Register (SES1)

7 6 5 4 3 2 1 0

NEG SES1

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)Initial value (-) (-) (-) (-) (-) (-) (-) (0)

Address:000029H

Serial edge selected after operation

Read/Write

Bit No.

Table 19.7-1 Setting the NEG Bit

NEG Operation

0 Normal operation [default]

1 The shift clock signal is inverted

314

19.8 UART1 Sample Applications and Precautionary Information

19.8 UART1 Sample Applications and Precautionary Information

This section presents a sample system configuration and communication flow chart as a sample application of the UART1 used in Mode 1.

■ UART1 Sample Application (System Configuration in Mode 1)

Mode 1 is used when one host CPU is connected to multiple slave CPU's (see Figure 19.8-1"Sample System Configuration in Mode 1"). This UART1 resource supports only communicationinterface with the host-side unit.

Figure 19.8-1 Sample System Configuration in Mode 1

■ UART1 Communication Flow Chart

Transmission begins with the transfer of address data by the host CPU. Address data is datahandled while the A/D bit in the SCR1 register is set to "1" and is used to select the slave CPUthat is to receive the transmission, and to enable communication with the host CPU. In normaldata, the A/D bit in the SCR1 register is set to "0". Figure 19.8-2 "Communications FlowchartUsing Mode 1" illustrates the flow of this process.

No parity check function is available in mode 2, so that the PEN bit in the SCR1 register shouldbe set to "0".

Host CPU

Slave CPU #0

S0

S1

S0 S1

Slave CPU #1

S0 S1

315


Figure 19.8-2 Communications Flowchart Using Mode 1

■ Extended Intelligent I/O Service (EI2OS)

For information about EI2OS, see section 3.6 "Extended Intelligent I/O Service (EI2OS)".

■ Precautions for UART1 Use

Always make communications mode settings when the UART1 is not operating. Transmit andreceive data values are not assured during mode setting.

(Host CPU)

START

Set transfer mode to 1

Set D0 to D7 to data selecting slave

Set A/D to `0'

Enable the receiving operation

Communicate with the slave CPU

Disable receiving operation

CPU, set A/D to `1' and transfer 1 byte

Communicationended?

Communicate withother slave CPU?

END

Yes

Yes

No

No

316

CHAPTER 20 SERIAL I/O

This chapter explains the functions and operations of the serial I/O.

20.1 "Outline of Serial I/O"

20.2 "Serial I/O Registers"

20.3 "Serial I/O Operation"

20.4 "Negative Clock Operation"

317


20.1 Outline of Serial I/O

The serial I/O interface operates in two modes:• Internal shift clock mode: Data is transferred in synchronization with the internal

clock.• External shift clock mode: Data is transferred in synchronization with the clock

supplied via the external pin (SCK2). By manipulating the general-purpose port sharing the external pin (SCK2), data can also be transferred by a CPU instruction in this mode.

■ Serial I/O Block Diagram

This block is a serial I/O interface that allows data transfer using clock synchronization. Theinterface consists of a single eight-bit channel. Data can be transferred from the LSB or MSB.

Figure 20.1-1 Extended Serial I/O Interface Block Diagram

SIN2

SOT2

SCK2

2 1 0

S M D 2 S M D 1 S M D 0 S I E S I R B U S Y S T O P S T R T M O D E B D S S O E S C O E

Internal data bus

(MSB first) D7 to D0 D7 to D0 (LSB first)

Transfer direction selection

SDR (Serial data register)

Read

Write

Control c i rcui t

Internal clock(Prescaler)

Interrupt

Internal data bus

request

Shi f t c lock counter

318

20.2 Serial I/O Registers


The serial I/O has the following two registers:• Serial mode control status register (SMCS)• Serial data register (SDR)

■ Serial I/O Resisters

Figure 20.2-1 Serial I/O Registers

Address : 00002DH SIR BUSY STOP STRTSIE

15 14 13 12 11 10 9 8

SMD0SMD2 SMD1 SMCS

Address : 00002EHD3 D2 D1 D0D4

7 6 5 4 3 2 1 0

D5D7 D6 SDR

Serial Mode Control Status Register

SCDCR

HAddress : 00002C MODE BDS SOE SCOE

7 6 5 4 3 2 1 0

SMCS

15

MI DIV3 DIV2 DIV1 DIV0

14 13 12 11 10 9 8

Address : 00002BH

Serial I/O prescaler

(R/W) (R/W)(R/W) (R/W) (R/W) (R/W) (R/W)(R)(0) (0) (0) (0) (0) (0) (0)(1)

(-) (-)(-) (-) (R/W) (R/W) (R/W)(R/W)(-) (-) (-) (-) (0) (0) (0)(0)

Serial data register

(R/W) (R/W)(R/W) (R/W) (R/W) (R/W) (R/W)(R/W)(X) (X) (X) (X) (X) (X) (X)(X)

(R/W) (R/W)(R/W) (R/W) (R/W) (R/W) (R/W)(R/W)(0) (-) (-) (-) (1) (1) (1)(1)

Bit No.

Read/write

Initial value

Read/write

Initial value

Bit No.

Bit No.

Read/write

Initial value

Read/write

Initial value

Bit No.

319


20.2.1 Serial Mode Control Status Register (SMCS)

The serial mode control status register (SMCS) controls the serial I/O transfer mode.

■ Serial Mode Control Status Register (SMCS)

Figure 20.2-2 Serial Mode Control Status Register (SMCS)

[bit 3] Serial mode selection bit (MODE)

The serial mode selection bit is used to select the conditions to start the transfer operationfrom the stop state. This bit must not be updated during operation.

This bit is initialized to a "0" upon a reset, and can be read or written to. To activate theintelligent I/O service, ensure that "1" is written to this bit.

Address: 00002DH

(R/W)

SIR BUSY STOP STRTSIE

15 14 13 12 11 10 9 8

SMD0SMD2 SMD1

*1 *2

MODE BDS SOE SCOE

7 6 5 4 3 2 1 0

SMCSAddress: 00002CH

*1: Only '0' can be written.*2: Only '1' can be written. '0' is always read.

(R/W) (R/W) (R/W) (R/W) (R/W)(R/W)(R)(0) (0) (0) (0) (0) (0) (1) (0)

(-) (-) (-) (-) (R/W) (R/W) (R/W) (R/W)(-) (-) (-) (-) (0) (0) (0) (0)

Bit No.


Read/write

Initial value

Bit No.

Serial Mode Control Status Register

Table 20.2-1 Setting the Serial Mode Selection Bit

MODE Operation

0 Transfer starts when STRT=1. [Default]

1 Transfer starts when the serial data register is read or written to.

320


[bit 2] Bit direction select bit (BDS)

When serial data is input or output, this bit determines from which bit data is to betransferred first, the least significant bit (LSB first) or the most significant bit (MSB first), asshown in Table 20.2-2 "Setting the Transfer Direction Selection Bit".

Note:

Specify the bit ordering before any data is written to SDR.

[bit 1] Serial output enable bit (SOE: Serial out enable)

This bit controls the output from the serial I/O output external pins (SOT2) as shown in Table20.2-3 "Setting the Serial Output Enable Bit".


[bit 0] Shift clock output enable bit (SCOE: SCK2 output enable)

This bit controls the output from the shift clock I/O output external pins (SCK2) as shown inTable 20.2-4 "Setting the Shift Clock Output Enable Bit".

Ensure that "0" is written to this bit when data is transferred for each instruction in externalshift clock mode.


Table 20.2-2 Setting the Transfer Direction Selection Bit

BDS Operation

0 LSB first [default]

1 MSB first

Table 20.2-3 Setting the Serial Output Enable Bit

SOE Operation

0 General-purpose port pin [default]

1 Serial data output

Table 20.2-4 Setting the Shift Clock Output Enable Bit

SCOE Operation

0 General-purpose port pin, transfer for each instruction [default]

1 Shift clock output pin

321


[Bits 15, 14, and 13] Shift clock selection bits (SMD2, SMD1, SMD0: Serial shift clockmode)

These bits are used to select the serial shift clock mode, as shown in Table 20.2-5 "Settingthe Serial Shift Clock Mode".

Setting of the Serial I/O prescaler (SCDCR)

* For details, see 20.2.3 "Serial I/O Prescaler (SCDCR)".

These bits are initialized to "000" upon a reset. These bits must not be updated during datatransfer.

Five types of internal shift clock and an external shift clock are available. Do not set 110 or111 in SMD2, SMD1, and SMD0 as these values are reserved.

When external shift clock mode is selected, changing the output levels of the general-purpose I/O devices sharing the shift clock input will also enable bit shifting.

Table 20.2-5 Setting the Serial Shift Clock Mode

SMD2 SMD1 SMD0 φ/div=4 MHz φ/div=2 MHz φ/div=1 MHz

0 0 0 2 MHz 1 MHz 500 kHz

0 0 1 1 MHz 500 kHz 250 kHz

0 1 0 250 kHz 125 kHz 62.5 kHz

0 1 1 125 kHz 62.5 kHz 31.25 kHz

1 0 0 62.5 kHz 31.25 kHz 15.625 kHz

1 0 1 External shift clock mode

1 1 0 Reserved

1 1 1 Reserved

div M1 DIV3 DIV2 DIV1 DIV0Recommended machine cycle

3 1 1 1 0 1 6 MHz

4 1 1 1 0 0 8 MHz

5 1 1 0 1 1 10 MHz

6 1 1 0 1 0 12 MHz

7 1 1 0 0 1 14 MHz

8 1 1 0 0 0 16 MHz

322


[bit 12] Serial I/O interrupt enable bit (SIE: Serial I/O interrupt enable)

This bit controls the serial I/O interrupt request as shown in Table 20.2-6 "Setting theInterrupt Request Enable Bit".


[bit 11] Serial I/O interrupt request bit (SIR: Serial I/O interrupt request)

When serial data transfer is completed, "1" is set to this bit. If this bit is set while interruptsare enabled (SIE=1), an interrupt request is issued to the CPU. The clear condition varieswith the MODE bit.

When "0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is writtento the MODE bit, the SIR bit is cleared by reading or writing to SDR. When the system isreset or "1" is written to the STOP bit, the SIR bit is cleared regardless of the MODE bitvalue.

Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a read-modify-write instruction.

[bit 10] Transfer status bit (BUSY)

The transfer status bit indicates whether serial transfer is being executed.

Table 20.2-6 Setting the Interrupt Request Enable Bit

SEE Operation

0 Serial I/O interrupt disabled [initial value]

1 Serial I/O interrupt enabled

323


This bit is initialized to "0" upon a reset. This is a read-only bit.

[bit 9] Stop bit (STOP)

The stop bit forcibly terminates serial transfer. When "1" is written to this bit, the transfer isstopped.


[bit 8] Start bit (STRT: Start)

The start bit activates serial transfer. Writing "1" to this bit starts the data transfer when theMODE bit is set to 0. When the MODE bit is set to 1 and the STRT bit is set to 1, writing thedata into serial data register starts the transfer.

Writing "1" is ignored while the system is performing serial transfer or standing by for a serialshift register read or write. Writing "0" has no effect. "0" is always read.

Table 20.2-7 Setting the Transfer Status Bit

BUSY Operating

0 Stopped, or standing by for serial data register R/W [default]

1 Serial transfer

Table 20.2-8 Setting the Stop Bit

STOP Operating

0 Normal operation

1 Transfer stop by STOP=1 [initial value]

324


20.2.2 Serial Shift Data Register (SDR)

This serial data register stores the serial I/O transfer data. During transfer, the SDR must not be read or written to.

■ Serial Shift Data Register (SDR)

Figure 20.2-3 Serial Shift Data Register (SDR)

Address : 00002EH D3 D2 D1 D0D4

7 6 5 4 3 2 1 0

D5D7 D6 SDR


(X) (X) (X) (X) (X) (X) (X) (X)

Serial Data Register

Read/write

Initial value

Bit No.

325


20.2.3 Serial I/O Prescaler (SCDCR)

The Serial I/O Prescaler provides the shift clock for the Serial I/O.The operation clock for the Serial I/O is obtained by dividing the machine clock. The Serial I/O is designed so that a constant baud rate can be obtained for a variety of machine clocks by the user of the communication prescaler. The SCDCR register controls the machine clock division.

■ Serial I/O Prescaler (SCDCR)

Figure 20.2-4 Serial I/O Prescaler (SCDCR)

[bit 15] MD (Machine clock divide mode select):

This bit is used to control the operation of the communication prescaler.

0: The Serial I/O Prescaler is disabled.

1: The Serial I/O Prescaler is enabled.

[bits 11, 10, 9, and 8] DIV3 to DIV0 (Divide 3 to 0):

These bits are used to determine the machine clock division ratio.

Note:

When the division ratio is changed, allow two cycles for the clock to stabilize before startingcommunication.

15 14 13 12 11 10 9 8

DIV3 DIV2 DIV1 DIV0 MIAddress: 00002BH

(R/W) (R/W) (R/W) (R/W) (R/W)(0) (1) (1) (1) (1)

SCDCR

Serial I/O Prescaler

Read/write

Initial value

Bit No.

Table 20.2-9 Machine Clock Division Ratio

DIV3 to 0 Division ratio

1101B 3

1100B 4

1011B 5

1010B 6

1001B 7

1000B 8

326

20.3 Serial I/O Operation


The serial I/O consists of the serial mode control status register (SMCS) and shift register (SDR), and is used for input and output of 8-bit serial data.

■ Serial I/O Operation

The bits in the shift register are serially output via the serial output pin (SOT2 pin) at the fallingedge of the serial shift clock (external clock or internal clock). The bits are serially input to theshift register (SDR) via the serial input pin (SIN2 pin) at the rising edge of the serial shift clock.The shift direction (transfer from MSB or LSB) is specified by the direction specification bit(BDS) of the serial mode control status register (SMCS).

At the end of serial data transfer, this block is stopped or stands by for a read or write of thedata register according to the MODE bit of the serial mode control status register (SMCS). Tostart transfer from the stop or standby state, follow the procedure below.

❍ To resume operation from the stop state, write '0' to the STOP bit and '1' to the STRT bit. (The STOP and STRT bits can be set simultaneously.)

❍ To resume operation from the serial shift data register R/W standby state, read or write to the data register.

327


20.3.1 Shift Clock

There are two modes of shift clock: internal or external shift clock. These two modes are selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer is stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit.

■ Internal Shift Clock Mode

In internal clock mode, the internal clock determines operation, and shift clocks with a duty ratioof 50% can be output from the SCK2 pin. One bit of data is transferred for each clock. Thetransfer speed (baud rate) is shown below:

A is a frequency-division ratio and is 21, 22, 24, 25, or 26 indicated by the SMCS SMD bits.

■ External Shift Clock Mode

In external shift clock mode, the data transfer is based on the external clock supplied via theSCK2 pin. Data is transferred at one bit per clock.

The transfer speed can be between DC and 1/(8 machine cycles). For example, the transferspeed can be up to 2 MHz when 1 machine cycle is equal to 62.5 ns.

A data bit can also be transferred by software, which is enabled as described below.

Select external shift clock mode, and write "0" to the SCOE bit of SMCS. Then, write "1" to thedirection register for the port sharing the SCK2 pin, and place the port in output mode. Then,when "1" and "0" are written to the data register (PDR) of the port, the port value output via theSCK2 pin is fetched as the external clock and transfer starts. Ensure that the shift clock startsfrom "H".

Note:

The SMCS or SDR must not be written to during serial I/O operation.

Baud rate = A

φ / div

Table 20.3-1 Formulas for Calculating Baud Rate in Internal Shift Clock Mode

SMD2 SMD1 SMD0 φ/div=4MHz φ/div=2MHz φ/div=1MHz Formula

0 0 0 2 MHz 1 MHz 500 kHz (φ/div)/21

0 0 1 1 MHz 500 kHz 250 kHz (φ/div)/22

0 1 0 250 kHz 125 kHz 62.5 Hz (φ/div)/24

0 1 1 125 kHz 62.5 kHz 31.25 kHz (φ/div)/25

1 0 0 62.5 kHz 31.2 kHz 15.625 kHz (φ/div)/26

See Table 19.4-4 "Prescaler settings", for the div values.

328


20.3.2 Serial I/O Operation

There are four serial I/O operation statuses:• STOP• Halt• SDR R/W standby• Transfer

■ Serial I/O Operation

❍ STOP

The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. Theshift counter is initialized, and "0" is written to SIR.

To resume operation from the STOP state, write "0" to STOP and "1" to STRT. (These two bitscan be written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot bestarted by writing "1" to STRT while "1" is written to STOP.

❍ Halt

When transfer is completed while the MODE bit is "0", "0" is set to BUSY and "1" is set to SIR ofthe SMCS, the counter is initialized, and the system stops. To resume operation from the stopstate, write "1" to STRT.

❍ Serial data register R/W standby

When transfer is completed while the MODE bit is "1", "0" is set to BUSY and "1" is set to SIR ofthe SMCS, and the system enters the serial data register R/W standby state. If the interruptenable flag is set, an interrupt signal is output from this block.

To resume operation from R/W standby state, read or write to the serial data register. This setsthe BUSY bit to "1" and starts data transfer.

❍ Transfer

"1" is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, thehalt state or R/W standby state comes next.

Figure 20.3-1 "Extended I/O Serial Interface Operation Transitions" is diagrams of the operationtransitions.

329


Figure 20.3-1 Extended I/O Serial Interface Operation Transitions

Figure 20.3-2 Serial Data Register Read/write

1. If "1" is written to MODE, transfer ends according to the shift clock counter. The read/writestandby state starts when "1" is written to SIR. If "1" is written to the SIE bit, an interruptsignal is generated. No interrupt signal is generated when SIE is inactive or transfer hasbeen terminated by writing "1" to STOP.

2. Reading or writing to the serial data register clears the interrupt request and starts serialtransfer.

STOP=0 & STRT=0

STOP=1STRT=0, BUSY=0

STRT=1, BUSY=0MODE=1

STOP=1 STOP=0&

STRT=1

STOP=1

MODE=1 & END & STOP=0STRT=1, BUSY=1

STOP=0&STRT=1

MODE=0&STOP=0&END

STRT=0, BUSY=0MODE=0

End of transfer

Transfer

Reset

Serial data register R/W standby

SDR R/W & MODE=1

STOP

CPUSOT2SIN2

Ser

ial d

ata

Data busReadWrite

Interrupt output

Extended I/O Interrupt inputInterrupt controllerserial interface

Data bus

ReadWrite

Data bus

330


20.3.3 Shift Operation Start/Stop Timing

To start the shift operation, set the STOP bit to "0" and the STRT bit to "1" in SMCS.The system may stop the shift operation at the end of transfer or when "1" is set in the STOP bit.• Stop by STOP=1 -> The system stops with SIR=0 regardless of the MODE bit.• Stop by end of transfer -> The system stops with SIR=1 regardless of the MODE

bit.Regardless of the MODE bit, the BUSY bit becomes "1" during serial transfer and becomes "0" during stop or R/W standby state. To check the transfer status, read this bit.

■ Shift Operation Start/Stop Timing

❍ Internal shift clock mode (LSB first)

Figure 20.3-3 Shift Operation Start/Stop Timing (Internal Clock)

❍ External shift clock mode (LSB first)

Figure 20.3-4 Shift Operation Start/Stop Timing (External Clock)

SCK2

STRT

BUSY

SOT2 DO0

(Transfer start) (Transfer end)

If MODE=0

DO7 (Data maintained)

'1' output

SCK2

STRT

BUSY

SOT2 DO0

(Transfer start) (Transfer end)

If MODE=0


331


❍ External shift clock mode with instruction shift (LSB first)

Figure 20.3-5 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift)

Note:

For an instruction shift, "H" is output when "1" is written to the bit corresponding to SCK2 ofPDR, and "L" is output when "0" is written. (When SCOE=0 in external shift clock mode)

❍ Stop by STOP=1 (LSB first, internal clock)

Figure 20.3-6 Stop Timing when "1" is Written to the STOP Bit

Note:

DO7 to DO0 indicate output data.

During serial data transfer, data is output from the serial output pin (SOT2) at the falling edge ofthe shift clock, and input from the serial input pin (SIN2) at the rising edge.

DO6

SCK2

STRT

BUSY

SOT2

SCK2='0' in PDRSCK2='1' in PDR (Transfer end)

SCK2='0' in PDR

If MODE=0


STRT

BUSY

SOT2

STOP

DO3 DO4

SCK2(Transfer start) (Transfer stop)

'1' output

If MODE=0


332


Figure 20.3-7 Serial Data I/O Shift Timing 1

Figure 20.3-8 Serial Data I/O Shift Timing 2

SIN2 Input

SOT2 OutputD10 D11 D12 D13 D14 D15 D16 D17

DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7

SCK2

SIN2

SOT2

❍ LSB first (When the BDS bit is '0')

D17 D16 D15 D14 D13 D12 D11 D10

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

SCK2

SIN2

SOT2

SIN2 Input

SOT2 Output

❍ MSB first (When the BDS bit is '1')

333


20.3.4 Interrupt Function of the Serial I/O Interface

This block can issue an interrupt request to the CPU. At the end of data transfer, the SIR bit is set as an interrupt flag. When "1" is written to the interrupt enable bit (SIE bit) of SMCS, an interrupt request is issued to the CPU.

■ Interrupt Function of the Serial I/O Interface

Figure 20.3-9 Interrupt Signal Output Timing of the Extended Serial I/O Interface

SCK2

BUSY

SIR

SOT2

SIE=1

DO6

(Transfer end) * When MODE=1

SDR RD/WR

DO7 (Data is maintained.)

334



The MB90435 series supports the negative clock operation of the Serial I/O. In this operation, the shift clock signal is simply negated by a inverter. Therefore the definition of the shift clock signal in the preceding sections of the Serial I/O is inverted from the logic low level to logic high level, from the negative edge to the positive edge and vise-versa. This is the same for both the serial clock input and output. The edge select register is installed for this purpose.

■ Negative Clock Operation

Figure 20.4-1 Serial Edge Select Register (SES2)

Address : 00002FH NEG

7 6 5 4 3 2 1 0

SES2


(-) (-) (-) (-) (-) (-) (-) (0)

Read/write

Initial value

Bit No.

Table 20.4-1 Setting the NEG Bit

NEG Operation

0 Normal operation [default]

1 The shift clock signal is inverted

335


336

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION

This chapter explains the address match detection function and operation.

21.1 "Overview of the Address Match Detection Function"

21.2 "Registers of the Address Match Detection Function"

21.3 "Operation of the Address Match Detection Function"

21.4 "Example of the Address Match Detection Function"

337


21.1 Overview of the Address Match Detection Function

When an address matches the value set in the address detection register, the instruction code to be read by the CPU is replaced with the INT9 instruction code (01H). Consequently, the CPU executes the INT9 instruction when executing a specified instruction. The address match detection function can be achieved using the INT9 interrupt routine for processing.There are two address detection registers, each with an interrupt permission bit. When an address matches the value set in the address detection register and the interrupt permission bit is 1, the instruction code to be read by the CPU is replaced with the INT9 instruction code.

■ Block Diagram of the Address Match Detection Function

Figure 21.1-1 Block Diagram of the Address Match Detection Function

Address latch

Address detection register C

ompa

rison

INT9 instruction

Permission bitF2MC-16LX CPU core

F2MC-16LX bus

338

21.2 Registers of the Address Match Detection Function

21.2 Registers of the Address Match Detection Function

The two types of registers for the address match detection function are as follows:• Program address detection registers (PADR0 and PADR1)• Program address detection control status register (PACSR)

■ Program Address Detection Registers (PADR0 and PADR1)

The program address detection registers 0 and 1 (PADR0 and PADR1) compare the addresswith the value written in each register. If they match when the interrupt permission bitcorresponding to ADCSR is 1, the CPU is requested to issue the INT9 instruction.

When the corresponding interrupt bit is 0, nothing occurs.

Figure 21.2-1 Program Address Detection Registers (PADR0 and PADR1)

Table 21.2-1 "Correspondence between PADR0 and PADR1 Registers and PACSR" lists thecorrespondence between the program address detection registers (PADR0 and PADR1) andPACSR.

■ Program Address Detection Control Status Register (PACSR)

The program address detection control status register (PACSR) controls the operation of theaddress detection function.

Figure 21.2-2 Program Address Detection Control Status Register (PACSR)

[Bits 7 to 4] Reserved bits

Bits 7 to 4 are reserved. Set these bits to 0 before setting PACSR.

[Bit 3] AD1E (Address detect register 1 enable)

The AD1E bit is the operation permission bit of ASIE ADR1.

When this bit is 1, the address is compared with the PADR1 register. If they match, the INT9instruction is issued.

byte byte byte

PADR0 1FF2H/1FF1H/1FF0H R/W

PADR1 1FF5H/1FF4H/1FF3H R/W

Program address detection registers Access Initial value

Not defined

Not defined

Table 21.2-1 Correspondence between PADR0 and PADR1 Registers and PACSR

Address detection register Interrupt permission bit

PADR0 AD0E

PADR1 AD1E

7 6 5 4 3 2 1 0

Address: 009EH AD1E AD0E

(-) (-) (-) (-) (R/W) (R/W) (R/W) (R/W)(-) (-) (-) (-) (0) (0) (0) (0)

Program address detection control status register

Reserved Reserved Reserved Reserved Reserved Reserved

Bit No.

PACSR


339



Bit 2 is reserved. Set this bit to 0 before setting PACSR.

[Bit 1] AD0E (Address Detect register 0 Enable)

The AD0E bit is the operation permission bit of ADR0.

When this bit is 1, the address is compared with the PADR0 register. If they match, the INT9instruction is issued.


Bit 0 is reserved. Set this bit to 0 before setting PACSR.

340

21.3 Operation of the Address Match Detection Function

21.3 Operation of the Address Match Detection Function

If the program counter specifies the same address as the address match detection register, the INT9 instruction is executed. The address match detection function can be achieved by processing the INT9 instruction routine.

■ Operation of the Address Match Detection Function

There are two address detection registers with a compare enable bit. When the value set in theaddress detection register and the value of the program counter match and the compare enablebit is set to 1, the CPU executes the INT9 instruction.

Note:

If the value of the address detection register and the value of the program counter match, thecontents of internal data bus is changed to 01H. Consequently, the INT9 instruction isexecuted. Before changing the contents of the address detection register, always set thecompare enable bit to 0. While the compare enable bit is set to 1, changing the contents ofthe address detection register may result in a malfunction.

341


21.4 Example of the Address Match Detection Function

Figure 21.4-1 "System Configuration Example of the Address Match Detection Function" shows a system configuration example of the address match detection

function. Table 21.4-1 "E2PROM Memory Map" lists the E2PROM memory map.

■ System Configuration Example of the Address Match Detection Function

Figure 21.4-1 System Configuration Example of the Address Match Detection Function

❍ Initial status

E2PROM is set to all 0s.

E2PROMMCU

F2MC16LX

SIN (UART)Pull-up resister

Connector

Table 21.4-1 E2PROM Memory Map

Address Description

0000H Number of bytes of patch program No.0 (If 0, no program error exists.)

0001H Program address No.0 bits 7 to 0



0004H Number of bytes of patch program No.1 (If 0, no program error exists.)




0010H or higher Main body of patch program No. 0

342

21.4 Example of the Address Match Detection Function

❍ When a program error occurs:

The main body of the patch program and program address are transferred to the MCU through

the connector (UART). The MCU writes the information to E2PROM.

❍ Reset sequence

The MCU reads the value of E2PROM after reset. If the number of bytes of the patch program

is not 0, the main body of the patch program is read from E2PROM and written to RAM. TheMCU then uses either PADR0 or PADR1 to set the patch address and sets the compare enablebit. If the relocatable patch program is required, the first address of the patched program can bewritten to the RAM area. In this case, the INT9 routine accesses this user-defined RAM areaand jumps to the patched program.

❍ INT9 interrupt

The interrupt routine can know the address where the interrupt occurs by checking the value ofthe stack program counter. The information that has been placed on the stack during theinterrupt is discarded.

■ Example of program patch processing

Figure 21.4-2 Example of program patch processing

FFFFFFH

ROM

RAM

000000H

Abnormal program

PC

= a

dd

ress

in e

rro

r

External E2PROM

Register set for program patch

Number of program bytes

Corrected programAddress where the interrupt occurs

Data transfer using UART

Corrected program

343


Figure 21.4-3 Flow of program patch processing

INT9YES

0000H(E2PROM)=0

NO

0001H to 0003H (E2PROM)MOV

PADR0 (MCU)

0010H to 0090H (E2PROM)MOV

000400H to 000480H (MCU)

MOV PACSR, #02H

NOPC=PADR0

YES

INT9FFFFFFH

FF0050H

ROMEEPROM FF0000H

FFFFH

FE0000H

0090H

0010H 001100H

0003H 000480H

RAM0002H 000400H

0001H 000100H

0000H 000000H

Reset

Reads 00H of E2PROM

To patch programJMP 000400H

Read address

Execute patch program000400H to 000480H

Read patch program Terminate patch programJMP FF0050H

Enable compare

Execute normal program

Abnormal program

Patch program

Patch program

Stack area

RAM area

RAM and register area

I/O area

Program address low-order: 00

Program address middle-order: 00

Program address high-order: FF

Number of bytes of the patch program: 80

344

CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE

This chapter explains the ROM mirroring function selection module.

22.1 "Outline of ROM Mirroring Function Selection Module"

22.2 "ROM Mirroring Function Selection Register (ROMM)"

345


22.1 Outline of ROM Mirroring Function Selection Module

The ROM Mirroring function selection module switches whether to mirror the image of the FF bank of the ROM to the 00 bank.

■ Block Diagram of ROM Mirroring Function Selection Module

Figure 22.1-1 Block Diagram of ROM Mirroring Function Selection Module

ROM Mirrroring Function Selection Register

ROM

00 bankFF bank

Address Area

Address

Data

Inte

rnal

dat

a bu

s

346

22.2 ROM Mirroring Function Selection Register (ROMM)

22.2 ROM Mirroring Function Selection Register (ROMM)

Do not access the ROM mirroring function selection register (ROMM) when addresses 004000H to 00FFFFH are being accessed.

■ ROM Mirroring Function Selection Register (ROMM)

Figure 22.2-1 ROM Mirroring Function Selection Register (ROMM)

[bit 8]: MI

The image of the ROM data in the FF bank can also be found in the 00 bank when "1" iswritten to this bit. However, this memory mapping will not be done when this bit is written to"0". This bit is write only.

Note:

Only FF4000H to FFFFFFH is mirrored to 004000H to 00FFFFH when ROM mirroring functionis activated. Therefore, addresses FF0000H to FF3FFFH will not be mirrored to 00 bank.

15 14 13 12 11 10 9 8

— — — — — — — MIAddress : 0006FH ROMM

(–) (–) (–) (–) (–) (–) (–) (1)Initial value

Bit No.

(–) (–) (–) (–) (–) (–) (W)Read/write (–)

ROM Mirroring Function Selection Module

347


348

CHAPTER 23 1M/2M-BIT FLASH MEMORY

This chapter explains the functions and operation of the 1M/2M-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory:• Parallel programmer• Serial programmer• Executing programs to write/erase dataThis chapter explains "Executing programs to write/erase data".

23.1 "Outline of 1M/2M-bit Flash Memory"

23.2 "Sector Configuration of the Flash Memory"

23.3 "Write/Erase Modes"

23.4 "Flash Memory Control Status Register (FMCS)"

23.5 "Starting the Flash Memory Automatic Algorithm"

23.6 "Confirming the Automatic Algorithm Execution State"

23.7 "Detailed Explanation of Writing to Erasing Flash Memory"

23.8 "Notes on using 1M/2M-bit Flash Memory"

23.9 "Flash Security Feature"

23.10 "Example of Programming 1M/2M-bit Flash Memory"

349


23.1 Outline of 1M/2M-bit Flash Memory

The 1M/2M-bit flash memory is mapped to the FEH/FCH to FFH bank in the CPU

memory map. The functions of the flash memory interface circuit enable read-access and program-access from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory. Internal CPU control therefore enables rewriting of the flash memory while it is mounted. As a result, improvements in programs and data can be performed efficiently.

■ 1M/2M-bit Flash Memory Features

• Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29LV200)

• Erase pause/restart functions provided

• Detection of completion of writing/erasing using data polling or toggle bit functions

• Detection of completion of writing/erasing using CPU interrupts

• Sector erase function (any combination of sectors)

• Minimum of 10,000 write/erase operations

Embedded Algorithm is a trademark of Advanced Micro Device, Inc.

Note:

The manufacturer code and device code do not have the reading function. These codescannot be accessed by the command.

■ Writing to/Erasing Flash Memory

The flash memory cannot be written to and read at the same time. That is, when data is writtento or erased data from the flash memory, the program in the flash memory must first be copiedto RAM. The entire process is then executed in RAM so that data is simply written to the flashmemory. This eliminates the need for the program to access the flash memory from the flashmemory itself.

■ Flash Memory Register

Figure 23.1-1 Flash Memory Control Status Register (FMCS)

7 6 5 4 3 2 1 0

INTE RDYINT WE RDY Reserved LPM1 Reserved LPM0

(R/W) (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (X) (0) (0) (0) (0)

Address: 0000AEH

Read/write ⇒

Initial value ⇒

⇐ Bit No.

FMCS

350

23.2 Sector Configuration of the Flash Memory

23.2 Sector Configuration of the Flash Memory

Figure 23.2-1 "Sector Configuration of the 1M/2M-bit Flash Memory" shows the sector configuration of the flash memory.

■ Sector Configuration of the 1M/2M-bit Flash Memory

Figure 23.2-1 "Sector Configuration of the 1M/2M-bit Flash Memory" shows the sectorconfiguration of the 1M/2M-bit flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector.

Figure 23.2-1 Sector Configuration of the 1M/2M-bit Flash Memory

*: The programmer address is equivalent to the CPU address when data is written to the flashmemory using a parallel programmer. When a general programmer is used for writing/erasing, this address is used for writing/erasing.

Programmer address*

7FFFFH

7BFFFH

79FFFH

77FFFH

6FFFFH

60000 H

CPU address

FFFFFFH

FFBFFFH

FF9FFFH

FF7FFFH

FEFFFFH

FE0000 H

SA4 (16K bytes)

SA2 (8K bytes)

SA1 (32K bytes)

SA0 (64K bytes)

Programmer address*

7FFFFH

7BFFFH

79FFFH

77FFFH

6FFFFH

5FFFFH

4FFFFH

40000 H

CPU address

FFFFFFH

FFBFFFH

FF9FFFH

FF7FFFH

FEFFFFH

FDFFFFH

FCFFFFH

FC0000 H

SA6 (16K bytes)

SA5 (8K bytes)

SA4 (8K bytes)

SA3 (32K bytes)

SA2 (64K bytes)

SA1(64K bytes)

SA0 (64K bytes)

Flash memory Flash memory

SA3 (8K bytes)

351


23.3 Write/Erase Modes

The flash memory can be accessed in two different ways: Flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus. Use the mode external pins to select the mode.

■ Flash Memory Mode

The CPU stops when the mode pins are set to 111 while the reset signal is asserted. The flashmemory interface circuit is connected directly to ports 0, 2, 3, and 4, enabling direct control fromthe external pins. This mode makes the MCU seem like a standard flash memory to theexternal pins, and write/erase can be performed using a flash memory programmer.

In flash memory mode, all operations supported by the flash memory automatic algorithm canbe used.

■ Alternative Mode

The flash memory is located in the FE/FC to FF banks in the CPU memory space, and likeordinary mask ROM, can be read-accessed and program-accessed from the CPU via the flashmemory interface circuit.

Since writing/erasing the flash memory is performed by instructions from the CPU via the flashmemory interface circuit, this mode allows rewriting even when the MCU is soldered on thetarget board.

Sector protect operations cannot be performed in these modes.

■ Flash Memory Control Signals

Table 23.3-1 "Flash Memory Control Signals" lists the flash memory control signals in flashmemory mode.

There is almost a one-to-one correspondence between the flash memory control signals and theexternal pins of the MBM29LV200. The VID (12 V) pins required by the sector protectoperations are MD0, MD1, and MD2 instead of A9, RESET, and OE for the MBM29LV200.

In flash memory mode, the external data bus signal width is limited to 8 bits, enabling only one-byte access. The DQ15 to DQ8 pins are not supported. The BYTE pin should always be set to0.

352

23.3 Write/Erase Modes

Table 23.3-1 Flash Memory Control Signals

MB90F438L(S)/F439(S)MBM29LV200

Pin number Normal function Flash memory mode

1 to 8 P20 to P27 AQ0 to AQ7 A-1, A0 to A6

9 P30 AQ16 A15

10 P31 CE CE

12 P32 OE OE

13 P33 WE WE

14 P34 AQ17 A16

16 P36 BYTE BYTE

17 P37 RY/BY RY/BY

18 to 22 P40 to P44 AQ8 to AQ12 A7 to A11

24 to 26 P45 to P47 AQ13 to AQ15 A12 to A14

49 MD0 MDO A9 (VID)

50 MD1 MD1 RESET (VID)

51 MD2 MD2 OE (VID)

85 to 92 P00 to P07 DQ0 to DQ7 DQ0 to DQ7

77 RST RESET RESET

Not supported DQ8 to DQ15

353


23.4 Flash Memory Control Status Register (FMCS)

The flash memory control status register (FMCS), together with the flash memory interface circuit, is used to write data to and erase data from the flash memory.

■ Flash Memory Control Status Register (FMCS)

Figure 23.4-1 Flash Memory Control Status Register (FMCS)

[Bit 7] INTE (interrupt enable)

This bit generates an interrupt to the CPU when flash memory write/erase terminates.

An interrupt to the CPU is generated when the INTE and RDYINT bits are 1. No interrupt isgenerated when the INTE bit is 0.

• 0: Disables interrupts when write/erase terminates.

• 1: Enables interrupts when write/erase terminates.

[Bit 6] RDYINT (ready interrupt)

This bit indicates the operating state of the flash memory.

This bit is set to 1 when flash memory write/erase terminates. Data cannot be written to orerased from the flash memory while this bit is 0 after a flash memory write/erase. Flashmemory write/erase is enabled when write/erase terminates and this bit is set to 1.

Writing 0 clears this bit to 0. Writing 1 is ignored. This bit is set to 1 at the termination timingof the flash memory automatic algorithm (see Section 23.5 "Starting the Flash MemoryAutomatic Algorithm"). When the read-modify-write (RMW) instruction is used, 1 is alwaysread.

• 0: Write/erase is being executed.

• 1: Write/erase has terminated (interrupt request generated).

[Bit 5] WE (write enable)

This bit enables writing to the flash memory area.

When this bit is 1, writing after the command sequence (see Section 23.5 "Starting the FlashMemory Automatic Algorithm") is issued to the FE/FC to FF bank writes to the flash memoryarea. When this bit is 0, the write/erase signal is not generated. This bit is used when theflash memory Write/Erase command is started.

If write/erase is not performed, it is recommended that this bit be set to 0 to prevent datafrom being mistakenly written to the flash memory.

• 0: Disables flash memory write/erase.

• 1: Enables flash memory write/erase.

7 6 5 4 3 2 1 0

INTE RDYINT WE RDY Reserved LPM1 Reserved LPM0

(R/W) (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (X) (0) (0) (0) (0)

Address: 0000AEH

Read/write

Initial value

Bit No.

FMCS

Flash Memory Control Status Register (FMCS)

354

23.4 Flash Memory Control Status Register (FMCS)

[Bit 4] RDY (ready)

This bit enables flash memory write/erase.

Flash memory write/erase is disabled while this bit is 0. However, Suspend commands,such as the Read/Reset command and Sector Erase Suspend command, can be acceptedeven if this bit is 0.

• 0: Write/erase is being executed (next data write/erase disabled).

• 1: Write/erase has terminated (next data write/erase enabled).

[Bit 3] Reserved bits

These bits are reserved for testing. During regular use, they should always be set to 0.

[Bit 1] Free bit

During regular use, this bit should always be set to 0.

[Bits 2 and 0] LPM1 and LPM0 (low-power mode)

These bits control the current consumed by the flash memory when the flash memory isaccessed. Since the access time to the flash memory from the CPU is largely dependent onthis setting, select a setting value based on the operating frequency of the CPU.

• 01: Low-power consumption mode (Operates at an internal operating frequency up to 4MHz.)



• 00: Regular power consumption mode (Operates at an internal operating frequency up to 16MHz.)

Note:

The RDYINT and RDY bits cannot be changed at the same time. Create a program so thatdecisions are made using one or the other of these bits.

Figure 23.4-2 RDYINT and RDY Bit Change Timing

1 machine cycle

Automatic algorithm Termination timing RDYINT bit RDY bit

355


23.5 Starting the Flash Memory Automatic Algorithm

Four types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, and Chip Erase. Control of suspend and restart is enabled for sector erase.

■ Command Sequence Table

Table 23.5-1 "Command Sequence Table" lists the commands used for flash memory write/erase. All of the data written to the command register is in bytes, but use word access to write.The data of the high-order bytes at this time is ignored.

Note:

• The addresses Fx in the table mean FF and FE for 1M-bit flash memory, FF, FE, FD and FCfor 2M-bit flash memory. Use these addresses as the access target bank values foroperations.

• The addresses in the table are the values in the CPU memory map. All addresses and dataare represented using hexadecimal notation. However, the letter X is an optional value.

• RA: Read address

• PA: Write address. Only even addresses can be specified.

• SA: Sector address. See Section 23.2 "Sector Configuration of the Flash Memory".

• RD: Read data

• PD: Write data. Only word data can be specified.

*1: Both of the two types of Read/Reset commands can reset the flash memory to read mode.

Table 23.5-1 Command Sequence Table

Command sequence

Bus write

access

1st bus write cycle 2nd bus write cycle

3rd bus write cycle

4th bus write cycle

5th bus write cycle

6th bus write cycle

Address Data Address Data Address Data Address Data Address Data Address Data

Read/Reset (*1)

1 FxXXXX XXF0 - - - - - - - - - -

Read/Reset (*1) 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXF0 RA RD - - - -

Write program 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXA0 PA

(even)PD

(word) - - - -

Chip Erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 FxAAAA XX10

Sector Erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 SA(even) XX30

Sector Erase Suspend Entering address FxXXXX data (xxB0H) suspends erasing during sector erase.

Sector Erase Restart Entering address FxXXXX data (xx30H) restarts erasing after erasing is suspended during sector erase.

Auto-select 3 FxAAA XXAAA Fx5554 XX55 FxAAAA XX90 - - - - - -

356

23.5 Starting the Flash Memory Automatic Algorithm

The Auto-select command shown in Table 23.5-1 "Command Sequence Table" is used to knowthe state of sector protection. When using the Auto-select command, set the address asfollows.

Table 23.5-2 Address Setting at Auto-select

AQ13 to AQ16 AQ7 AQ2 AQ1 AQ0 DQ7 to DQ0

Sector protection Sector Address L H L L CODE*

*: When the sector address is protected, the output is "01H". When the sector address is not protected, the output is "00H".

357


23.6 Confirming the Automatic Algorithm Execution State

Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequences.

■ Hardware Sequence Flags

The hardware sequence flags are configured from the four-bit output of DQ7, DQ6, DQ5, DQ3and DQ2. The functions of these bits are those of the data polling flag (DQ7), toggle bit flag(DQ6), timing limit exceeded flag (DQ5), sector erase timer flag (DQ3) and toggle bit 2 flag(DQ2). The hardware sequence flags can therefore be used to confirm that writing or chipsector erase has been completed or that erase code write is valid.

The hardware sequence flags can be accessed by read-accessing the addresses of the targetsectors in the flash memory after setting of the command sequence (see Table 23.5-1"Command Sequence Table" in Section 23.5 "Starting the Flash Memory Automatic Algorithm".Table 23.6-1 "Bit Assignments of Hardware Sequence Flags" lists the bit assignments of thehardware sequence flags.

To determine whether automatic writing or chip sector erase is being executed, the hardwaresequence flags can be checked or the status can be determined from the RDY bit of the flashmemory control register (FMCS) that indicates whether writing has been completed. Afterwriting/erasing has terminated, the state returns to the read/reset state. When creating aprogram, use one of the flags to confirm that automatic writing/erasing has terminated. Then,perform the next processing operation, such as data read. In addition, the hardware sequenceflags can be used to confirm whether the second or subsequent sector erase code write is valid.The following sections describe each hardware sequence flag separately. Table 23.6-2"Hardware Sequence Flag Functions" lists the functions of the hardware sequence flags.

Table 23.6-1 Bit Assignments of Hardware Sequence Flags

Bit No. 7 6 5 4 3 2 1 0

Hardware sequence flag DQ7 DQ6 DQ5 - DQ3 DQ2 - -

358


Table 23.6-2 Hardware Sequence Flag Functions

State DQ7 DQ6 DQ5 DQ3 DQ2

State change for normal operation

Write --> Write completed (write address specified)

DQ7 -->DATA:7

Toggle -->DATA:6

0 -->DATA:5

0 -->DATA:3

1 -->DATA:2

Chip/sector erase --> Erase completed

0 --> 1Toggle -->Stop

0 --> 1 1Toggle --> Stop

Sector erase wait --> Erase started 0 Toggle 0 0 --> 1 Toggle

Erase --> Sector erase suspended (sector being erased)

0 --> 1Toggle -->1

0 1 --> 0 Toggle

Sector erase suspend --> Erase restarted (sector being erased)

1 --> 01 -->Toggle

0 0 --> 1 Toggle

Sector erase suspended (sector not being erased)

DATA:7 DATA:6 DATA:5 DATA:3 DATA:2

Abnormal operation

Write DQ7 Toggle 1 0 1

Chip/sector erase 0 Toggle 1 1 *1

*1: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle. DQ2 does not toggle when the successive reads are executed from other sectors.

359


23.6.1 Data Polling Flag (DQ7)

The data polling flag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated

■ Data Polling Flag (DQ7)

Table 23.6-3 "Data Polling Flag State Transitions (State Change for Normal Operation)" andTable 23.6-4 "Data Polling Flag State Transitions (State Change for Abnormal Operation)" listthe state transitions of the data polling flag.

❍ Write

Read-access during execution of the automatic write algorithm causes the flash memory tooutput the opposite data of bit 7 last written, regardless of the value at the address specified bythe address signal. Read-access at the end of the automatic write algorithm causes the flashmemory to output bit 7 of the read value of the address specified by the address signal.

❍ Chip/sector erase

For a sector erase, read-access during execution of the chip erase/sector erase algorithmcauses the flash memory to output 0 from the sector currently being erased. For a chip erase,read-access causes the flash memory to output 0 regardless of the value at the addressspecified by the address signal. Read-access at the end of the automatic write algorithmcauses the flash memory to output 1 in the same way.

❍ Sector erase suspend

Read-access during a sector erase suspend causes the flash memory to output 1 if the addressspecified by the address signal belongs to the sector being erased. The flash memory outputsbit 7 (DATA: 7) of the read value at the address specified by the address signal if the addressspecified by the address signal does not belong to the sector being erased. Referencing thisflag together with the toggle bit flag (DQ6) enables a decision to be made on whether the flashmemory is in the erase suspended state and which sector is being erased.

Table 23.6-3 Data Polling Flag State Transitions (State Change for Normal Operation)

Operating state

Write --> Completed

Chip/sector erase --> Completed

Sector erase wait--> Started

Sector erase --> Erase suspend (sector being erased)

Sector erase suspend --> Restarted (sector being erased)


DQ7 DQ7 --> DATA:7

0 --> 1 0 0 --> 1 1 --> 0 DATA:7

Table 23.6-4 Data Polling Flag State Transitions (State Change for Abnormal Operation)

Operating state

Write Chip/sector erase

DQ7 DQ7 0

360


Note:

When the automatic algorithm is being started, read-access to the specified address isignored. Since termination of the data polling flag (DQ7) can be accepted for a data readand other bits output, data read after the automatic algorithm has terminated should beperformed after read-access has confirmed that data polling has terminated.

361


23.6.2 Toggle Bit Flag (DQ6)

Like the data polling flag (DQ7), the toggle bit flag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated.

■ Toggle Bit Flag (DQ6)

Table 23.6-5 "Toggle Bit Flag State Transitions (State Change for Normal Operation)" and Table23.6-6 "Toggle Bit Flag State Transitions (State Change for Abnormal Operation)" list the statetransitions of the toggle bit flag.

❍ Write/chip sector erase

Continuous read-access during execution of the automatic write algorithm and chip/sector erasealgorithm causes the flash memory to toggle the 1 or 0 state for every read cycle, regardless ofthe value at the address specified by the address signal. Continuous read-access at the end ofthe automatic write algorithm and chip/sector erase algorithm causes the flash memory to stoptoggling bit 6 and output bit 6 (DATA: 6) of the read value of the address specified by theaddress signal.

❍ Sector erase suspend

Read-access during a sector erase suspend causes the flash memory to output 1 if the addressspecified by the address signal belongs to the sector being erased. The flash memory outputsbit 6 (DATA: 6) of the read value at the address specified by the address signal if the addressspecified by the address signal does not belong to the sector being erased.

Note:

For a write, if the sector where data is to be written is rewrite-protected, the toggle bitterminates the toggle operation after approximately 2μs without any data being rewritten.For an erase, if all of the selected sectors are write-protected, the toggle bit performstoggling for approximately 100μs and then returns to the read/reset state without any databeing rewritten.

Table 23.6-5 Toggle Bit Flag State Transitions (State Change for Normal Operation)

Operating state

Write --> Completed


Sector erase wait --> Started




DQ6Toggle --> DATA:6

Toggle -->Stop

Toggle Toggle --> 1 1 --> Toggle DATA:6

Table 23.6-6 Toggle Bit Flag State Transitions (State Change for Abnormal Operation)

Operating state


DQ6 Toggle Toggle

362


23.6.3 Timing Limit Exceeded Flag (DQ5)

The timing limit exceeded flag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory.

■ Timing Limit Exceeded Flag (DQ5)

Table 23.6-7 "Timing Limit Exceeded Flag State Transitions (State Change for NormalOperation") and Table 23.6-8 "Timing Limit Exceeded Bit Flag State Transitions (State Changefor Abnormal Operation)" list the state transitions of the timing limit exceeded flag.

❍ Write/chip sector erase

Read-access after write or chip/sector erase automatic algorithm activation causes the flashmemory to output 0 if the time is within the prescribed time (time required for write/erase) or tooutput 1 if the prescribed time has been exceeded. Because this is done regardless of whetherthe automatic algorithm is being executed or has terminated, it is possible to determine whetherwrite/erase was successful or unsuccessful. That is, when this flag outputs 1, writing can bedetermined to have been unsuccessful if the automatic algorithm is still being executed by thedata polling function or toggle bit function.

For example, writing 1 to a flash memory address where 0 has been written will cause the failstate to occur. In this case, the flash memory will lock and execution of the automatic algorithmwill not terminate. As a result, valid data will not be output from the data polling flag (DQ7). Inaddition, the toggle bit flag (DQ6) will exceed the time limit without stopping the toggle operationand the timing limit exceeded flag (DQ5) will output 1. Note that this state indicates that theflash memory is not faulty, but has been used correctly. When this state occurs, execute theReset command.

Table 23.6-7 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation)

Operating state

Write --> Completed






DQ5 0 --> DATA:5

0 --> 1 0 0 0 DATA:5

Table 23.6-8 Timing Limit Exceeded Bit Flag State Transitions (State Change for Abnormal Operation)

Operating state


DQ5 1 1

363


23.6.4 Sector Erase Timer Flag (DQ3)

The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is being executed during the sector erase wait period after the Sector Erase command has been started.

■ Sector Erase Timer Flag (DQ3)

Table 23.6-9 "Sector Erase Timer Flag State Transitions (State Change for Normal Operation)"and Table 23.6-10 "Sector Erase Timer Flag State Transitions (State Change for AbnormalOperation)" list the state transitions of the sector erase timer flag.

❍ Sector erase

Read-access after the Sector Erase command has been started causes the flash memory tooutput 0 if the automatic algorithm is being executed during the sector erase wait period,regardless of the value at the address specified by the address signal of the sector that issuedthe command. The flash memory outputs 1 if the sector erase wait period has been exceeded.

If the data polling function or toggle bit function indicates that the erase algorithm is beingexecuted, internally controlled erase has already started if this flag is 1. Continuous write of thesector erase codes or commands other than the Sector Erase Suspend command will beignored until erase is terminated.

If this flag is 0, the flash memory will accept write of additional sector erase codes. To confirmthis, it is recommended that the state of this flag be checked before continuing to write sectorerase codes. If this flag is 1 after the second state check, it is possible that additional sectorerase codes may not be accepted.

Table 23.6-9 Sector Erase Timer Flag State Transitions (State Change for Normal Operation)

Operating state

Write --> Completed






DQ3 0 --> DATA:3

1 0 --> 1 1 --> 0 0 --> 1 DATA:3

Table 23.6-10 Sector Erase Timer Flag State Transitions (State Change for Abnormal Operation)

Operating state


DQ3 0 1

364


❍ Sector erase

Read-access during execution of sector erase suspend causes the flash memory to output 1 ifthe address specified by the address signal belongs to the sector being erased. The flashmemory outputs bit 3 (DATA: 3) of the read value of the address specified by the address

signal if the address specified by the address signal does not belong to the sector being erased.

365


23.6.5 Toggle Bit 2 Flag (DQ2)

The toggle bit 2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the sector is in the erase-suspended state.

■ Toggle Bit 2 Flag (DQ2)

Table 23.6-11 "Toggle Bit 2 Flag State Transitions (State Change for Normal Operation)" andTable 23.6-12 "Toggle Bit 2 Flag State Transitions (State Change for Abnormal Operation)" listthe state transitions of the toggle bit flag.

❍ During a sector erase operation

If successive reads are executed during the execution of the chip sector erase algorithm, a flashmemory toggles to output "1" and "0" to addresses alternately at every read access regardlessof the location indicated by the addresses. If successive reads are executed after the chipsector erase algorithm is completed, the flash memory stops the toggle operation of the bit 2and outputs the read value of the bit 2 (DATA: 2) to the location indicated by the address.

Table 23.6-11 Toggle Bit 2 Flag State Transitions (State Change for Normal Operation)

Operating state

Write --> Completed






DQ21 --> DATA:2

Toggle -->Stop

Toggle Toggle Toggle DATA:2

Table 23.6-12 Toggle Bit 2 Flag State Transitions (State Change for Abnormal Operation)

Operating state


DQ2 1 *1

*1: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle. DQ2 does not toggle when the successive reads are executed from other sectors.

366


❍ While a sector erase operation is suspended

If successive reads are executed while a sector erase operation is suspended, and if theaddress indicates the sector to be erased, the flash memory toggles to alternately output "1"and "0". If the address indicates the sector is not to be erased, the flash memory outputs theread value of the bit 2 (DATA: 2) to the location indicated by the address.

In the erase-suspend-program mode, successive reads from the non-erase suspended sectorcauses the flash memory to output "1".

Both DQ2 and DQ6 are used for detecting an erase-suspended sector (DQ2 toggles, but DQ6does not).

DQ2 is also used for detecting an erasing sector. While erasing a sector, if a read access isexecuted from the erasing sector, DQ2 toggles.

Reference:

If all sectors selected for erasing are write-protected, the toggle bit 2 toggles for about 100μs,

and then returns to the read/reset mode without writing the data.

367


23.7 Detailed Explanation of Writing to and Erasing Flash Memory

This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a command that starts the automatic algorithm is issued.

■ Detailed Explanation of Flash Memory Write/Erase

The flash memory executes the automatic algorithm by issuing a command sequence (seeTable 23.5-1 "Command Sequence Table" in Section 23.5 "Starting the Flash MemoryAutomatic Algorithm") for a write cycle to the bus to perform Read/Reset, Write, Chip Erase,Sector Erase, Sector Erase Suspend, or Sector Erase Restart operations. Each bus write cyclemust be performed continuously. In addition, whether the automatic algorithm has terminatedcan be determined using the data polling or other function. At normal termination, the flashmemory is returned to the read/reset state.

Each operation of the flash memory is described in the following order:

• Setting the read/reset state

• Writing data

• Erasing all data (erasing chips)

• Erasing optional data (erasing sectors)

• Suspending sector erase

• Restarting sector erase

368


23.7.1 Setting The Read/Reset State

This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state.

■ Setting the Flash Memory to the Read/Reset State

The flash memory can be set to the read/reset state by sending the Read/Reset command inthe command sequence table (see Table 23.5-1 "Command Sequence Table" in Section 23.5"Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flashmemory.

The Read/Reset command has two types of command sequences that execute the first andthird bus operations. However, there are no essential differences between these commandsequences.

The read/reset state is the initial state of the flash memory. When the power is turned on andwhen a command terminates normally, the flash memory is set to the read/reset state. In theread/reset state, other commands wait for input.

In the read/reset state, data is read by regular read-access. As with the mask ROM, programaccess from the CPU is enabled. The Read/Reset command is not required to read data by aregular read. The Read/Reset command is mainly used to initialize the automatic algorithm insuch cases as when a command does not terminate normally.

369


23.7.2 Writing Data

This section describes the procedure for issuing the Write command to write data to the flash memory.

■ Writing Data to the Flash Memory

The data write automatic algorithm of the flash memory can be started by sending the Writecommand in the command sequence table (see Table 23.5-1 "Command Sequence Table" inSection 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the target sectorin the flash memory. When data write to the target address is completed in the fourth cycle, theautomatic algorithm and automatic write are started.

❍ Specifying addresses

Only even addresses can be specified as the write addresses specified in a write data cycle.Odd addresses cannot be written correctly. That is, writing to even addresses must be done inunits of word data.

Writing can be done in any order of addresses or even if the sector boundary is exceeded.However, the Write command writes only data of one word for each execution.

❍ Notes on writing data

Writing cannot return data 0 to data 1. When data 1 is written to data 0, the data pollingalgorithm (DQ7) or toggle operation (DQ6) does not terminate and the flash memory elementsare determined to be faulty. If the time prescribed for writing is thus exceeded, the timing limitexceeded flag (DQ5) is determined to be an error. Otherwise, the data is viewed as if dummydata 1 had been written. However, when data is read in the read/reset state, the data remains0. Data 0 can be set to data 1 only by erase operations.

All commands are ignored during execution of the automatic write algorithm. If a hardwarereset is started during writing, the data of the written addresses will be unpredictable.

■ Writing to the Flash Memory

Figure 23.7-1 "Example of the Flash Memory Write Procedure" is an example of the procedurefor writing to the flash memory. The hardware sequence flags (see Section 23.6 "Confirmingthe Automatic Algorithm Execution State") can be used to determine the state of the automaticalgorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm that writinghas terminated.

The data read to check the flag is read from the address written to last.

The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5)changes. For example, even if the timing limit exceeded flag (DQ5) is 1, the data polling flag bit(DQ7) must be rechecked.

Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timinglimit exceeded flag bit (DQ5) changes to 1. The toggle bit flag (DQ6) must therefore berechecked.

370


Figure 23.7-1 Example of the Flash Memory Write Procedure

Data

Data

Data

0

1

Data

Start writing

FMCS: WE (bit 5) Enable flash memory write

Write command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XXA0 (4) Write address <-- Write data

Read internal address Next address

Data polling (DQ7)

Timing limit (DQ5)

Read internal address

Data polling (DQ7)

Write error Final address

FMCS: WE (bit 5) Disable flash memory write

Complete writingConfirm with the hardware sequence flags.

371


23.7.3 Erasing All Data (Erasing Chips)

This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory.

■ Erasing all Data in the Flash Memory (Erasing Chips)

All data can be erased from the flash memory by sending the Chip Erase command in thecommand sequence table (see Table 23.5-1 "Command Sequence Table" in Section 23.5"Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flashmemory.

The Chip Erase command is executed in six bus operations. When writing of the sixth cycle iscompleted, the chip erase operation is started. For chip erase, the user need not write to theflash memory before erasing. During execution of the automatic erase algorithm, the flashmemory writes 0 for verification before all of the cells are erased automatically.

372


23.7.4 Erasing Optional Data (Erasing Sectors)

This section describes the procedure for issuing the Sector Erase command to erase optional data (erase sector) in the flash memory. Individual sectors can be erased. Multiple sectors can also be specified at one time.

■ Erasing Optional Data (Erasing Sectors) in the Flash Memory

Optional sectors in the flash memory can be erased by sending the Sector Erase command inthe command sequence table (see Table 23.5-1 "Command Sequence Table" in Section 23.5"Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flashmemory.

❍ Specifying sectors

The Sector Erase command is executed in six bus operations. Sector erase wait of 50μs isstarted by writing the sector erase code (30h) to an accessible even-numbered address in thetarget sector in the sixth cycle. To erase multiple sectors, write the erase code (30h) to theaddresses in the target sectors after the above processing operation.

❍ Notes on specifying multiple sectors

Erase is started when the sector erase wait period of 50μs terminates after the final sector erasecode has been written. That is, to erase multiple sectors at one time, an erase code (sixth cycleof the command sequence) must be written within 50μs of writing of the address of a sector andthe address of the next sector must be written within 50μs of writing of the previous erase code.Otherwise, the address and erase code may not be accepted. The sector erase timer(hardware sequence flag DQ3) can be used to check whether writing of the subsequent sectorerase code is valid. At this time, specify so that the address used for reading the sector erasetimer indicates the sector to be erased.

■ Erasing Sectors in the Flash Memory

The hardware sequence flags (see Section 23.6 "Confirming the Automatic Algorithm ExecutionState") can be used to determine the state of the automatic algorithm in the flash memory.Figure 23.7-2 "Example of the Flash Memory Sector Erase Procedure" is an example of theprocedure for erasing sectors in the flash memory. Here, the toggle bit flag (DQ6) is used toconfirm that erasing has terminated.

The data that is read to check the flag is read from the sector to be erased.

The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limitexceeded flag (DQ5) is changed to 1. For example, even if the timing limit exceeded flag (DQ5)is 1, the toggle bit flag (DQ6) must be rechecked.

The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit(DQ5) changes. As a result, the data polling flag (DQ7) must be rechecked.

373


Figure 23.7-2 Example of the Flash Memory Sector Erase Procedure

N

Y

Y

0

1

N

Y

N

Y

N

0

Start erasing

FMCS: WE (bit 5) Enable flash memory erase

Erase command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XX80 (4) Fx5554 <-- XX55 (5) Sector address <--

Erase code (30H)Sector erase timer (DQ3)

(6) Sector address <--Erase code (30H)

Read internal address Another erase sector

Read internal address 1

Read internal address 2 Next sector

Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)

Timing limit (DQ5)



Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)

Erase error Final sector

FMCS: WE (bit 5) Disable flash memory erase

Complete erasing

Confirm with the hardware sequence flags.

1

374


23.7.5 Suspending Sector Erase

This section describes the procedure for issuing the Sector Erase Suspend command to suspend erasing of flash memory sectors. Data can be read from sectors that are not being erased.

■ Suspending Erasing of Flash Memory Sectors

Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspendcommand in the command sequence table (see Table 23.5-1 "Command Sequence Table" inSection 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the target sectorin the flash memory.

The Sector Erase Suspend command suspends the sector erase operation being executed andenables data to be read from sectors that are not being erased. In this state, only reading isenabled; data cannot be written. This command is valid only during sector erase operations thatinclude the erase wait time. The command will be ignored during chip erase or write operations.

This command is implemented by writing the erase suspend code (B0h). At this time, specifyan optional address in the flash memory for the address. An Erase Suspend command issuedagain during erasing of sectors will be ignored.

Entering the Sector Erase Suspend command during the sector erase wait period willimmediately terminate sector erase wait, cancel the erase operation, and set the erase stopstate. Entering the Erase Suspend command during the erase operation after the sector erasewait period has terminated will set the erase suspend state after a maximum period of 15μs haselapsed.

375


23.7.6 Restarting Sector Erase

This section describes the procedure for issuing the Sector Erase Restart command to restart suspended erasing of flash memory sectors.

■ Restarting Erasing of Flash Memory Sectors

Suspended erasing of flash memory sectors can be restarted by sending the Sector EraseRestart command in the command sequence table (see Table 23.5-1 "Command SequenceTable" in Section 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to thetarget sector in the flash memory.

The Sector Erase Restart command is used to restart erasing of sectors from the sector erasesuspend state set using the Sector Erase Suspend command. The Sector Erase Restartcommand is implemented by writing the erase restart code (30h). At this time, specify anoptional address in the flash memory area for the address.

If a Sector Erase Restart command is issued during sector erase, the command will be ignored.

376

23.8 Notes on using 1M/2M-bit Flash Memory

23.8 Notes on using 1M/2M-bit Flash Memory

This section contains notes on using 1M/2M-bit flash memory.

■ Notes on using flash memory

❍ Input of a hardware reset (RST)

To input a hardware reset when the automatic algorithm has not been started and reading is inprogress, a minimum low-level width of 500 ns must be maintained. In this case, a maximum of500 ns is required until data can be read from the flash memory after a hardware reset has beenactivated.

Similarly, to input a hardware reset when the automatic algorithm has been activated and writingor erasing is in progress, a minimum low-level width of 50 ns must be maintained. In this case,20 μs are required until data can be read after the operation for initializing the flash memory hasterminated.

A hardware reset during writing the data being written to be undefined. A hardware reset duringerasing may make the sector being erased unusable.

❍ Canceling of a software reset, watchdog timer reset, and hardware standby

When the flash memory is being written to or erased with CPU access and if reset conditionsoccur while the automatic algorithm is active, the CPU may run out of control. This occursbecause these reset conditions cause the automatic algorithm to continue without initializing theflash memory unit, possibly preventing the flash memory unit from entering the read state whenthe CPU starts the sequence after the reset has been deasserted. These reset conditions mustbe disabled during writing to or erasing of the flash memory.

❍ Program access to flash memory

When the automatic algorithm is operating, read access to the flash memory is disabled. Withthe memory access mode of the CPU set to internal ROM mode, writing or erasing must bestarted after the program area is switched to another area such as RAM. In this case, whensectors (SA4/SA6) containing interrupt vectors are erased, writing or erasing interruptprocessing cannot be executed. For the same reason, all interrupt sources other than the flashmemory are disabled while the automatic algorithm is operating.

Also, while the automatic algorithm is being executed, all interrupt sources except flash memoryare disabled.

❍ Hold function

When the CPU accepts a hold request, the Write signal WE of the flash memory unit may beskewed, causing erroneous writing or erasing due to an erroneous write. When the acceptanceof a hold request is enabled (HDE bit of EPCR set to 1), ensure that the WE bit of the controlstatus register (FMCS) is 0.

❍ Extended intelligent I/O service (EI2OS)

Because write and erase interrupts issued to the CPU from the flash memory interface circuit

cannot be accepted by the EI2OS, they should not be used.

377


❍ Applying VID

Applying VID required for the sector protect operation should always be started and terminatedwhen the supply voltage is on.

378

23.9 Flash Security Feature

23.9 Flash Security Feature

The Flash security Controller provides possibilities to protect the content of the flash memory from being read from external pins.

■ Flash Security Feature

One predefined address of the flash memory is assigned to the Flash Security Controller (1M-bitflash memory: FE0001, 2M-bit flash memory: FC0001). If the protection code of "01H" is writtenis this address, access to the flash memory is restricted. Once the flash memory is protected,performing the chip erase operation only can unlock the function otherwise read/write access tothe flash memory from any external pins is not generally possible.

This function is suitable for applications requiring security of self-containing and data stored inthe flash memory. If the target application requires any part of program to locate outside themicrocontroller, the Flash Security Controller can not offer the intended features. For thisreason, the External Vector Fetch mode should not be used when the protection code is set.

In order to re-program the once protected flash memory, the chip erase operation should beperformed.

379


23.10 Example of Programming 1M/2M-bit Flash Memory

This section presents a programming example of 1M/2M-bit flash memory.

■ Programming example of 1M/2M-bit flash memory

NAME FLASHWE TITLE FLASHWE;-------------------------------------------------------------------------------;1M/2M-bit-FLASH sample program;;1: Transmits the program (address: FFC000H, sector: SA4/SA6) from FLASH to RAM; (address: 000700H).;2: Executes the program on RAM.;3: Writes the PDR1 value to FLASH (address: FE0000H, sector: SA0/SA2).;4: Reads the written value (address: FD0000H, sector: SA0/SA2) and outputs it to PDR2.;5: Erases the written sector (SA0/SA2).;6: Checks and outputs erase data.;Conditions; - Number of bytes transmitted to RAM: 100H (256B); - Write/erase termination judgment; Judgment according to DQ5 (timing limit excess flag); Judgment according to DQ6 (toggle bit flag); Judgment according to RDY (FMCS); - Error handling; Hi output to P00 to P07; Reset command issuance;-------------------------------------------------------------------;RESOUS IOSEG ABS=00 ;"RESOUS" I/O segment definition ORG 0000HPDR0 RB 1PDR1 RB 1PDR2 RB 1PDR3 RB 1 ORG 0010HDDR0 RB 1DDR1 RB 1DDR2 RB 1DDR3 RB 1 ORG 00A1HCKSCR RB 1 ORG 00AEHFMCS RB 1 ORG 006FHROMM RB 1RESOUS ENDS;SSTA SSEG RW 0127HSTA_T RW 1SSTA ENDS;DATA DSEG ABS=0FFH ;FLASH command address ORG 5554HCOMADR2 RW 1 ORG 0AAAAHCOMADR1 RW 1DATA ENDS

380


;/////////////////////////////////////////////////////////////;Main program (SAI);/////////////////////////////////////////////////////////////CODE CSEGSTART: ;///////////////////////////////////////////////////// ; Initialization ;///////////////////////////////////////////////////// MOV CKSCR,#0BAH ;3-multiple setting MOV RP,#0 MOV A,#!STA_T MOV SSB,A MOVW A,#STA_T MOVW SP,A MOV ROMM,#00H ;Mirror OFF MOV PDR0,#00H ;For error check MOV DDR0,#0FFH MOV PDR1,#00H ;Port for data input MOV DDR1,#00H MOV PDR2,#00H ;Port for data output MOV DDR2,#0FFH; //////////////////////////////////////////////////////////////; Transfer of "FLASH write erase program (FFC000H)" to RAM (700H address); ////////////////////////////////////////////////////////////// MOVW A,#0700H ;Transfer destination RAM area MOVW A,#0C000H ;Transfer source address (program position) MOVW RW0,#100H ;Number of bytes to be transferred MOVS ADB,PCB ;Transfer of 100H from FFBC00H to 00700H CALLP 000700H ;Jump to the address containing the transferred; program; /////////////////////////////////////////////////////; Data output; /////////////////////////////////////////////////////OUT MOV A,#0FEH MOV ADB,A MOVW RW2,#0000H MOVW A,@RW2+00 MOV PDR2,AEND JMP *CODE ENDS;////////////////////////////////////////////////////////////;FLASH write erase program (SA4/SA6);////////////////////////////////////////////////////////////RAMPRG CSEG ABS=0FFH ORG 0C000H; //////////////////////////////////////////// Initialization; //////////////////////////////////////////// MOVW RW0,#0500H ;RW0:RAM space for input data acquisition 00:0500 to MOVW RW2,#0000H ;RW2:Flash memory write address FD:0000 to MOV A,#00H ;DTB modification MOV DTB,A ;Bank specification for @RW0 MOV A,#0FDH ;ADB modification 1 MOV ADB,A ;Bank specification for write mode specification; address MOV PDR3,#00H ;Switch initialization MOV DDR3,#00H;WAIT1 BBC PDR3:0,WAIT1 ;PDR3: 0(write start at high level);;////////////////////////////////////////////////;Write (SA0/SA2);//////////////////////////////////////////////// MOV A,PDR1 MOVW @RW0+00,A ;PDR1 data allocation to RAM MOV FMCS,#20H ;Write mode setting MOVW ADB:COMADR1,#00AAH ;Flash write command 1 MOVW ADB:COMADR2,#0055H ;Flash write command 2

381


MOVW ADB:COMADR1,#00A0H ;Flash write command 3; MOVW A,@RW0+00 ;Input data (RW0) write to flash memory (RW2) MOVW @RW2+00,AWRITE ;Wait time check; ///////////////////////////////////////////////////////////////////; ERROR when the time limit excess check flag is set and toggle operation is ; in progress; /////////////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOW ;Time limit over MOVW A,@RW2+00 ;AH MOVW A,@RW2+00 ;AL XORW A ;XOR of AH and AL (1 when the values differ) AND A,#40H ;Is the DQ6 toggle bit different? BNZ ERROR ;To ERROR when the DQ6 toggle bit is different; ///////////////////////////////////////; Write termination check (FMCS-RDY); ///////////////////////////////////////; ///////////////////////////////////////NTOW MOVW A,FMCS AND A,#10H ;Extraction of FMCS RDY bit (bit 4) BZ WRITE ;End of write? MOV FMCS,#00H ;Write mode release; /////////////////////////////////////////////////////; Write data output; ///////////////////////////////////////////////////// MOVW RW2,#0000H ;Write data output MOVW A,@RW2+00 MOV PDR2,A;WAIT2 BBC PDR3:1,WAIT2 ;PDR3: 1(sector erase start at high level);;/////////////////////////////////////////////;Sector erase (SA0/SA2);///////////////////////////////////////////// MOV @RW2+00,#0000H ;Address initialization MOV FMCS,#20H ;Erase mode setting MOVW ADB:COMADR1,#00AAH ;Flash erase command 1 MOVW ADB:COMADR2,#0055H ;Flash erase command 2 MOVW ADB:COMADR1,#0080H ;Flash erase command 3 MOVW ADB:COMADR1,#00AAH ;Flash erase command 4 MOVW ADB:COMADR2,#0055H ;Flash erase command 5 MOV @RW2+00,#0030H ;Issuance of erase command 6 to the sector to be erasedELS ;Wait time check; ///////////////////////////////////////////////////////////////////; ERROR when the time limit excess check flag is set and toggle operation is ; in progress; /////////////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOE ;Time limit over MOVW A,@RW2+00 ;AH High and Low are alternately output from MOVW A,@RW2+00 ;AL DQ6 per read during write operation. XORW A ;XOR of AH and AL (If the DQ6 value differs, ; write operation is in progress (1)). AND A,#40H ;Is the DQ6 toggle bit High? BNZ ERROR ;ERROR when the DQ6 toggle bit is High; ///////////////////////////////////////; Erase termination check (FMCS-RDY); ///////////////////////////////////////NTOE MOVW A,FMCS ; AND A,#10H ;Extraction of FMCS RDY bit (bit 4) BZ ELS ;End of sector erase? MOV FMCS,#00H ;FLASH erase mode release RETP ;Return to the main program

382


;//////////////////////////////////////////////;Error;//////////////////////////////////////////////ERROR MOV ADB:COMADR1,#0F0H ;Reset command (read is enabled) MOV FMCS,#00H ;FLASH mode release MOV PDR0,#0FFH ;Error handling check RETP ;Return to the main programRAMPRG ENDS;/////////////////////////////////////////////VECT CSEG ABS=0FFH ORG 0FFDCH DSL START DB 00HVECT ENDS; END START

383


384

CHAPTER 24 EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION

This chapter provides examples of serial programming connection with the AF220/AF210/AF120/AF110 flash microcomputer programmer manufactured by Yokogawa Digital Computer Corporation.

24.1 "Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection"

24.2 "Example of Serial Programming Connection (User Power Supply Used)"

24.3 "Example of Serial Programming Connection (Power Supplied from the Programmer)"

24.4 "Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)"

24.5 "Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer)"

385


24.1 Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection

The MB90F438L(S)/F439(S) supports flash ROM serial on-board programming (Fujitsu standard). This section describes the specifications.

■ Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection

The AF220/AF210/AF120/AF110 flash microcomputer programmer manufactured by YokogawaDigital Computer Corporation is used for Fujitsu standard serial on-board programming. Figure24.1-1 "Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection" showsthe basic configuration of the MB90F438L(S)/F439(S) serial programming connection.

Figure 24.1-1 Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection

Note:

Ask Yokogawa Digital Computer Corporation for information about the functions andoperations of the AF220/AF210/AF120/AF110 flash microcomputer programmer, general-purpose common cable (AZ210) for connection, and connectors.

Host interface cable

AF220/AF210/AF120/AF110

flash microcomputer programmer

+ memory card

General-purpose common cable (AZ210)

CLK synchronous serialRS232C MB90F438L(S)/F439(S)

user system

Stand-alone operation enabled

386


Even if the P00, SIN1, SOT1, and SCK1 pins are used for the user system, the control circuitshown in the figure below is required. (The /TICS signal of the flash microcomputerprogrammer can be used to disconnect the user circuit during serial programming).

Figure 24.1-2 Control Circuit

Sections 24.2 "Example of Serial Programming Connection (User Power Supply Used)" to 24.5"Example of Minimum Connection to the Flash Microcomputer Programmer (Power Suppliedfrom the Programmer)" present examples the following four types of serial programmingconnection. See each Section as required.

• Serial programming connection in MB90F438L(S)/F439(S) internal vector mode (user powersupply used)

• Serial programming connection in MB90F438L(S)/F439(S) internal vector mode (powersupplied from the Programmer)

• Example of minimum connection to the flash microcomputer programmer (user power supplyused)

• Example of minimum connection to the flash microcomputer programmer (power suppliedfrom the Programmer)

Table 24.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming

Pin Function Additional information

MD2, MD1MD0

Mode pins Controls programming mode from the flash microcomputer programmer.

X0, X1 Oscillation pins In programming mode, the CPU internal operation clock signal is one multiple of the PLL clock signal frequency. Therefore, because the oscillation clock frequency becomes the internal operation clock signal.

P00, P01 Programming activation pins -

RST Reset pin -

SIN1 Serial data input pin

The UART1 is used in CLK synchronous mode.SOT1 Serial data output pin

SCK1 Serial clock input pin

C C pin This external capacitor pin is used to stabilize the power supply. Connect a ceramic capacitor of approximately 0.1μF to the outside.

VCC Power voltage supply pin If the programming voltage (5 V 10%) is supplied from the user system, the flash microcomputer programmer need not be connected. Connect so that the power supply of the user side is not short-circuited.

VSS GND pin Common to the ground of the flash microcomputer programmer.

HST Hardware standby pin Input high level during serial programming mode.

AF220/AF210/AF120/AF110/ TICS pin

AF220/AF210/AF120/AF110 write control pin

MB90F438L(S)/F439(S)write control pin

User

10K

387


Inquiries: Yokogawa Digital Computer Corporation

Telephone number: (81)-42-333-6224

Note:

The AF200 flash microcomputer programmer, which is not supported now, can be used byusing control module FF201. For the serial programming connection information, see thefollowing section, "Oscillation Clock Frequency and Serial Clock Input Frequency".

Table 24.1-2 Flash Microcomputer Programmer System Configuration (Manufactured by Yokogawa Digital Computer Corporation)

Model Function

Mainframe AF220/AC4P Model with Ethernet interface built in / 100 to 220 V power adaptor

AF210/AC4P Standard model / 100V to 220 V power adaptor

AF120/AC4P Single-key Ethernet interface model / 100V to 220 V power adaptor

AF110/AC4P Single-key model/100V to 220 V power adaptor

AZ221 PC/AT RS232C cable only for Programmer

AZ210 Standard target probe (a), length: 1 m

FF201 Fujitsu F2MC-16LX flash microcomputer control model

AZ290 Remote controller

/P2 2 MB PC card (option) for flash memory sizes of up to 128 KB

/P4 4 MB PC card (option) for flash memory sizes of up to 512 KB

388


■ Oscillation Clock Frequency and Serial Clock Input Frequency

The formula shown below can be used to calculate the maximum serial clock frequency that canbe input to the MB90F438L(S)/F439(S).

Maximum serial clock frequency that can be input = 0.125 x oscillation clock frequency

Consequently, change the serial clock input frequency by setting the serial clock frequency ofthe flash microcomputer programmer according to the current oscillation clock frequency.

Table 24.1-3 Examples of the Maximum Serial Clock Frequency That Can Be Input

Oscillation or External clock

frequency

Maximum serial clock frequency that can be

input for the microcomputer

Maximum serial clock frequency that can be set with AF220/AF210/

AF120/AF110

Maximum serial clock frequency that can be

set with AF200

4 MHz 500 kHz 500 kHz 500 kHz

8 MHz *1 1 MHz 850 kHz 500 kHz

16 MHz *1 2 MHz 1.25 MHz 500 kHz

*1: External clock only

389


24.2 Example of Serial Programming Connection (User Power Supply Used)

Figure 24.2-1 "Example of Serial Programming Connection for MB90F438L(S)/F439(S) Single-chip Modes (User Power Supply Used)"shows an example of serial programming connection when the microcomputer power voltage is supplied from the user power supply. The values 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer.Serial reprogramming mode: MD2, MD1, MD0 = 110

■ Example of Serial Programming Connection (User Power Supply Used)

Figure 24.2-1 Example of Serial Programming Connection for MB90F438L(S)/F439(S) Single-chip Modes (User Power Supply Used)

TAUX3

TMODE

TAUX

TICS

TRES

TTXDTRXD TCK

GND

DX10-28S

(19)

(12)

(23)

(10)

(5)

(13)(27)(6)

(7,8,14,15,21, 221, 28)

MB90F438L(S)/F439(S)

MD2

MD1

MD0X0

X1

P00

HST

RST

P01

C

SIN1SOT1SCK1

Vcc

Vss

DX10-28S

(2)TVcc

AF220/AF210/AF120/AF110 flash microcomputer programmer

User system

Connector

User

User

User

User power supply

Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open.

DX10-28S: Right-angle type

Pin 14 Pin 1

Pin 28 Pin 15

Connector (Hirose Electronics Ltd.) pin arrangement

390

24.2 Example of Serial Programming Connection (User Power Supply Used)

• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuitshown in the figure below is required in the same way that it is for P00. (The /TICS signal ofthe flash microcomputer programmer can be used to disconnect the user circuit during serialprogramming.)

• Connect the AF220/AF210/AF120/AF110 while the user power is off.

AF220/AF210/AF120/AF110/TICS pin


User

10K


391


24.3 Example of Serial Programming Connection (Power Supplied from the Programmer)

Figure 24.3-1 "Example of Serial Programming Connection for MB90F438L(S)/F439(S) Single-chip Modes (Power Supplied from the Programmer) "shows an example of serial programming connection when the microcomputer power voltage is supplied from the programmer. The values 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer.Serial reprogramming mode: MD2, MD1, MD0 = 110

■ Example of Serial Programming Connection (Power Supplied from the Programmer)

Figure 24.3-1 Example of Serial Programming Connection for MB90F438L(S)/F439(S) Single-chip Modes (Power Supplied from the Programmer)

TAUX3

TMODE

TAUX

TICS

TRES

TTXDTRXD TCKTVcc Vcc

TVPP1

GND

DX10-28S

MD2

MD1

MD0X0

X1

P00

HST

RST

P01

C

SIN1SOT1SCK1

Vcc

Vss

DX10-28S


User system

Connector

User

User

User

Pins 4, 9, 11, 17, 18, 20, 24, 25, and 26 are open.


Pin 14 Pin 1

Pin 28 Pin 15


(19)

(12)

(23)

(10)

(5)

(13)(27)(6)(2)(3)(16)

(7, 8,14,15,21, 221, 28)

MB90F438L(S)/F439(S)

392

24.3 Example of Serial Programming Connection (Power Supplied from the Programmer)

• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuitshown in the figure below is required in the same way that it is for P00. (The /TICS signal ofthe flash microcomputer programmer can be used to disconnect the user circuit during serialprogramming.)


• When the programming power is supplied from the AF220/AF210/AF120/AF110, be carefulnot to short-circuit the user power supply.



User

10K


393


24.4 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)

Figure 24.4-1 "Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)" is an example of the minimum connection to the flash microcomputer programmer when the user power supply is used.Serial reprogramming mode: MD2, MD1, MD0 = 110

■ Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)

For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputerprogrammer need not be connected if the pins are set as described below.

Figure 24.4-1 Example of Minimum Connection to the MB90F438L(S)/F439(S) Flash Microcomputer Programmer (User Power Supply Used)

TRESTTXDTRXD TCKTVcc

GND

MD2

MD1

MD0

X0

X1

P00

HST

RST

P01

C

SIN1SOT1SCK1

Vcc

Vss

DX10-28S

DX10-28S


User system

Connector



Pin 14 Pin 1

Pin 28 Pin 15

1 for serial reprogrammingUser circuit

User circuit

User power supply

Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25, and 26 are open.

(5)(13)(27)(6)(2)

(7,8,14,15,21,22,1,28)

MB90F438L(S)/F439(S)

1 for serialreprogramming




394

24.4 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)

• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuitshown in the figure below is required. (The /TICS signal of the flash microcomputerprogrammer can be used to disconnect the user circuit during serial programming.)




User

10K


395


24.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer)

Figure 24.5-1 "Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer)" is an example of the minimum connection to the flash microcomputer programmer when power is supplied from the programmer.Serial reprogramming mode: MD2, MD1, MD0 = 110

■ Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer)

For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputerprogrammer need not be connected if the pins are set as described below.

Figure 24.5-1 Example of Minimum Connection to the MB90F438L(S)/F439(S) Flash Microcomputer Programmer (Power Supplied from the Programmer)

TRESTTXDTRXD TCKTVcc

VuTVPP1

GND

MD2

MD1

MD0

X0

X1

P00

HST

RST

P01

C

SIN1SOT1SCK1

Vcc

Vss

DX10-28S

DX10-28S


User system

1 for serial reprogrammingUser circuit

User circuit

Connector

Pins 4, 9, 10, 11, 12, 17, 18, 19, 20, 23, 24, 25, and 26 are open.


Pin 14 Pin 1

Pin 28 Pin 15


(5)(13)(27)(6)(2)(3)(16)

(7,8,14,15,21,22,1,28)

MB90F438L(S)/F439(S)





396

24.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer)

• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuitshown in the figure below is required. (The /TICS signal of the flash microcomputerprogrammer can be used to disconnect the user circuit during serial programming.)


• When the programming power is supplied from the AF220/AF210/AF120/AF110, be carefulnot to short-circuit the user power supply.



User

10K


397


398

APPENDIX

The appendix provides I/O maps and outlines instructions.

APPENDIX A "I/O Maps"

APPENDIX B "Instructions"

399

APPENDIX A I/O Maps

APPENDIX A I/O Maps

Table A-1 "I/O Map" lists addresses to be assigned to the registers in the peripheral blocks.

■ I/O Maps

Table A-1 I/O Map

Address RegisterAbbrevia

-tionAccess Resource Initial value

000000H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB










00000AH Port A data register PDRA R/W Port A -------XB

00000BH to 00000FH

Reserved

000010H Port 0 direction register DDR0 R/W Port 0 00000000B









000019H Port 9 direction register DDR9 R/W Port 9 --000000B

00001AH Port A direction register DDRA R/W Port A -------0B

400

APPENDIX A I/O Maps

00001BH Analog input enable register ADER R/W Port 6, A/D 11111111B

00001CH Port 0 pull-up control register PUCR0 R/W Port 0 00000000B

00001DH Port 1 pull-up control register PUCR1 R/W Port 1 00000000B

00001EH Port 2 pull-up control register PUCR2 R/W Port 2 00000000B

00001FH Port 3 pull-up control register PUCR3 R/W Port 3 00000000B

000020H Serial mode control register 0 UMC0 R/W

UART0

00000100B

000021H Serial status register 0 USR0 R/W 00010000B

000022HSerial input data register 0/serial output data register 0

UIDR0/UODR0

R/W XXXXXXXXB

000023H Rate and data register URD0 R/W 0000000XB

000024H Serial mode register 1 SMR1 R/W

UART1

00000000B

000025H Serial control register 1 SCR1 R/W 00000100B

000026HSerial input data register 1/serial output data register 1

SIDR1/SODR1

R/W XXXXXXXXB

000027H Serial status register SSR1 R/W 00001-00B

000028H UART1 prescaler control register U1CDCR R/W 0---1111B

000029H Serial edge select register 1 SES1 R/W ------0B

00002AH Use prohibited

00002BH Serial I/O prescaler SCDCR R/W Serial I/O 0---1111B

00002CHSerial mode control register SMCS R/W

----0000B

00002DH 00000010B

00002EH Serial data register SDR R/W XXXXXXXXB

00002FH Serial edge select register 2 SES2 R/W -------0B

000030H External Interrupt enable register ENIR R/W

DTP/external interrupt

00000000B

000031H External Interrupt request register EIRR R/W XXXXXXXXB

000032HExternal interrupt level register ELVR R/W

00000000B

000033H 00000000B

000034H A/D control status register 0 ADCS0 R/W

A/D converter

00000000B

000035H A/D control status register 1 ADCS1 R/W 00000000B

000036H A/D data register 0 ADCR0 R XXXXXXXXB

000037H A/D data register 1 ADCR1 R/W 00001-XXB

Table A-1 I/O Map (Continued)



401

APPENDIX A I/O Maps

000038HPPG0 operation mode control register

PPGC0 R/W

16-bit PPG timer 0/1

0-000--1B


PPGC1 R/W 0-000001B

00003AH PPG0/1 clock selection register PPG01 R/W 000000--B

00003BH Reserved

00003CHPPG2 operation mode control register

PPGC2 R/W


0-000--1B

00003DHPPG3 operation mode control register

PPGC3 R/W 0-000001B

00003EH PPG2/3 clock selection register PPG23 R/W 000000--B

00003FH Use prohibited


PPGC4 R/W


0-000--1B


PPGC5 R/W 0-000001B

000042H PPG4/5 clock selection register PPG45 R/W 000000--B

000043H Use prohibited


PPGC6 R/W


0-000--1B


PPGC7 R/W 0-000001B

000046H PPG6/7 clock selection register PPG67 R/W 000000--B

000047H to 00004BH

Use prohibited

00004CHInput capture control status register 0/1

ICS01 R/WInput capture

0/100000000B

00004DHInput capture control status register 2/3


2/300000000B

00004EHInput capture control status register 4/5


4/500000000B

00004FHInput capture control status register 6/7

ICS67 R/W Input capture 6/7

00000000B

000050HTimer control status register 0 TMCSR0 R/W


00000000B

000051H ----0000B

000052H Timer register 0/timer reload register 0

TMR0/TMRLR0

R/WXXXXXXXXB

000053H XXXXXXXXB




402

APPENDIX A I/O Maps

000054HTimer control status register 1 TMCSR1 R/W


00000000B

000055H ----0000B

000056H Timer register 1/timer reload register 1

TMR1/TMRLR1

R/WXXXXXXXXB

000057H XXXXXXXXB

000058H Output compare control register 0 OCS0R/W

Output compare 0/1

0000--00B

000059H Output compare control register 1 OCS1 ---00000B

00005AH Output compare control register 2 OCS2R/W

Output compare 2/3

0000--00B

00005BH Output compare control register 3 OCS3 ---00000B

00005CH to 00006BH

Use prohibited

00006CHTimer counter data register TCDT R/W

I/O timer

00000000B

00006DH 00000000B

00006EHTimer counter control status register

TCCS R/W 00000000B

00006FHROM mirror function selection register

ROMM R/W

ROM mirror function selection module

-------1B

000070H to 00007FH

Reserved

000080H to 00008FH

Reserved

000090H to 00009DH

Use prohibited

00009EHProgram address detection control status register

PACSR R/W

Address match

detection function

00000000B

00009FH Delayed interrupt/release register DIRR R/W

Delayed interrupt

generation module

-------0B

0000A0H Low-power mode control register LPMCR R/W Low-power control circuit

00011000B

0000A1H Clock selection register CKSCR R/W 11111100B

0000A2H to 0000A4H

Use prohibited




403

APPENDIX A I/O Maps

0000A5HAutomatic ready function selection register

ARSR

WExternal memory access

0011--00B

0000A6HExternal address output control register

HACR 00000000B

0000A7HBus control signal selection register

ECSR 0000000-B

0000A8H Watch-dog timer control register WDTC R/WWatch-dog

timerXXXXX111B

0000A9H Time base timer control register TBTC R/WTime base

timer1--00100B

0000AAH Watch timer control register WTC R/W Watch timer 1X000000B

0000ABH to 0000ADH

Use prohibited

0000AEH

Flash memory control status register (flash only, otherwise reserved)

FMCS R/W Flash memory 000X0000B

0000AFH Use prohibited

0000B0H Interrupt control register 00 ICR00 R/W


00000111B

0000B1H Interrupt control register 01 ICR01 R/W 00000111B









0000BAH Interrupt control register 10 ICR10 R/W 00000111B

0000BBH Interrupt control register 11 ICR11 R/W 00000111B

0000BCH Interrupt control register 12 ICR12 R/W 00000111B

0000BDH Interrupt control register 13 ICR13 R/W 00000111B

0000BEH Interrupt control register 14 ICR14 R/W 00000111B

0000BFH Interrupt control register 15 ICR15 R/W 00000111B

0000C0H to 0000FFH

External area




404

APPENDIX A I/O Maps

001FF0H

Program address detection register 0

PADR0

R/W

Address match

detection function

XXXXXXXXB

001FF1H R/W XXXXXXXXB


001FF3H

Program address detection register 1

PADR1

R/W XXXXXXXXB



• In the Initial value column, "0" indicates that the initial value is 0, "1" indicates that the initial value is 1, X indicates that the initial value is undefined, and "-" indicates that the initial value is undefined (no value).

Note:For bits to which values can be written, the values initialized by a reset are those written in the Initial value column. These values are not read values.The LPMCR/CKSCR/WDTC bits are not always be initialized by a reset. Whether they are initialized depends on the reset type. The values initialized by a reset are listed in the Initial value column for these registers.

• Free-running timer 2 is used for compare registers 0 to 3, and free-running timer 1 is used for 4 to 7. Free-running timer 1 is also used for the input capture.


Address Register Abbrevia-tion

Access Resource Initial value

3900H Reload register L PRLL0 R/W


XXXXXXXXB

3901H Reload register H PRLH0 R/W XXXXXXXXB

3902H Reload register L PRLL1 R/W XXXXXXXXB




XXXXXXXXB


3906H Reload register L PRLL3 R/W XXXXXXXXB




XXXXXXXXB


390AH Reload register L PRLL5 R/W XXXXXXXXB

390BH Reload register H PRLH5 R/W XXXXXXXXB

390CH Reload register L PRLL6 R/W


XXXXXXXXB

390DH Reload register H PRLH6 R/W XXXXXXXXB

390EH Reload register L PRLL7 R/W XXXXXXXXB

390FH Reload register H PRLH7 R/W XXXXXXXXB




405

APPENDIX A I/O Maps

3910H to 3917H

Reserved

3918H Input capture register 0 IPCP0 R

Input capture 0/1

XXXXXXXXB

3919H Input capture register 0 IPCP0 R XXXXXXXXB

391AH Input capture register 1 IPCP1 R XXXXXXXXB

391BH Input capture register 1 IPCP1 R XXXXXXXXB

391CH Input capture register 2 IPCP2 R

Input capture 2/3

XXXXXXXXB

391DH Input capture register 2 IPCP2 R XXXXXXXXB

391EH Input capture register 3 IPCP3 R XXXXXXXXB

391FH Input capture register 3 IPCP3 R XXXXXXXXB


Input capture 4/5

XXXXXXXXB





Input capture 6/7

XXXXXXXXB




3928H Output compare register 0 OCCP0 R/W

Output compare 0/1

XXXXXXXXB

3929H Output compare register 0 OCCP0 R/W XXXXXXXXB

392AH Output compare register 1 OCCP1 R/W XXXXXXXXB

392BH Output compare register 1 OCCP1 R/W XXXXXXXXB

392CH Output compare register 2 OCCP2 R/W

Output compare 2/3

XXXXXXXXB

392DH Output compare register 2 OCCP2 R/W XXXXXXXXB

392EH Output compare register 3 OCCP3 R/W XXXXXXXXB

392FH Output compare register 3 OCCP3 R/W XXXXXXXXB

3930H to 39FFH

Reserved

3A00H to 3AFFH

Reserved

3B00H to 3BFFH

Reserved




406

APPENDIX A I/O Maps

3C00H to 3CFFH

Reserved

3D00H to 3DFFH

Reserved

3E00H to 3FFFH

Reserved

• Explanation of write and readR/W: Both read and write enabledR: Only read enabledW: Only write enabled

• Explanation of initial values0: The initial value of this bit is 0.1: The initial value of this bit is 1.X: The initial value of this bit is undefined.-: This bit is not used, and the initial value is undefined.

Note:Do not access the reserved area in I/O map for a write. If the reserved area is read, the value is undefined.




407

APPENDIX B Instructions


APPENDIX B describes the instructions used by the F2MC-16LX.

B.1 Instruction Types

B.2 Addressing

B.3 Direct Addressing

B.4 Indirect Addressing

B.5 Execution Cycle Count

B.6 Effective address field

B.7 How to Read the Instruction List

B.8 F2MC-16LX Instruction List

B.9 Instruction Map

Code: CM44-00202-1E

408

Changed the entire part of "APPENDIX B Instructions"


B.1 Instruction Types

The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself.

■ Instruction Types

The F2MC-16LX supports the following 351 types of instructions:

• 41 transfer instructions (byte)

• 38 transfer instructions (word or long word)

• 42 addition/subtraction instructions (byte, word, or long word)

• 12 increment/decrement instructions (byte, word, or long word)

• 11 comparison instructions (byte, word, or long word)

• 11 unsigned multiplication/division instructions (word or long word)

• 11 signed multiplication/division instructions (word or long word)

• 39 logic instructions (byte or word)

• 6 logic instructions (long word)

• 6 sign inversion instructions (byte or word)

• 1 normalization instruction (long word)

• 18 shift instructions (byte, word, or long word)

• 50 branch instructions

• 6 accumulator operation instructions (byte or word)

• 28 other control instructions (byte, word, or long word)

• 21 bit operation instructions

• 10 string instructions

409


B.2 Addressing

With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing.

■ Addressing

The F2MC-16LX supports the following 23 types of addressing:

• Immediate (#imm)

• Register direct

• Direct branch address (addr16)

• Physical direct branch address (addr24)

• I/O direct (io)

• Abbreviated direct address (dir)

• Direct address (addr16)

• I/O direct bit address (io:bp)

• Abbreviated direct bit address (dir:bp)

• Direct bit address (addr16:bp)

• Vector address (#vct)

• Register indirect (@RWj j = 0 to 3)

• Register indirect with post increment (@RWj+ j = 0 to 3)

• Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)

• Long register indirect with displacement (@RLi + disp8 i = 0 to 3)

• Program counter indirect with displacement (@PC + disp16)

• Register indirect with base index (@RW0 + RW7, @RW1 + RW7)

• Program counter relative branch address (rel)

• Register list (rlst)

• Accumulator indirect (@A)

• Accumulator indirect branch address (@A)

• Indirectly-specified branch address (@ear)

• Indirectly-specified branch address (@eam)

410


■ Effective Address FieldTable B.2-1 lists the address formats specified by the effective address field.

Table B.2-1 Effective Address Field

Code Representation Address format Default bank

00 R0 RW0 RL0

Register direct: Individual parts correspond to the byte, word, and long word types in order from the left.

None

01 R1 RW1 (RL0)

02 R2 RW2 RL1

03 R3 RW3 (RL1)

04 R4 RW4 RL2

05 R5 RW5 (RL2)

06 R6 RW6 RL3

07 R7 RW7 (RL3)

08 @RW0

Register indirect

DTB

09 @RW1 DTB

0A @RW2 ADB

0B @RW3 SPB

0C @RW0+

Register indirect with post increment

DTB

0D @RW1+ DTB

0E @RW2+ ADB

0F @RW3+ SPB

10 @RW0+disp8

Register indirect with 8-bit displacement

DTB

11 @RW1+disp8 DTB

12 @RW2+disp8 ADB

13 @RW3+disp8 SPB

14 @RW4+disp8


DTB

15 @RW5+disp8 DTB

16 @RW6+disp8 ADB

17 @RW7+disp8 SPB

18 @RW0+disp16


DTB

19 @RW1+disp16 DTB

1A @RW2+disp16 ADB

1B @RW3+disp16 SPB

1C @RW0+RW7 Register indirect with index DTB

1D @RW1+RW7 Register indirect with index DTB

1E @PC+disp16 PC indirect with 16-bit displacement PCB

1F addr16 Direct address DTB

411


B.3 Direct Addressing

An operand value, register, or address is specified explicitly in direct addressing mode.

■ Direct Addressing

● Immediate addressing (#imm)

Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).

Figure B.3-1 Example of Immediate Addressing (#imm)

● Register direct addressing

Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2

shows an example of register direct addressing.

MOVW A, #01212H (This instruction stores the operand value in A.)

Before execution A 2 2 3 3 4 4 5 5

After execution A 4 4 5 5 1 2 1 2 (Some instructions transfer AL to AH.)

Table B.3-1 Direct Addressing Registers

General-purpose register Byte R0, R1, R2, R3, R4, R5, R6, R7

Word RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

Long word RL0, RL1, RL2, RL3

Special-purpose register Accumulator A, AL

Pointer SP *

Bank PCB, DTB, USB, SSB, ADB

Page DPR

Control PS, CCR, RP, ILM

*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on the value of the S flag bit in the condition code register (CCR). For branch instructions, the program counter (PC) is not specified in an instruction operand but is specified implicitly.

412


Figure B.3-2 Example of Register Direct Addressing

● Direct branch addressing (addr16)

Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which

indicates the branch destination in the logical address space. Direct branch addressing is used for an

unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are

specified by the program counter bank register (PCB).

Figure B.3-3 Example of Direct Branch Addressing (addr16)

MOV R0, A (This instruction transfers the eight low-order bits of A to the general-purpose register R0.)

Before execution A 0 7 1 6 2 5 3 4 Memory space

R0 ? ?

After execution A 0 7 1 6 2 5 6 4 Memory space

R0 3 4

JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing in a bank.)

Before execution PC 3 C 2 0 PCB 4 F Memory space

4F3B20H Next instruction

4F3C20H 6 2 JMP 3B20HAfter execution PC 3 B 2 0 PCB 4 F 4F3C21H 2 0

4F3C22H 3 B

413


● Physical direct branch addressing (addr24)

Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical

direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.

Figure B.3-4 Example of Direct Branch Addressing (addr24)

● I/O direct addressing (io)

Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the

physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)

and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an

instruction using I/O direct addressing.

Figure B.3-5 Example of I/O Direct Addressing (io)

JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.)


333B20H Next instruction

4F3C20H 6 3 JMPP 333B20HAfter execution PC 3 B 2 0 PCB 3 3 4F3C21H 2 0

4F3C22H 3 B

4F3C23H 3 3

MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it in A.)


0000C0H E E

0000C1H F F

After execution A 2 5 3 4 F F E E

414


● Abbreviated direct addressing (dir)

Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are

specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register

(DTB).

Figure B.3-6 Example of Abbreviated Direct Addressing (dir)

● Direct addressing (addr16)

Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are

specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for

this mode of addressing.

Figure B.3-7 Example of Direct Addressing (addr16)

MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.)


DPR 6 6 DTB 7 7 776620H ? ?

After execution A 4 4 5 5 1 2 1 2 Memory space

DPR 6 6 DTB 7 7 776620H 1 2

MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)

Before execution A 2 0 2 0 A A B B DTB 5 5 Memory space

553B21H 0 1

553B20H 2 3

After execution A A A B B 0 1 2 3 DTB 5 5

415


● I/O direct bit addressing (io:bp)

Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",

where the larger number indicates the most significant bit (MSB) and the lower number indicates the least

significant bit (LSB).

Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp)

● Abbreviated direct bit addressing (dir:bp)

Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are

specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register

(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit

(MSB) and the lower number indicates the least significant bit (LSB).

Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)

● Direct bit addressing (addr16:bp)

Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register

(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit

(MSB) and the lower number indicates the least significant bit (LSB).

Figure B.3-10 Example of Direct Bit Addressing (addr16:bp)

SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.)

Memory space

Before execution 0000C1H 0 0

Memory space

After execution 0000C1H 0 1

SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.)

Memory space

Before execution DTB 5 5 DPR 6 6 556610H 0 0

Memory space

After execution DTB 5 5 DPR 6 6 556610H 0 1

SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)

Memory space

Before execution DTB 5 5 552222H 0 0

Memory space

After execution DTB 5 5 552222H 0 1

416


● Vector Addressing (#vct)

Specify vector data in an operand to indicate the branch destination address. There are two sizes for vectornumbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.

Figure B.3-11 Example of Vector Addressing (#vct)

Note:

When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area ofINT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2).

CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.)

Before execution PC 0 0 0 0 Memory space

PCB F F FFC000H E F CALLV #15

After execution PC D 0 0 0FFFFE0H 0 0

PCB F F FFFFE1H D 0

Table B.3-2 CALLV Vector List

Instruction Vector address L Vector address H

CALLV #0 XXFFFEH XXFFFFH

CALLV #1 XXFFFCH XXFFFDH

CALLV #2 XXFFFAH XXFFFBH

CALLV #3 XXFFF8H XXFFF9H





CALLV #8 XXFFEEH XXFFEFH

CALLV #9 XXFFECH XXFFEDH

CALLV #10 XXFFEAH XXFFEBH

CALLV #11 XXFFE8H XXFFE9H





Note: A PCB register value is set in XX.

417


B.4 Indirect Addressing

In indirect addressing mode, an address is specified indirectly by the address data of an operand.

■ Indirect Addressing

● Register indirect addressing (@RWj j = 0 to 3)

Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to

23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register

(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when

RW2 is used.

Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)

● Register indirect addressing with post increment (@RWj+ j = 0 to 3)

Memory is accessed using the contents of general-purpose register RWj as an address. After operand

operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).

Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system

stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank

register (ADB) when RW2 is used.

If the post increment results in the address of the register that specifies the increment, the incremented

value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to

writing by an instruction and, therefore, the register that would be incremented becomes write data.

MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.)


Memory space

RW1 D 3 0 F DTB 7 8 78D30FH E E

78D310H F F


RW1 D 3 0 F DTB 7 8

418


Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)

● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)

Memory is accessed using the address obtained by adding an offset to the contents of general-purpose

register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric

values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or

RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is

used, or additional data bank register (ADB) when RW2 or RW6 is used.

Figure B.4-3 Example of Register Indirect Addressing with Offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)

MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.)


Memory space

RW1 D 3 0 F DTB 7 8 78D30FH E E

78D310H F F


RW1 D 3 1 1 DTB 7 8

MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an offset and stores it in A.)


(+10H) Memory space

RW1 D 3 0 F DTB 7 8 78D31FH E E

78D320H F F


RW1 D 3 0 F DTB 7 8

419


● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)

Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the

contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.

Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)

● Program counter indirect addressing with offset (@PC + disp16)

Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one

word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the

operand address of each of the following instructions is not deemed to be (next instruction address +

disp16):

• DBNZ eam, rel

• DWBNZ eam, rel

• CBNE eam, #imm8, rel

• CWBNE eam, #imm16, rel

• MOV eam, #imm8

• MOVW eam, #imm16

Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)

MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.)


(+25H) Memory space

RL2 F 3 8 2 4 B 0 2 824B27H E E

824B28H F F


RL2 F 3 8 2 4 B 0 2

MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with an offset and stores it in A.)


PCB C 5 PC 4 5 5 6 C54556H 7 3

MOVWA, @PC+20H

C54557H 9 E

C54558H 2 0

C54559H 0 0

After execution A 2 5 3 4 F F E E +4 C5455AH

.

.

.PCB C 5 PC 4 5 5 A +20H

C5457AH E E

C5457BH F F

420


● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)

Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general-

purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).

Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)

MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.)


RW1 D 3 0 F + 78D410H E EDTB 7 8

WR7 0 1 0 1 78D411H F F


RW1 D 3 0 F DTB 7 8

WR7 0 1 0 1

421


● Program counter relative branch addressing (rel)

The address of the branch destination is a value determined by adding an 8-bit offset to the program

counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is

not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte

bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to

23 are indicated by the program counter bank register (PCB).

Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)

● Register list (rlst)

Specify a register to be pushed onto or popped from a stack.

Figure B.4-8 Configuration of the Register List

BRA 10H (This instruction causes an unconditional relative branch.)


4F3C32H Next instruction

4F3C21H 1 0

After execution PC 3 C 3 2 PCB 4 F 4F3C20H 6 0 BRA 10H

MSB LSB

RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0

A register is selected when the corresponding bit is 1 and deselected when the bit is 0.

422


Figure B.4-9 Example of Register List (rlist)

● Accumulator indirect addressing (@A)

Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the

accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).

Figure B.4-10 Example of Accumulator Indirect Addressing (@A)

POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.)

SP 3 4 F A SP 3 4 F E

RW0 × × × × RW0 0 2 0 1

RW1 × × × × RW1 × × × ×

RW2 × × × × RW2 × × × ×

RW3 × × × × RW3 × × × ×

RW4 × × × × RW4 0 4 0 3

RW5 × × × × RW5 × × × ×

RW6 × × × × RW6 × × × ×

RW7 × × × × RW7 × × × ×

Memory space Memory space

SP 0 1 34FAH 0 1 34FAH

0 2 34FBH 0 2 34FBH

0 3 34FCH 0 3 34FCH

0 4 34FDH 0 4 34FDH

34FEH SP 34FEH

Before execution After execution

MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)


DTB B B BB2534H E E

BB2535H F F


DTB B B

423


● Accumulator indirect branch addressing (@A)

The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the

accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are

specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,

address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for

unconditional branch instructions.

Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A)

● Indirect specification branch addressing (@ear)

The address of the branch destination is the word data at the address indicated by ear.

Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear)

JMP @A (This instruction causes an unconditional branch by accumulator indirect branch addressing.)


A 6 6 7 7 3 B 2 0 4F3B20H Next instruction

4F3C20H 6 1 JMP @A

After execution PC 3 B 2 0 PCB 4 F

A 6 6 7 7 3 B 2 0

JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.)


RW0 7 F 4 8 DTB 2 1 217F48H 2 0

217F49H 3 B

4F3B20H Next instruction

After execution PC 3 B 2 0 PCB 4 F 4F3C20H 7 3 JMP @@RW0

4F3C21H 0 8

RW0 7 F 4 8 DTB 2 1

424


● Indirect specification branch addressing (@eam)

The address of the branch destination is the word data at the address indicated by eam.

Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam)

JMP @RW0 (This instruction causes an unconditional branch by register indirectaddressing.)


RW0 3 B 2 0 4F3B20H Next instruction

4F3C20H 7 3 JMP @RW0

After execution PC 3 B 2 0 PCB 4 F 4F3C21H 0 0

RW0 3 B 2 0

425


B.5 Execution Cycle Count

The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch.

■ Execution Cycle CountThe number of cycles required for instruction execution (execution cycle count) is obtained by adding the

number of cycles required for each instruction, "correction value" determined by the condition, and the

number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal

ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.

Therefore, intervening in data access increases the execution cycle count.

Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the

program fetches every byte of an instruction being executed. Therefore, intervening in data access increases

the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,

internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the

cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.

Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add

the "access count x cycle count for the halt" as a correction value to the normal execution count.

426


■ Calculating the Execution Cycle Count

Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data.

Table B.5-1 Execution Cycle Counts in Each Addressing Mode

Code Operand(a) *

Register access count in each addressing modeExecution cycle count in

each addressing mode

00|

07

RiRwiRLi

See the instruction list. See the instruction list.

08|

0B@RWj 2 1

0C|

0F@RWj+ 4 2

10|

17@RWi+disp8 2 1

18|

1B@RWi+disp16 2 1

1C1D1E1F

@RW0+RW7@RW1+RW7@PC+disp16addr16

4421

2200

*: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List".

427


Note:

When an external data bus is used, the cycle counts during which an instruction is made to wait byready input or automatic ready must also be added.

Notes:

• When an external data bus is used, the cycle counts during which an instruction is made to waitby ready input or automatic ready must also be added.

• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use thecorrection values to calculate the worst case.

Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles

Operand(b) byte * (c) word * (d) long *

Cycle count

Access count

Cycle count

Access count

Cycle count

Access count

Internal register +0 1 +0 1 +0 2

Internal memoryEven address

+0 1 +0 1 +0 2

Internal memory Odd address

+0 1 +2 2 +4 4

External data bus16-bit even address

+1 1 +1 1 +2 2

External data bus16-bit odd address

+1 1 +4 2 +8 4

External data bus8-bits

+1 1 +4 2 +8 4

*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List".

Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles

Instruction Byte boundary Word boundary

Internal memory - +2

External data bus 16-bits - +3

External data bus 8-bits +3 -

428


B.6 Effective address field

Table B.6-1 shows the effective address field.

■ Effective Address Field

Table B.6-1 Effective Address Field

Code Representation Address formatByte count of

extended address part *

00 R0 RW0 RL0

Register direct: Individual parts correspond to the byte, word, and long word types in order from the left.

-

01 R1 RW1 (RL0)

02 R2 RW2 RL1

03 R3 RW3 (RL1)

04 R4 RW4 RL2

05 R5 RW5 (RL2)

06 R6 RW6 RL3

07 R7 RW7 (RL3)

08 @RW0

Register indirect 009 @RW1

0A @RW2

0B @RW3

0C @RW0+

Register indirect with post increment 00D @RW1+

0E @RW2+

0F @RW3+

10 @RW0+disp8

Register indirect with 8-bit displacement 1

11 @RW1+disp8

12 @RW2+disp8

13 @RW3+disp8

14 @RW4+disp8

15 @RW5+disp8

16 @RW6+disp8

17 @RW7+disp8

18 @RW0+disp16

Register indirect with 16-bit displacement 219 @RW1+disp16

1A @RW2+disp16

1B @RW3+disp16

1C @RW0+RW7 Register indirect with index 0

1D @RW1+RW7 Register indirect with index 0

1E @PC+disp16 PC indirect with 16-bit displacement 2

1F addr16 Direct address 2

*1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX Instruction List".

429


B.7 How to Read the Instruction List

Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table B.7-2 describes the symbols used in the same list.

■ Description of Instruction Presentation Items and Symbols

Table B.7-1 Description of Items in the Instruction List (1/2)

Item Description

MnemonicUppercase, symbol: Represented as is in the assembler.Lowercase: Rewritten in the assembler.Number of following lowercase: Indicates bit length in the instruction.

# Indicates the number of bytes.

~Indicates the number of cycles.See Table B.2-1 for the alphabetical letters in items.

RG

Indicates the number of times a register access is performed during instruction execution.The number is used to calculate the correction value for CPU intermittent operation.

B

Indicates the correction value used to calculate the actual number of cycles during instruction execution.The actual number of cycles during instruction execution can be determined by adding the value in the ~ column to this value.

Operation Indicates the instruction operation.

LH

Indicates the special operation for bit15 to bit08 of the accumulator.Z: Transfers 0.X: Transfers after sign extension.-: No transfer

AH

Indicates the special operation for the 16 high-order bits of the accumulator.*: Transfers from AL to AH.-: No transferZ: Transfers 00 to AH.X: Transfers 00H or FFH to AH after AL sign extension.

I Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry).*: Changes upon instruction execution.-: No changeS: Set upon instruction execution.R: Reset upon instruction execution.

S

T

N

Z

V

C

430


RMW

Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory).*: Read Modify Write instruction-: Not Read Modify Write instructionNote:

Cannot be used for an address that has different meanings between read and write operations.

Table B.7-2 Explanation on Symbols in the Instruction List (1/2)

Symbol Explanation

A

The bit length used varies depending on the 32-bit accumulator instruction.Byte: Low-order 8 bits of byte ALWord: 16 bits of word ALLong word: 32 bits of AL and AH

AH 16 high-order bits of A

AL 16 low-order bits of A

SP Stack pointer (USP or SSP)

PC Program counter

PCB program counter bank register

DTB Data bank register

ADB Additional data bank register

SSB System stack bank register

USB User stack bank register

SPB Current stack bank register (SSB or USB)

DPR Direct page register

brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB

brg2 DTB, ADB, SSB, USB, DPR, SPB

Ri R0, R1, R2, R3, R4, R5, R6, R7

RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RWj RW0, RW1, RW2, RW3

RLi RL0, RL1, RL2, RL3

dir Abbreviated direct addressing

addr16 Direct addressing

addr24 Physical direct addressing

ad24 0-15 Bit0 to bit15 of addr24

Table B.7-1 Description of Items in the Instruction List (1/2)

Item Description

431


ad24 16-23 Bit16 to bit23 of addr24

io I/O area (000000H to 0000FFH)

#imm4 4-bit immediate data




ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data

disp8 8-bit displacement

disp16 16-bit displacement

bp Bit offset

vct4 Vector number (0 to 15)

vct8 Vector number (0 to 255)

( ) b Bit address

rel PC relative branch

ear Effective addressing (code 00 to 07)

eam Effective addressing (code 08 to 1F)

rlst Register list

Table B.7-2 Explanation on Symbols in the Instruction List (1/2)

Symbol Explanation

432


B.8 F2MC-16LX Instruction List

Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX.

■ F2MC-16LX Instruction List

Note:

See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.

Table B.8-1 41 Transfer Instructions (Byte)

Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW

MOV A,dir 2 3 0 (b) byte (A) ← (dir) Z * - - - * * - - -MOV A,addr16 3 4 0 (b) byte (A) ← (addr16) Z * - - - * * - - -MOV A,Ri 1 2 1 0 byte (A) ← (Ri) Z * - - - * * - - -MOV A,ear 2 2 1 0 byte (A) ← (ear) Z * - - - * * - - -MOV A,eam 2+ 3 + (a) 0 (b) byte (A) ← (eam) Z * - - - * * - - -MOV A,io 2 3 0 (b) byte (A) ← (io) Z * - - - * * - - -MOV A,#imm8 2 2 0 0 byte (A) ← imm8 Z * - - - * * - - -MOV A,@A 2 3 0 (b) byte (A) ← ((A)) Z - - - - * * - - -MOV A,@RLi+disp8 3 10 2 (b) byte (A) ← ((RLi)+disp8) Z * - - - * * - - -MOVN A,#imm4 1 1 0 0 byte (A) ← imm4 Z * - - - R * - - -MOVX A,dir 2 3 0 (b) byte (A) ← (dir) X * - - - * * - - -MOVX A,addr16 3 4 0 (b) byte (A) ← (addr16) X * - - - * * - - -MOVX A,Ri 2 2 1 0 byte (A) ← (Ri) X * - - - * * - - -MOVX A,ear 2 2 1 0 byte (A) ← (ear) X * - - - * * - - -MOVX A,eam 2+ 3 + (a) 0 (b) byte (A) ← (eam) X * - - - * * - - -MOVX A,io 2 3 0 (b) byte (A) ← (io) X * - - - * * - - -MOVX A,#imm8 2 2 0 0 byte (A) ← imm8 X * - - - * * - - -MOVX A,@A 2 3 0 (b) byte (A) ← ((A)) X - - - - * * - - -MOVX A,@RWi+disp8 2 5 1 (b) byte (A) ← ((RWi)+disp8) X * - - - * * - - -MOVX A,@RLi+disp8 3 10 2 (b) byte (A) ← ((RLi)+disp8) X * - - - * * - - -MOV dir,A 2 3 0 (b) byte (dir) ← (A) - - - - - * * - - -MOV addr16,A 3 4 0 (b) byte (addr16) ← (A) - - - - - * * - - -MOV Ri,A 1 2 1 0 byte (Ri) ← (A) - - - - - * * - - -MOV ear,A 2 2 1 0 byte (ear) ← (A) - - - - - * * - - -MOV eam,A 2+ 3 + (a) 0 (b) byte (eam) ← (A) - - - - - * * - - -MOV io,A 2 3 0 (b) byte (io) ← (A) - - - - - * * - - -MOV @RLi+disp8,A 3 10 2 (b) byte ((RLi)+disp8) ← (A) - - - - - * * - - -MOV Ri,ear 2 3 2 0 byte (Ri) ← (ear) - - - - - * * - - -MOV Ri,eam 2+ 4 + (a) 1 (b) byte (Ri) ← (eam) - - - - - * * - - -MOV ear,Ri 2 4 2 0 byte (ear) ← (Ri) - - - - - * * - - -MOV eam,Ri 2+ 5 + (a) 1 (b) byte (eam) ← (Ri) - - - - - * * - - -MOV Ri,#imm8 2 2 1 0 byte (Ri) ← imm8 - - - - - * * - - -MOV io,#imm8 3 5 0 (b) byte (io) ← imm8 - - - - - - - - - -MOV dir,#imm8 3 5 0 (b) byte (dir) ← imm8 - - - - - - - - - -MOV ear,#imm8 3 2 1 0 byte (ear) ← imm8 - - - - - * * - - -MOV eam,#imm8 3+ 4 + (a) 0 (b) byte (eam) ← imm8 - - - - - - - - - -MOV @AL,AH 2 3 0 (b) byte ((A)) ← (AH) - - - - - * * - - -XCH A,ear 2 4 2 0 byte (A) ↔ (ear) Z - - - - - - - - -XCH A,eam 2+ 5 + (a) 0 2 × (b) byte (A) ↔ (eam) Z - - - - - - - - -XCH Ri,ear 2 7 4 0 byte (Ri) ↔ (ear) - - - - - - - - - -XCH Ri,eam 2+ 9 + (a) 2 2 × (b) byte (Ri) ↔ (eam) - - - - - - - - - -

433


Note:

See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table.

Table B.8-2 38 Transfer Instructions (Word, Long Word)


MOVW A,dir 2 3 0 (c) word (A) ← (dir) - * - - - * * - - -MOVW A,addr16 3 4 0 (c) word (A) ← (addr16) - * - - - * * - - -MOVW A,SP 1 1 0 0 word (A) ← (SP) - * - - - * * - - -MOVW A,RWi 1 2 1 0 word (A) ← (RWi) - * - - - * * - - -MOVW A,ear 2 2 1 0 word (A) ← (ear) - * - - - * * - - -MOVW A,eam 2+ 3 + (a) 0 (c) word (A) ← (eam) - * - - - * * - - -MOVW A,io 2 3 0 (c) word (A) ← (io) - * - - - * * - - -MOVW A,@A 2 3 0 (c) word (A) ← ((A)) - - - - - * * - - -MOVW A,#imm16 3 2 0 0 word (A) ← imm16 - * - - - * * - - -MOVW A,@RWi+disp8 2 5 1 (c) word (A) ← ((RWi)+disp8) - * - - - * * - - -MOVW A,@RLi+disp8 3 10 2 (c) word (A) ← ((RLi)+disp8) - * - - - * * - - -MOVW dir,A 2 3 0 (c) word (dir) ← (A) - - - - - * * - - -MOVW addr16,A 3 4 0 (c) word (addr16) ← (A) - - - - - * * - - -MOVW SP,A 1 1 0 0 word (SP) ← (A) - - - - - * * - - -MOVW RWi,A 1 2 1 0 word (RWi) ← (A) - - - - - * * - - -MOVW ear,A 2 2 1 0 word (ear) ← (A) - - - - - * * - - -MOVW eam,A 2+ 3 + (a) 0 (c) word (eam) ← (A) - - - - - * * - - -MOVW io,A 2 3 0 (c) word (io) ← (A) - - - - - * * - - -MOVW @RWi+disp8,A 2 5 1 (c) word ((RWi)+disp8) ← (A) - - - - - * * - - -MOVW @RLi+disp8,A 3 10 2 (c) word ((RLi)+disp8) ← (A) - - - - - * * - - -MOVW RWi,ear 2 3 2 0 word (RWi) ← (ear) - - - - - * * - - -MOVW RWi,eam 2+ 4 + (a) 1 (c) word (RWi) ← (eam) - - - - - * * - - -MOVW ear,RWi 2 4 2 0 word (ear) ← (RWi) - - - - - * * - - -MOVW eam,RWi 2+ 5 + (a) 1 (c) word (eam) ← (RWi) - - - - - * * - - -MOVW RWi,#imm16 3 2 1 0 word (RWi) ← imm16 - - - - - * * - - -MOVW io,#imm16 4 5 0 (c) word (io) ← imm16 - - - - - - - - - -MOVW ear,#imm16 4 2 1 0 word (ear) ← imm16 - - - - - * * - - -MOVW eam,#imm16 4+ 4 + (a) 0 (c) word (eam) ← imm16 - - - - - - - - - -MOVW @AL,AH 2 3 0 (c) word ((A)) ← (AH) - - - - - * * - - -XCHW A,ear 2 4 2 0 word (A) ↔ (ear) - - - - - - - - - -XCHW A,eam 2+ 5 + (a) 0 2 × (c) word (A) ↔ (eam) - - - - - - - - - -XCHW RWi, ear 2 7 4 0 word (RWi) ↔ (ear) - - - - - - - - - -XCHW RWi, eam 2+ 9 + (a) 2 2 × (c) word (RWi) ↔ (eam) - - - - - - - - - -MOVL A,ear 2 4 2 0 long (A) ← (ear) - - - - - * * - - -MOVL A,eam 2+ 5 + (a) 0 (d) long (A) ← (eam) - - - - - * * - - -MOVL A,#imm32 5 3 0 0 long (A) ← imm32 - - - - - * * - - -MOVL ear,A 2 4 2 0 long (ear) ← (A) - - - - - * * - - -MOVL eam,A 2+ 5 + (a) 0 (d) long(eam) ← (A) - - - - - * * - - -

434


Note:

See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.

Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)


ADD A,#imm8 2 2 0 0 byte (A) ← (A) + imm8 Z - - - - * * * * -ADD A,dir 2 5 0 (b) byte (A) ← (A) + (dir) Z - - - - * * * * -ADD A,ear 2 3 1 0 byte (A) ← (A) + (ear) Z - - - - * * * * -ADD A,eam 2+ 4 + (a) 0 (b) byte (A) ← (A) + (eam) Z - - - - * * * * -ADD ear,A 2 3 2 0 byte (ear) ← (ear) + (A) - - - - - * * * * -ADD eam,A 2+ 5 + (a) 0 2 × (b) byte (eam) ← (eam) + (A) Z - - - - * * * * *ADDC A 1 2 0 0 byte (A) ← (AH) + (AL) + (C) Z - - - - * * * * -ADDC A,ear 2 3 1 0 byte (A) ← (A) + (ear)+ (C) Z - - - - * * * * -ADDC A,eam 2+ 4 + (a) 0 (b) byte (A) ← (A) + (eam)+ (C) Z - - - - * * * * -ADDDC A 1 3 0 0 byte (A) ← (AH) + (AL) + (C)

(decimal)Z - - - - * * * * -

SUB A,#imm8 2 2 0 0 byte (A) ← (A) - imm8 Z - - - - * * * * -SUB A,dir 2 5 0 (b) byte (A) ← (A) - (dir) Z - - - - * * * * -SUB A,ear 2 3 1 0 byte (A) ← (A) - (ear) Z - - - - * * * * -SUB A,eam 2+ 4 + (a) 0 (b) byte (A) ← (A) - (eam) Z - - - - * * * * -SUB ear,A 2 3 2 0 byte (ear) ← (ear) - (A) - - - - - * * * * -SUB eam,A 2+ 5 + (a) 0 2 × (b) byte (eam) ← (eam) - (A) - - - - - * * * * *SUBC A 1 2 0 0 byte (A) ← (AH) - (AL) - (C) Z - - - - * * * * -SUBC A,ear 2 3 1 0 byte (A) ← (A) - (ear) - (C) Z - - - - * * * * -SUBC A,eam 2+ 4 + (a) 0 (b) byte (A) ← (A) - (eam) - (C) Z - - - - * * * * -SUBDC A 1 3 0 0 byte (A) ← (AH) - (AL) - (C)

(decimal)Z - - - - * * * * -

ADDW A 1 2 0 0 word (A) ← (AH) + (AL) - - - - - * * * * -ADDW A,ear 2 3 1 0 word (A) ← (A) + (ear) - - - - - * * * * -ADDW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) + (eam) - - - - - * * * * -ADDW A,#imm16 3 2 0 0 word (A) ← (A) + imm16 - - - - - * * * * -ADDW ear,A 2 3 2 0 word (ear) ← (ear) + (A) - - - - - * * * * -ADDW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) + (A) - - - - - * * * * *ADDCW A,ear 2 3 1 0 word (A) ← (A) + (ear) + (C) - - - - - * * * * -ADDCW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) + (eam) + (C) - - - - - * * * * -SUBW A 1 2 0 0 word (A) ← (AH) - (AL) - - - - - * * * * -SUBW A,ear 2 3 1 0 word (A) ← (A) - (ear) - - - - - * * * * -SUBW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) - (eam) - - - - - * * * * -SUBW A,#imm16 3 2 0 0 word (A) ← (A) - imm16 - - - - - * * * * -SUBW ear,A 2 3 2 0 word (ear) ← (ear) - (A) - - - - - * * * * -SUBW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) - (A) - - - - - * * * * *SUBCW A,ear 2 3 1 0 word (A) ← (A) - (ear) - (C) - - - - - * * * * -SUBCW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) - (eam) - (C) - - - - - * * * * -ADDL A,ear 2 6 2 0 long (A) ← (A) + (ear) - - - - - * * * * -ADDL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) + (eam) - - - - - * * * * -ADDL A,#imm32 5 4 0 0 long (A) ← (A) + imm32 - - - - - * * * * -SUBL A,ear 2 6 2 0 long (A) ← (A) - (ear) - - - - - * * * * -SUBL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) - (eam) - - - - - * * * * -SUBL A,#imm32 5 4 0 0 long (A) ← (A) - imm32 - - - - - * * * * -

435


Note:


Note:


Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)


INC ear 2 3 2 0 byte (ear) ← (ear) + 1 - - - - - * * * - -

INC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) + 1 - - - - - * * * - *

DEC ear 2 3 2 0 byte (ear) ← (ear) - 1 - - - - - * * * - -

DEC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) - 1 - - - - - * * * - *

INCW ear 2 3 2 0 word (ear) ← (ear) + 1 - - - - - * * * - -

INCW eam 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) + 1 - - - - - * * * - *

DECW ear 2 3 2 0 word (ear) ← (ear) - 1 - - - - - * * * - -

DECW eam 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) - 1 - - - - - * * * - *

INCL ear 2 7 4 0 long (ear) ← (ear) + 1 - - - - - * * * - -

INCL eam 2+ 9+(a) 0 2 × (d) long (eam) ← (eam) + 1 - - - - - * * * - *

DECL ear 2 7 4 0 long (ear) ← (ear) - 1 - - - - - * * * - -

DECL eam 2+ 9+(a) 0 2 × (d) long (eam) ← (eam) - 1 - - - - - * * * - *

Table B.8-5 11 Compare Instructions (Byte, Word, Long Word)


CMP A 1 1 0 0 byte (AH) - (AL) - - - - - * * * * -

CMP A,ear 2 2 1 0 byte (A) - (ear) - - - - - * * * * -

CMP A,eam 2+ 3+(a) 0 (b) byte (A) - (eam) - - - - - * * * * -

CMP A,#imm8 2 2 0 0 byte (A) - imm8 - - - - - * * * * -

CMPW A 1 1 0 0 word (AH) - (AL) - - - - - * * * * -

CMPW A,ear 2 2 1 0 word (A) - (ear) - - - - - * * * * -

CMPW A,eam 2+ 3+(a) 0 (c) word (A) - (eam) - - - - - * * * * -

CMPW A,#imm16 3 2 0 0 word (A) - imm16 - - - - - * * * * -

CMPL A,ear 2 6 2 0 long (A) - (ear) - - - - - * * * * -

CMPL A,eam 2+ 7+(a) 0 (d) long (A) - (eam) - - - - - * * * * -

CMPL A,#imm32 5 3 0 0 long (A) - imm32 - - - - - * * * * -

436


Note:

See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.

Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)


DIVU A 1 *1 0 0 word (AH) / byte (AL)quotient → byte (AL) remainder → byte (AH)

- - - - - - - * * -

DIVU A,ear 2 *2 1 0 word (A) / byte (ear)quotient → byte (A) remainder → byte (ear)

- - - - - - - * * -

DIVU A,eam 2+ *3 0 *6 word (A) / byte (eam)quotient → byte (A) remainder → byte (eam)

- - - - - - - * * -

DIVUW A,ear 2 *4 1 0 long (A) / word (ear)quotient → word (A) remainder → word (ear)

- - - - - - - * * -

DIVUW A,eam 2+ *5 0 *7 long (A) / word (eam)quotient → word (A) remainder → word (eam)

- - - - - - - * * -

MULU A 1 *8 0 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - -

MULU A,ear 2 *9 1 0 byte (A) * byte (ear) → word (A) - - - - - - - - - -

MULU A,eam 2+ *10 0 (b) byte (A) * byte (eam) → word (A) - - - - - - - - - -

MULUW A 1 *11 0 0 word (AH) * word (AL) → Long (A) - - - - - - - - - -

MULUW A,ear 2 *12 1 0 word (A) * word (ear) → Long (A) - - - - - - - - - -

MULUW A,eam 2+ *13 0 (c) word (A) * word (eam) → Long (A) - - - - - - - - - -

*1: 3: Division by 0 7: Overflow 15: Normal*2: 4: Division by 0 8: Overflow 16: Normal*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal*4: 4: Division by 0 7: Overflow 22: Normal*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal*6: (b): Division by 0 or overflow 2 × (b): Normal*7: (c): Division by 0 or overflow 2 × (c): Normal*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.

437


Notes:

• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a pre-operation count or a post-operation count depending on the detection timing.

• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.

• See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.

Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)


DIV A 2 *1 0 0 word (AH) / byte (AL)quotient → byte (AL) remainder → byte (AH)

Z - - - - - - * * -

DIV A,ear 2 *2 1 0 word (A) / byte (ear)quotient → byte (A) remainder → byte (ear)

Z - - - - - - * * -

DIV A,eam 2+ *3 0 *6 word (A) / byte (eam)quotient → byte (A) remainder → byte (eam)

Z - - - - - - * * -

DIVW A,ear 2 *4 1 0 long (A) / word (ear)quotient → word (A) remainder → word (ear)

- - - - - - - * * -

DIVW A,eam 2+ *5 0 *7 long (A) / word (eam)quotient → word (A) remainder → word (eam)

- - - - - - - * * -

MUL A 2 *8 0 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - -

MUL A,ear 2 *9 1 0 byte (A) * byte (ear) → word (A) - - - - - - - - - -

MUL A,eam 2+ *10 0 (b) byte (A) * byte (eam) → word (A) - - - - - - - - - -

MULW A 2 *11 0 0 word (AH) * word (AL) → Long (A) - - - - - - - - - -

MULW A,ear 2 *12 1 0 word (A) * word (ear) → Long (A) - - - - - - - - - -

MULW A,eam 2+ *13 0 (c) word (A) * word (eam) → Long (A) - - - - - - - - - -

*1: 3: Division by 0, 8 or 18: Overflow, 18: Normal*2: 4: Division by 0, 11 or 22: Overflow, 23: Normal*3: 5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal*4: When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal

When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal

When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal*6: (b): Division by 0 or overflow, 2 × (b): Normal*7: (c): Division by 0 or overflow, 2 × (c): Normal*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative

438


Note:


Table B.8-8 39 Logic 1 Instructions (Byte, Word)


AND A,#imm8 2 2 0 0 byte (A) ← (A) and imm8 - - - - - * * R - -

AND A,ear 2 3 1 0 byte (A) ← (A) and (ear) - - - - - * * R - -

AND A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) and (eam) - - - - - * * R - -

AND ear,A 2 3 2 0 byte (ear) ← (ear) and (A) - - - - - * * R - -

AND eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) and (A) - - - - - * * R - *

OR A,#imm8 2 2 0 0 byte (A) ← (A) or imm8 - - - - - * * R - -

OR A,ear 2 3 1 0 byte (A) ← (A) or (ear) - - - - - * * R - -

OR A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) or (eam) - - - - - * * R - -

OR ear,A 2 3 2 0 byte (ear) ← (ear) or (A) - - - - - * * R - -

OR eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) or (A) - - - - - * * R - *

XOR A,#imm8 2 2 0 0 byte (A) ← (A) xor imm8 - - - - - * * R - -

XOR A,ear 2 3 1 0 byte (A) ← (A) xor (ear) - - - - - * * R - -

XOR A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) xor (eam) - - - - - * * R - -

XOR ear,A 2 3 2 0 byte (ear) ← (ear) xor (A) - - - - - * * R - -

XOR eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) xor (A) - - - - - * * R - *

NOT A 1 2 0 0 byte (A) ← not (A) - - - - - * * R - -

NOT ear 2 3 2 0 byte (ear) ← not (ear) - - - - - * * R - -

NOT eam 2+ 5+(a) 0 2 × (b) byte (eam) ← not (eam) - - - - - * * R - *

ANDW A 1 2 0 0 word (A) ← (AH) and (A) - - - - - * * R - -

ANDW A,#imm16 3 2 0 0 word (A) ← (A) and imm16 - - - - - * * R - -

ANDW A,ear 2 3 1 0 word (A) ← (A) and (ear) - - - - - * * R - -

ANDW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) and (eam) - - - - - * * R - -

ANDW ear,A 2 3 2 0 word (ear) ← (ear) and (A) - - - - - * * R - -

ANDW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) and (A) - - - - - * * R - *

ORW A 1 2 0 0 word (A) ← (AH) or (A) - - - - - * * R - -

ORW A,#imm16 3 2 0 0 word (A) ← (A) or imm16 - - - - - * * R - -

ORW A,ear 2 3 1 0 word (A) ← (A) or (ear) - - - - - * * R - -

ORW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) or (eam) - - - - - * * R - -

ORW ear,A 2 3 2 0 word (ear) ← (ear) or (A) - - - - - * * R - -

ORW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) or (A) - - - - - * * R - *

XORW A 1 2 0 0 word (A) ← (AH) xor (A) - - - - - * * R - -

XORW A,#imm16 3 2 0 0 word (A) ← (A) xor imm16 - - - - - * * R - -

XORW A,ear 2 3 1 0 word (A) ← (A) xor (ear) - - - - - * * R - -

XORW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) xor (eam) - - - - - * * R - -

XORW ear,A 2 3 2 0 word (ear) ← (ear) xor (A) - - - - - * * R - -

XORW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) xor (A) - - - - - * * R - *

NOTW A 1 2 0 0 word (A) ← not (A) - - - - - * * R - -

NOTW ear 2 3 2 0 word (ear) ← not (ear) - - - - - * * R - -

NOTW eam 2+ 5+(a) 0 2 × (c) word (eam) ← not (eam) - - - - - * * R - *

439


Note:

See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table.

Note:


Table B.8-9 6 Logic 2 Instructions (Long Word)


ANDL A,ear 2 6 2 0 long (A) ← (A) and (ear) - - - - - * * R - -

ANDL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) and (eam) - - - - - * * R - -

ORL A,ear 2 6 2 0 long (A) ← (A) or (ear) - - - - - * * R - -

ORL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) or (eam) - - - - - * * R - -

XORL A,ear 2 6 2 0 long (A) ← (A) xor (ear) - - - - - * * R - -

XORL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) xor (eam) - - - - - * * R - -

Table B.8-10 6 Sign Inversion Instructions (Byte, Word)


NEG A 1 2 0 0 byte (A) ← 0 - (A) X - - - - * * * * -

NEG ear 2 3 2 0 byte (ear) ← 0 - (ear) - - - - - * * * * -

NEG eam 2+ 5+(a) 0 2 × (b) byte (eam) ← 0 - (eam) - - - - - * * * * *

NEGW A 1 2 0 0 word (A) ← 0 - (A) - - - - - * * * * -

NEGW ear 2 3 2 0 word (ear) ← 0 - (ear) - - - - - * * * * -

NEGW eam 2+ 5+(a) 0 2 × (c) word (eam) ← 0 - (eam) - - - - - * * * * *

Table B.8-11 1 Normalization Instruction (Long Word)


NRML A,R0 2 *1 1 0 long (A) ← Shift left to the position where '1' is set for the first time.byte (R0) ← Shift count at that time

- - - - - - * - - -

*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)

440


Note:

See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.

Table B.8-12 18 Shift Instructions (Byte, Word, Long Word)


RORC A 2 2 0 0 byte (A) ← Right rotation with carry - - - - - * * - * -

ROLC A 2 2 0 0 byte (A) ← Right rotation with carry - - - - - * * - * -

RORC ear 2 3 2 0 byte (ear) ← Right rotation with carry - - - - - * * - * -

RORC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← Right rotation with carry - - - - - * * - * *

ROLC ear 2 3 2 0 byte (ear) ← Left rotation with carry - - - - - * * - * -

ROLC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← Left rotation with carry - - - - - * * - * *

ASR A,R0 2 *1 1 0 byte (A) ← Arithmetic right shift (A, 1 bit) - - - - * * * - * -

LSR A,R0 2 *1 1 0 byte (A) ← Logical right barrel shift (A, R0) - - - - * * * - * -

LSL A,R0 2 *1 1 0 byte (A) ← Logical left barrel shift (A, R0) - - - - - * * - * -

ASRW A 1 2 0 0 word (A) ← Arithmetic right shift (A, 1 bit) - - - - * * * - * -

LSRW A/SHRW A 1 2 0 0 word (A) ← Logical right shift (A, 1 bit) - - - - * R * - * -

LSLW A/SHLW A 1 2 0 0 word (A) ← Logical left shift (A, 1 bit) - - - - - * * - * -

ASRW A,R0 2 *1 1 0 word (A) ← Arithmetic right barrel shift (A, R0) - - - - * * * - * -

LSRW A,R0 2 *1 1 0 word (A) ← Logical right barrel shift (A, R0) - - - - * * * - * -

LSLW A,R0 2 *1 1 0 word (A) ← Logical left barrel shift (A, R0) - - - - - * * - * -

ASRL A,R0 2 *2 1 0 long (A) ← Arithmetic right barrel shift (A, R0) - - - - * * * - * -

LSRL A,R0 2 *2 1 0 long (A) ← Logical right barrel shift (A, R0) - - - - * * * - * -

LSLL A,R0 2 *2 1 0 long (A) ← Logical left barrel shift (A, R0) - - - - - * * - * -

*1: 6 when R0 is 0; otherwise, 5 + (R0)*2: 6 when R0 is 0; otherwise, 6 + (R0)

441


Note:


Table B.8-13 31 Branch 1 Instructions


BZ/BEQ rel 2 *1 0 0 Branch on (Z) = 1 - - - - - - - - - -

BNZ/BNE

rel 2 *1 0 0 Branch on (Z) = 0 - - - - - - - - - -

BC/BLO rel 2 *1 0 0 Branch on (C) = 1 - - - - - - - - - -

BNC/BHS

rel 2 *1 0 0 Branch on (C) = 0 - - - - - - - - - -

BN rel 2 *1 0 0 Branch on (N) = 1 - - - - - - - - - -

BP rel 2 *1 0 0 Branch on (N) = 0 - - - - - - - - - -

BV rel 2 *1 0 0 Branch on (V) = 1 - - - - - - - - - -

BNV rel 2 *1 0 0 Branch on (V) = 0 - - - - - - - - - -

BT rel 2 *1 0 0 Branch on (T) = 1 - - - - - - - - - -

BNT rel 2 *1 0 0 Branch on (T) = 0 - - - - - - - - - -

BLT rel 2 *1 0 0 Branch on (V) xor (N) = 1 - - - - - - - - - -

BGE rel 2 *1 0 0 Branch on (V) xor (N) = 0 - - - - - - - - - -

BLE rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 1 - - - - - - - - - -

BGT rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 0 - - - - - - - - - -

BLS rel 2 *1 0 0 Branch on (C) or (Z) = 1 - - - - - - - - - -

BHI rel 2 *1 0 0 Branch on (C) or (Z) = 0 - - - - - - - - - -

BRA rel 2 *1 0 0 Unconditional branch - - - - - - - - - -

JMP @A 1 2 0 0 word (PC) ← (A) - - - - - - - - - -

JMP addr16 3 3 0 0 word (PC) ← addr16 - - - - - - - - - -

JMP @ear 2 3 1 0 word (PC) ← (ear) - - - - - - - - - -

JMP @eam 2+ 4+(a) 0 (c) word (PC) ← (eam) - - - - - - - - - -

JMPP @ear *3 2 5 2 0 word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - -

JMPP @eam *3 2+ 6+(a) 0 (d) word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - -

JMPP addr24 4 4 0 0 word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - -

CALL @ear *4 2 6 1 (c) word (PC) ← (ear) - - - - - - - - - -

CALL @eam *4 2+ 7+(a) 0 2 × (c) word (PC) ← (eam) - - - - - - - - - -

CALL addr16 *5 3 6 0 (c) word (PC) ← addr16 - - - - - - - - - -

CALLV #vct4 *5 1 7 0 2 × (c) Vector call instruction - - - - - - - - - -

CALLP @ear *6 2 10 2 2 × (c) word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - -

CALLP @eam *6 2+ 11+(a) 0 *2 word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - -

CALLP addr24 *7 4 10 0 2 × (c) word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - -

*1: 4 when a branch is made; otherwise, 3*2: 3 × (c) + (b)*3: Read (word) of branch destination address*4: W: Save to stack (word) R: Read (word) of branch destination address*5: Save to stack (word)*6: W: Save to stack (long word), R: Read (long word) of branch destination address *7: Save to stack (long word)

442


Note:


Table B.8-14 19 Branch 2 Instructions


CBNE A,#imm8,rel 3 *1 0 0 Branch on byte (A) not equal to imm8 - - - - - * * * * -

CWBNE A,#imm16,rel 4 *1 0 0 Branch on word (A) not equal to imm16 - - - - - * * * * -

CBNE ear,#imm8,rel 4 *2 1 0 Branch on byte (ear) not equal to imm8 - - - - - * * * * -

CBNE eam,#imm8,rel *9 4+ *3 0 (b) Branch on byte (eam) not equal to imm8 - - - - - * * * * -

CWBNE ear,#imm16,rel 5 *4 1 0 Branch on word (ear) not equal to imm16 - - - - - * * * * -

CWBNE eam,#imm16,rel*9 5+ *3 0 (c) Branch on word (eam) not equal to imm16 - - - - - * * * * -

DBNZ ear,rel 3 *5 2 0 byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0 - - - - - * * * - -

DBNZ eam,rel 3+ *6 2 2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0 - - - - - * * * - *

DWBNZ ear,rel 3 *5 2 0 word (ear) ← (ear) - 1, Branch on (ear) not equal to 0 - - - - - * * * - -

DWBNZ eam,rel 3+ *6 2 2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0 - - - - - * * * - *

INT #vct8 2 20 0 8 × (c) Software interrupt - - R S - - - - - -

INT addr16 3 16 0 6 × (c) Software interrupt - - R S - - - - - -

INTP addr24 4 17 0 6 × (c) Software interrupt - - R S - - - - - -

INT9 1 20 0 8 × (c) Software interrupt - - R S - - - - - -

RETI 1 *8 0 *7 Return from interrupt - - * * * * * * * -

LINK #imm8 2 6 0 (c) Saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area.

- - - - - - - - - -

UNLINK 1 5 0 (c) Recovers the old frame pointer from the stack upon exiting the function.

- - - - - - - - - -

RET *10 1 4 0 (c) Return from subroutine - - - - - - - - - -

RETP *11 1 6 0 (d) Return from subroutine - - - - - - - - - -

*1: 5 when a branch is made; otherwise, 4*2: 13 when a branch is made; otherwise, 12*3: 7+(a) when a branch is made; otherwise, 6+(a)*4: 8 when a branch is made; otherwise, 7*5: 7 when a branch is made; otherwise, 6*6: 8+(a) when a branch is made; otherwise, 7+(a)*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.*10: Return from stack (word)*11: Return from stack (long word)

443


Note:

See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table.

Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word)


PUSHW A 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (A) - - - - - - - - - -

PUSHW AH 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (AH) - - - - - - - - - -

PUSHW PS 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (PS) - - - - - - - - - -

PUSHW rlst 2 *3 *5 *4 (SP) ← (SP) - 2n, ((SP)) ← (rlst) - - - - - - - - - -

POPW A 1 3 0 (c) word (A) ← ((SP)), (SP) ← (SP) + 2 - * - - - - - - - -

POPW AH 1 3 0 (c) word (AH) ← ((SP)), (SP) ← (SP) + 2 - - - - - - - - - -

POPW PS 1 4 0 (c) word (PS) ← ((SP)), (SP) ← (SP) + 2 - - * * * * * * * -

POPW rlst 2 *2 *5 *4 (rlst) ← ((SP)), (SP) ← (SP) + 2n - - - - - - - - - -

JCTX @A 1 14 0 6 × (c) Context switch instruction - - * * * * * * * -

AND CCR,#imm8 2 3 0 0 byte (CCR) ← (CCR) and imm8 - - * * * * * * * -

OR CCR,#imm8 2 3 0 0 byte (CCR) ← (CCR) or imm8 - - * * * * * * * -

MOV RP,#imm8 2 2 0 0 byte (RP) ← imm8 - - - - - - - - - -

MOV ILM,#imm8 2 2 0 0 byte (ILM) ← imm8 - - - - - - - - - -

MOVEA RWi,ear 2 3 1 0 word (RWi) ← ear - - - - - - - - - -

MOVEA RWi,eam 2+ 2+(a) 1 0 word (RWi) ← eam - - - - - - - - - -

MOVEA A,ear 2 1 0 0 word (A) ← ear - * - - - - - - - -

MOVEA A,eam 2+ 1+(a) 0 0 word (A) ← eam - * - - - - - - - -

ADDSP #imm8 2 3 0 0 word (SP) ← (SP) + ext(imm8) - - - - - - - - - -

ADDSP #imm16 3 3 0 0 word (SP) ← (SP) + imm16 - - - - - - - - - -

MOV A,brg1 2 *1 0 0 byte (A) ← (brg1) Z * - - - * * - - -

MOV brg2,A 2 1 0 0 byte (brg2) ← (A) - - - - - * * - - -

NOP 1 1 0 0 No operation - - - - - - - - - -

ADB 1 1 0 0 Prefix code for AD space access - - - - - - - - - -

DTB 1 1 0 0 Prefix code for DT space access - - - - - - - - - -

PCB 1 1 0 0 Prefix code for PC space access - - - - - - - - - -

SPB 1 1 0 0 Prefix code for SP space access - - - - - - - - - -

NCC 1 1 0 0 Prefix code for flag no-change - - - - - - - - - -

CMR 1 1 0 0 Prefix code for common register bank - - - - - - - - - -

*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)*4: (POP count) × (c) or (PUSH count) × (c)*5: (POP count) or (PUSH count)

444


Note:

See Table B.5-1 and Table B.5-2 for information on (b) in the table.

Table B.8-16 21 Bit Operand Instructions


MOVB A,dir:bp 3 5 0 (b) byte (A) ← (dir:bp)b Z * - - - * * - - -

MOVB A,addr16:bp 4 5 0 (b) byte (A) ← (addr16:bp)b Z * - - - * * - - -

MOVB A,io:bp 3 4 0 (b) byte (A) ← (io:bp)b Z * - - - * * - - -

MOVB dir:bp,A 3 7 0 2 × (b) bit (dir:bp)b ← (A) - - - - - * * - - *

MOVB addr16:bp,A 4 7 0 2 × (b) bit (addr16:bp)b ← (A) - - - - - * * - - *

MOVB io:bp,A 3 6 0 2 × (b) bit (io:bp)b ← (A) - - - - - * * - - *

SETB dir:bp 3 7 0 2 × (b) bit (dir:bp)b ← 1 - - - - - - - - - *

SETB addr16:bp 4 7 0 2 × (b) bit (addr16:bp)b ← 1 - - - - - - - - - *

SETB io:bp 3 7 0 2 × (b) bit (io:bp)b ← 1 - - - - - - - - - *

CLRB dir:bp 3 7 0 2 × (b) bit (dir:bp)b ← 0 - - - - - - - - - *

CLRB addr16:bp 4 7 0 2 × (b) bit (addr16:bp)b ← 0 - - - - - - - - - *

CLRB io:bp 3 7 0 2 × (b) bit (io:bp)b ← 0 - - - - - - - - - *

BBC dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 0 - - - - - - * - - -

BBC addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 0 - - - - - - * - - -

BBC io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 0 - - - - - - * - - -

BBS dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 1 - - - - - - * - - -

BBS addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 1 - - - - - - * - - -

BBS io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 1 - - - - - - * - - -

SBBS addr16:bp,rel 5 *3 0 2 × (b) Branch on (addr16:bp) b = 1, bit (addr16:bp) b ← 1

- - - - - - * - - *

WBTS io:bp 3 *4 0 *5 Waits until (io:bp) b = 1 - - - - - - - - - -

WBTC io:bp 3 *4 0 *5 Waits until (io:bp) b = 0 - - - - - - - - - -

*1: 8 when a branch is made; otherwise, 7*2: 7 when a branch is made; otherwise, 6*3: 10 when the condition is met; otherwise, 9*4: Undefined count*5: Until the condition is met

Table B.8-17 6 Accumulator Operation Instructions (Byte, Word)


SWAP 1 3 0 0 byte (A)0-7 ↔ (A)8-15 - - - - - - - - - -

SWAPW 1 2 0 0 word (AH) ↔ (AL) - * - - - - - - - -

EXT 1 1 0 0 Byte sign extension X - - - - * * - - -

EXTW 1 2 0 0 Word sign extension - X - - - * * - - -

ZEXT 1 1 0 0 Byte zero extension Z - - - - R * - - -

ZEXTW 1 1 0 0 Word zero extension - Z - - - R * - - -

445


Note:

m: RW0 value (counter value), n: Loop count

See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table.

Table B.8-18 10 String Instructions


MOVS / MOVSI 2 *2 *5 *3 byte transfer @AH+ ← @AL+, counter = RW0 - - - - - - - - - -

MOVSD 2 *2 *5 *3 byte transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - -

SCEQ / SCEQI 2 *1 *8 *4 byte search @AH+ ← AL, counter = RW0 - - - - - * * * * -

SCEQD 2 *1 *8 *4 byte search @AH- ← AL, counter = RW0 - - - - - * * * * -

FILS / FILSI 2 6m+6 *8 *3 byte fill @AH+ ← AL, counter = RW0 - - - - - * * - - -

MOVSW / MOVSWI 2 *2 *5 *6 word transfer @AH+ ← @AL+, counter = RW0 - - - - - - - - - -

MOVSWD 2 *2 *5 *6 word transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - -

SCWEQ / SCWEQI 2 *1 *8 *7 word search @AH+ - AL, counter = RW0 - - - - - * * * * -

SCWEQD 2 *1 *8 *7 word search @AH- - AL, counter = RW0 - - - - - * * * * -

FILSW / FILSWI 2 6m+6 *8 *6 word fill @AH+ ← AL, counter = RW0 - - - - - * * - - -

*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.*4: (b) × n*5: 2 × (b) × (RW0)*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.*7: (c) × n*8: (b) × (RW0)

446


B.9 Instruction Map

Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction

map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX instruction map.

■ Structure of Instruction Map

Figure B.9-1 Structure of Instruction Map

An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An

instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it

references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2

shows the correspondence between an actual instruction code and instruction map.

Basic page map : Byte 1

Bit operation instructions

Character string operation

instructions

2-byte instructions

ea instructions × 9 : Byte 2

447


Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map

An example of an instruction code is shown in Table B.9-1.

*: The extended page map is a generic name of maps for bit operation instructions, characterstring operation instructions, 2-byte instructions, and ea instructions. Actually, there aremultiple extended page maps for each type of instructions.

Some instructions do not contain byte 2.

Length varies depending on the instruction.

Instruction code

Byte 1 Byte 2 Operand Operand . . .

[Basic page map]

XY

+Z

[Extended page map]*

UV

+W

Table B.9-1 Example of an Instruction Code

Instruction Byte 1(from basic page map)

Byte 2(from extended page map)

NOP 00 +0=00 -

AND A, #8 30 +4=34 -

MOV A, ADB 60 +F=6F 00 +0=00

@RW2+d8, #8, rel 70 +0=70 F0 +2=F2

448


Table B.9-2 Basic Page Map

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

NO

PC

MR

AD

DA

, dir

AD

DA

, #8

MO

VA

, dir

MO

VA

, io

BR

Are

lea

in

stru

ctio

n 1

MO

VA

, Ri

MO

VR

i, A

MO

VR

i, #8

MO

VA

, Ri

MO

VX

A,

@R

Wi+

d8M

OV

A, #

4C

ALL

#4B

Z/B

EQ

rel

+1

INT

9N

CC

SU

BA

, dir

SU

BA

, #8

MO

Vdi

r, A

MO

Vio

, AJM

P@

Aea

in

stru

ctio

n 2

BN

Z/B

NE re

l

+2

AD

DD

CA

SU

BD

CA

AD

DC

AS

UB

CA

MO

VA

, #8

MO

VA

, add

r16

JMP ad

dr16

ea

inst

ruct

ion

3B

C/B

LOre

l

+3

NE

GA

JCT

X@

AC

MP

AC

MP

A, #

8M

OV

X A, #

8M

OV

addr

16, A

JMP

P addr

24ea

in

stru

ctio

n 4

BN

C/B

HS re

l

+4

PC

BE

XT

AN

D CC

R, #

8A

ND

A, #

8M

OV di

r, #

8M

OV

io, #

8C

ALL ad

dr16

ea

inst

ruct

ion

5B

Nre

l

+5

DT

BZ

EX

TO

R CC

R, #

8O

RA

, #8

MO

VX A

, dir

MO

VX

A, i

oC

ALL

Pad

dr24

ea

inst

ruct

ion

6B

Pre

l

+6

AD

BS

WA

PD

IVU

AX

OR

A, #

8M

OV

W A, S

PM

OV

W io, #

16R

ET

Pea

in

stru

ctio

n 7

BV

rel

+7

SP

BA

DD

SP

#8M

ULU

AN

OT

AM

OV

W SP

, AM

OV

XA

, add

r16

RE

Tea

in

stru

ctio

n 8

BN

Vre

l

+8

LIN

K #im

m8

AD

DL A

, #32

AD

DW

AA

DD

W A, #

16M

OV

W A, d

irM

OV

WA

, io

INT

#vct

8ea

in

stru

ctio

n 9

MO

VW A, R

Wi

MO

VW RW

i, A

MO

VW

RW

i, #1

6M

OV

A,

@R

Wi+

d8M

OV

W

@R

Wi+

d8, A

BT

rel

+9

UN

LIN

KS

UB

L A, #

32S

UB

WA

SU

BW A

, #16

MO

VW di

r, A

MO

VW

io, A

INT

addr

16M

OV

EA

RW

i, ea

BN

Tre

l

+A

MO

V RP

, #8

MO

V ILM

, #8

CB

NE

A,

#8, r

elC

WB

NE

A,

#16,

rel

MO

VW A, #

16M

OV

WA

,add

r16

INT

P addr

24M

OV

Ri,

eaB

LTre

l

+B

NE

GW

AC

MP

L A, #

32C

MP

WA

CM

PW A, #

16M

OV

L A, #

32M

OV

Wad

dr16

, AR

ET

IM

OV

WR

Wi,

eaB

GE

rel

+C

LSLW

AE

XT

WA

ND

WA

AN

DW A

, #16

PU

SH

WA

PO

PW

AB

it op

erat

ion

inst

ruct

ion

MO

Vea

, Ri

BLE

rel

+D

ZE

XT

WO

RW

AO

RW A

, #16

PU

SH

WA

HP

OP

WA

HM

OV

Wea

, RW

iB

GT

rel

+E

AS

RW

AS

WA

PW

XO

RW

AX

OR

W A, #

16P

US

HW

PS

PO

PW

PS

Cha

ract

er

strin

g op

erat

ion

inst

ruct

ion

XC

HR

i, ea

BLS

rel

+F

LSR

WA

AD

DS

P #16

MU

LUW

AN

OT

WA

PU

SH

Wrls

tP

OP

Wrls

t2-

byte

in

stru

ctio

nX

CH

WR

Wi,

eaB

HI

rel

449


Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

VB

A, i

o:bp

MO

VB

io:b

p, A

CLR

Bio

:bp

SE

TB

io:b

pB

BC io

;bp,

rel

BB

S io:b

p, r

elW

BT

S io:b

pW

BT

C io:b

p

+1

+2

+3

+4

+5

+6

+7

+8

MO

VB

A, d

ir:bp

MO

VB

A,

addr

16:b

pM

OV

Bdi

r:bp

, AM

OV

Bad

dr16

:bp,

AC

LRB di

r:bp

CLR

Bad

dr16

:bp

SE

TB di

r:bp

SE

TB

addr

16:b

pB

BC dir:

bp, r

elB

BC

addr

16:b

p,re

lB

BS dir:

bp, r

elB

BS

addr

16:b

p,re

lS

BB

Sad

dr16

:bp

+9

+A

+B

+C

+D +E +F

450


Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

VS

IP

CB

, PC

BM

OV

SD

MO

VS

WI

MO

VS

WD

SC

EQ

I PC

BS

CE

QD P

CB

SC

WE

QI

PC

BS

CW

EQ

DP

CB

FIL

SI

PC

BF

ILS

IP

CB

+1

PC

B, D

TB

DT

BD

TB

DT

BD

TB

DT

BD

TB

+2

PC

B, A

DB

AD

BA

DB

AD

BA

DB

AD

BA

DB

+3

PC

B, S

PB

SP

BS

PB

SP

BS

PB

SP

BS

PB

+4

DT

B, P

CB

+5

DT

B, D

TB

+6

DT

B, A

DB

+7

DT

B, S

PB

+8

AD

B, P

CB

+9

AD

B, D

TB

+A

AD

B, A

DB

+B

AD

B, S

PB

+C

SP

B, P

CB

+D

SP

B, D

TB

+E

SP

B, A

DB

+FS

PB

, SP

B

451


Table B.9-5 2-byte Instruction Map (First Byte = 6FH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

V A, D

TB

MO

V DT

B, A

MO

VX

A, @

RL0

+d8

MO

V@

RL0

+d8,

AM

OV

A, @

RL0

+d8

+1

MO

V A, A

DB

MO

V AD

B, A

+2

MO

V A, S

SB

MO

V SS

B, A

MO

VX

A, @

RL1

+d8

MO

V@

RL1

+d8,

AM

OV

A, @

RL1

+d8

+3

MO

V A, U

SB

MO

V US

B, A

+4

MO

V A, D

PR

MO

V DP

R, A

MO

VX

A, @

RL2

+d8

MO

V@

RL2

+d8,

AM

OV

A, @

RL2

+d8

+5

MO

V A, @

AM

OV

@A

L, A

H

+6

MO

V A, P

CB

MO

V A, @

AM

OV

XA

, @R

L3+d

8M

OV

@R

L3+d

8, A

MO

VA

, @R

L3+d

8

+7

RO

LCA

RO

LCA

+8

MO

VW

@R

L0+d

8, A

MO

VW

A, @

RL0

+d8

MU

LA

+9

MU

LWA

+A

MO

VW

@R

L1+d

8, A

MO

VW

A, @

RL1

+d8

DIV

UA

+B

+CLS

LWA

, R0

LSLL

A, R

0LS

LA

, R0

MO

VW

@R

L2+d

8, A

MO

VW

A, @

RL2

+d8

+DM

OV

W A, @

AM

OV

W@

AL,

AH

NR

ML A

, R0

+E

AS

RW A

, R0

AS

RL A

, R0

AS

RA

, R0

MO

VW

@R

L3+d

8, A

MO

VW

A, @

RL3

+d8

+F

LSR

W A, R

0LS

RL A

, R0

LSR

A, R

0

452


Table B.9-6 ea Instruction 1 (First Byte = 70H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

CW

BN

E ↓

CW

BN

E ↓

CB

NE

↓C

BN

E ↓

+0

AD

DL A, R

L0A

DD

L A

,@

RW

0+d8

SU

BL A, R

L0S

UB

L A

,@

RW

0+d8

RW

0,#1

6, r

el@

RW

0+d8

#16,

rel

CM

PL A, R

L0C

MP

L A

,@

RW

0+d8

AN

DL A, R

L0A

ND

L A

,@

RW

0+d8

OR

L A, R

L0O

RL

A,

@R

W0+

d8X

OR

L A, R

L0X

OR

L A

,@

RW

0+d8

R0,

#8, r

el@

RW

0+d8

,#8

, rel

+1

AD

DL A, R

L0A

DD

L A

,@

RW

1+d8

SU

BL A, R

L0S

UB

L A

,@

RW

1+d8

RW

1,#1

6, r

el@

RW

1+d8

#16,

rel

CM

PL A, R

L0C

MP

L A

,@

RW

1+d8

AN

DL A, R

L0A

ND

L A

,@

RW

1+d8

OR

L A, R

L0O

RL

A,

@R

W1+

d8X

OR

L A, R

L0X

OR

L A

,@

RW

1+d8

R1,

#8, r

el@

RW

1+d8

,#8

, rel

+2

AD

DL A, R

L1A

DD

L A

,@

RW

2+d8

SU

BL A, R

L1S

UB

L A

,@

RW

2+d8

RW

2,#1

6, r

el@

RW

2+d8

#16,

rel

CM

PL A, R

L1C

MP

L A

,@

RW

2+d8

AN

DL A, R

L1A

ND

L A

,@

RW

2+d8

OR

L A, R

L1O

RL

A,

@R

W2+

d8X

OR

L A, R

L1X

OR

L A

,@

RW

2+d8

R2,

#8, r

el@

RW

2+d8

,#8

, rel

+3

AD

DL A, R

L1A

DD

L A

,@

RW

3+d8

SU

BL A, R

L1S

UB

L A

,@

RW

3+d8

RW

3,#1

6, r

el@

RW

3+d8

#16,

rel

CM

PL A, R

L1C

MP

L A

,@

RW

3+d8

AN

DL A, R

L1A

ND

L A

,@

RW

3+d8

OR

L A, R

L1O

RL

A,

@R

W3+

d8X

OR

L A, R

L1X

OR

L A

,@

RW

3+d8

R3,

#8, r

el@

RW

3+d8

,#8

, rel

+4

AD

DL A, R

L2A

DD

L A

,@

RW

4+d8

SU

BL A, R

L2S

UB

L A

,@

RW

4+d8

RW

4,#1

6, r

el@

RW

4+d8

#16,

rel

CM

PL A, R

L2C

MP

L A

,@

RW

4+d8

AN

DL A, R

L2A

ND

L A

,@

RW

4+d8

OR

L A, R

L2O

RL

A,

@R

W4+

d8X

OR

L A, R

L2X

OR

L A

,@

RW

4+d8

R4,

#8, r

el@

RW

4+d8

,#8

, rel

+5

AD

DL A, R

L2A

DD

L A

,@

RW

5+d8

SU

BL A, R

L2S

UB

L A

,@

RW

5+d8

RW

5,#1

6, r

el@

RW

5+d8

#16,

rel

CM

PL A, R

L2C

MP

L A

,@

RW

5+d8

AN

DL A, R

L2A

ND

L A

,@

RW

5+d8

OR

L A, R

L2O

RL

A,

@R

W5+

d8X

OR

L A, R

L2X

OR

L A

,@

RW

5+d8

R5,

#8, r

el@

RW

5+d8

,#8

, rel

+6

AD

DL A, R

L3A

DD

L A

,@

RW

6+d8

SU

BL A, R

L3S

UB

L A

,@

RW

6+d8

RW

6,#1

6, r

el@

RW

6+d8

#16,

rel

CM

PL A, R

L3C

MP

L A

,@

RW

6+d8

AN

DL A, R

L3A

ND

L A

,@

RW

6+d8

OR

L A, R

L3O

RL

A,

@R

W6+

d8X

OR

L A, R

L3X

OR

L A

,@

RW

6+d8

R6,

#8, r

el@

RW

6+d8

,#8

, rel

+7

AD

DL A, R

L3A

DD

L A

,@

RW

7+d8

SU

BL A, R

L3S

UB

L A

,@

RW

7+d8

RW

7,#1

6, r

el@

RW

7+d8

#16,

rel

CM

PL A, R

L3C

MP

L A

,@

RW

7+d8

AN

DL A, R

L3A

ND

L A

,@

RW

7+d8

OR

L A, R

L3O

RL

A,

@R

W7+

d8X

OR

L A, R

L3X

OR

L A

,@

RW

7+d8

R7,

#8, r

el@

RW

7+d8

,#8

, rel

+8

AD

DL

A,@

RW

0A

DD

L A

,@

RW

0+d1

6S

UB

LA

,@R

W0

SU

BL

A,

@R

W0+

d16

@R

W0,

#16,

rel

@R

W0+

d16

#16,

rel

CM

PL

A,@

RW

0C

MP

L A

,@

RW

0+d1

6A

ND

LA

,@R

W0

AN

DL

A,

@R

W0+

d16

OR

LA

,@R

W0

OR

L A

,@

RW

0+d1

6X

OR

LA

,@R

W0

XO

RL

A,

@R

W0+

d16

@R

W0,

#8, r

el@

RW

0+d1

6,#

8, r

el

+9

AD

DL

A,@

RW

1A

DD

L A

,@

RW

1+d1

6S

UB

LA

,@R

W1

SU

BL

A,

@R

W1+

d16

@R

W1,

#16,

rel

@R

W1+

d16

#16,

rel

CM

PL

A,@

RW

1C

MP

L A

,@

RW

1+d1

6A

ND

LA

,@R

W1

AN

DL

A,

@R

W1+

d16

OR

LA

,@R

W1

OR

L A

,@

RW

1+d1

6X

OR

LA

,@R

W1

XO

RL

A,

@R

W1+

d16

@R

W1,

#8, r

el@

RW

1+d1

6,#

8, r

el

+AA

DD

LA

,@R

W2

AD

DL

A,

@R

W2+

d16

SU

BL

A,@

RW

2S

UB

L A

,@

RW

2+d1

6@

RW

2,#1

6, r

el@

RW

2+d1

6#1

6, r

elC

MP

LA

,@R

W2

CM

PL

A,

@R

W2+

d16

AN

DL

A,@

RW

2A

ND

L A

,@

RW

2+d1

6O

RL

A,@

RW

2O

RL

A,

@R

W2+

d16

XO

RL

A,@

RW

2X

OR

L A

,@

RW

2+d1

6@

RW

2,#8

, rel

@R

W2+

d16

,#8,

rel

+BA

DD

LA

,@R

W3

AD

DL

A,

@R

W3+

d16

SU

BL

A,@

RW

3S

UB

L A

,@

RW

3+d1

6@

RW

3,#1

6, r

el@

RW

3+d1

6#1

6, r

elC

MP

LA

,@R

W3

CM

PL

A,

@R

W3+

d16

AN

DL

A,@

RW

3A

ND

L A

,@

RW

3+d1

6O

RL

A,@

RW

3O

RL

A,

@R

W3+

d16

XO

RL

A,@

RW

3X

OR

L A

,@

RW

3+d1

6@

RW

3,#8

, rel

@R

W3+

d16

,#8,

rel

+C

AD

DL

A,@

RW

0+A

DD

L A

,@

RW0+

RW

7S

UB

LA

,@R

W0+

SU

BL

A,

@R

W0+

RW7

Use

pr

ohib

ited

@RW

0+R

W7

#16,

rel

CM

PL

A,@

RW

0+C

MP

L A

,@

RW0+

RW

7A

ND

LA

,@R

W0+

AN

DL

A,

@R

W0+

RW7

OR

LA

,@R

W0+

OR

L A

,@

RW

0+RW

7X

OR

LA

,@R

W0+

XO

RL

A,

@RW

0+R

W7

Use

pr

ohib

ited

@R

W0+

RW7

,#8,

rel

+D

AD

DL

A,@

RW

1+A

DD

L A

,@

RW1+

RW

7S

UB

LA

,@R

W1+

SU

BL

A,

@R

W1+

RW7

Use

pr

ohib

ited

@RW

1+R

W7

#16,

rel

CM

PL

A,@

RW

1+C

MP

L A

,@

RW1+

RW

7A

ND

LA

,@R

W1+

AN

DL

A,

@R

W1+

RW7

OR

LA

,@R

W1+

OR

L A

,@

RW

1+RW

7X

OR

LA

,@R

W1+

XO

RL

A,

@RW

1+R

W7

Use

pr

ohib

ited

@R

W1+

RW7

,#8,

rel

+EA

DD

LA

,@R

W2+

AD

DL

A,

@P

C+d

16S

UB

LA

,@R

W2+

SU

BL

A,

@P

C+d

16U

se

proh

ibite

d@

PC

+d16

,#1

6, r

elC

MP

LA

,@R

W2+

CM

PL

A,

@P

C+d

16A

ND

LA

,@R

W2+

AN

DL

A,

@P

C+d

16O

RL

A,@

RW

2+O

RL

A,

@P

C+d

16X

OR

LA

,@R

W2+

XO

RL

A,

@P

C+d

16U

se

proh

ibite

d@

PC

+d16

,,#

8, r

el

+F

AD

DL

A,@

RW

3+A

DD

L A

,ad

dr16

SU

BL

A,@

RW

3+S

UB

L A

,ad

dr16

Use

pr

ohib

ited

addr

16,

#16,

rel

CM

PL

A,@

RW

3+C

MP

L A

,ad

dr16

AN

DL

A,@

RW

3+A

ND

L A

,ad

dr16

OR

LA

,@R

W3+

OR

L A

,ad

dr16

XO

RL

A,@

RW

3+X

OR

L A

,ad

dr16

Use

pr

ohib

ited

addr

16,

,#8,

rel

453



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

JMP

P @R

L0JM

PP@

@RW

0+d8

CA

LLP

@R

L0C

ALLP

@@

RW0+

d8IN

CL

RL0

INC

L@

RW

0+d8

DE

CL

RL0

DE

CL

@R

W0+

d8M

OV

LA

, RL0

MO

VL

A,

@R

W0+

d8M

OV

LR

L0, A

MO

VL

@R

W0+

d8,A

MO

V R0,

#8

MO

V@

RW

0+d8

,#8

MO

VE

AA

, RW

0M

OV

EA

A,

@R

W0+

d8

+1

JMP

P @R

L0JM

PP@

@RW

1+d8

CA

LLP

@R

L0C

ALLP

@@

RW1+

d8IN

CL

RL0

INC

L@

RW

1+d8

DE

CL

RL0

DE

CL

@R

W1+

d8M

OV

LA

, RL0

MO

VL

A,

@R

W1+

d8M

OV

LR

L0, A

MO

VL

@R

W1+

d8,A

MO

V R1,

#8

MO

V@

RW

1+d8

,#8

MO

VE

AA

, RW

1M

OV

EA

A,

@R

W1+

d8

+2

JMP

P @R

L1JM

PP@

@RW

2+d8

CA

LLP

@R

L1C

ALLP

@@

RW2+

d8IN

CL

RL1

INC

L@

RW

2+d8

DE

CL

RL1

DE

CL

@R

W2+

d8M

OV

LA

, RL1

MO

VL

A,

@R

W2+

d8M

OV

LR

L1, A

MO

VL

@R

W2+

d8,A

MO

V R2,

#8

MO

V@

RW

2+d8

,#8

MO

VE

AA

, RW

2M

OV

EA

A,

@R

W2+

d8

+3

JMP

P @R

L1JM

PP@

@RW

3+d8

CA

LLP

@R

L1C

ALLP

@@

RW3+

d8IN

CL

RL1

INC

L@

RW

3+d8

DE

CL

RL1

DE

CL

@R

W3+

d8M

OV

LA

, RL1

MO

VL

A,

@R

W3+

d8M

OV

LR

L1, A

MO

VL

@R

W3+

d8,A

MO

V R3,

#8

MO

V@

RW

3+d8

,#8

MO

VE

AA

, RW

3M

OV

EA

A,

@R

W3+

d8

+4

JMP

P @R

L2JM

PP@

@RW

4+d8

CA

LLP

@R

L2C

ALLP

@@

RW4+

d8IN

CL

RL2

INC

L@

RW

4+d8

DE

CL

RL2

DE

CL

@R

W4+

d8M

OV

LA

, RL2

MO

VL

A,

@R

W4+

d8M

OV

LR

L2, A

MO

VL

@R

W4+

d8,A

MO

V R4,

#8

MO

V@

RW

4+d8

,#8

MO

VE

AA

, RW

4M

OV

EA

A,

@R

W4+

d8

+5

JMP

P @R

L2JM

PP@

@RW

5+d8

CA

LLP

@R

L2C

ALLP

@@

RW5+

d8IN

CL

RL2

INC

L@

RW

5+d8

DE

CL

RL2

DE

CL

@R

W5+

d8M

OV

LA

, RL2

MO

VL

A,

@R

W5+

d8M

OV

LR

L2, A

MO

VL

@R

W5+

d8,A

MO

V R5,

#8

MO

V@

RW

5+d8

,#8

MO

VE

AA

, RW

5M

OV

EA

A,

@R

W5+

d8

+6

JMP

P @R

L3JM

PP@

@RW

6+d8

CA

LLP

@R

L3C

ALLP

@@

RW6+

d8IN

CL

RL3

INC

L@

RW

6+d8

DE

CL

RL3

DE

CL

@R

W6+

d8M

OV

LA

, RL3

MO

VL

A,

@R

W6+

d8M

OV

LR

L3, A

MO

VL

@R

W6+

d8,A

MO

V R6,

#8

MO

V@

RW

6+d8

,#8

MO

VE

AA

, RW

6M

OV

EA

A,

@R

W6+

d8

+7

JMP

P @R

L3JM

PP@

@RW

7+d8

CA

LLP

@R

L3C

ALLP

@@

RW7+

d8IN

CL

RL3

INC

L@

RW

7+d8

DE

CL

RL3

DE

CL

@R

W7+

d8M

OV

LA

, RL3

MO

VL

A,

@R

W7+

d8M

OV

LR

L3, A

MO

VL

@R

W7+

d8,A

MO

V R7,

#8

MO

V@

RW

7+d8

,#8

MO

VE

AA

, RW

7M

OV

EA

A,

@R

W7+

d8

+8

JMP

P@

@R

W0

JMP

P @

@R

W0+

d16

CA

LLP

@@

RW

0C

ALL

P @

@R

W0+

d16

INC

L @R

W0

INC

L@

RW

0+d1

6D

EC

L@

RW

0D

EC

L@

RW

0+d1

6M

OV

LA

,@R

W0

MO

VL

A,

@R

W0+

d16

MO

VL

@R

W0,

AM

OVL

@R

W0+

d16,

AM

OV

@R

W0,

#8

MO

V@

RW

0+d1

6,#8

MO

VE

AA

,@R

W0

MO

VE

A A

,@

RW

0+d1

6

+9

JMP

P@

@R

W1

JMP

P @

@R

W1+

d16

CA

LLP

@@

RW

1C

ALL

P @

@R

W1+

d16

INC

L @R

W1

INC

L@

RW

1+d1

6D

EC

L@

RW

1D

EC

L@

RW

1+d1

6M

OV

LA

,@R

W1

MO

VL

A,

@R

W1+

d16

MO

VL

@R

W1,

AM

OVL

@R

W1+

d16,

AM

OV

@R

W1,

#8

MO

V@

RW

1+d1

6,#8

MO

VE

AA

,@R

W1

MO

VE

A A

,@

RW

1+d1

6

+A

JMP

P@

@R

W2

JMP

P @

@R

W2+

d16

CA

LLP

@@

RW

2C

ALL

P @

@R

W2+

d16

INC

L @R

W2

INC

L@

RW

2+d1

6D

EC

L@

RW

2D

EC

L@

RW

2+d1

6M

OV

LA

,@R

W2

MO

VL

A,

@R

W2+

d16

MO

VL

@R

W2,

AM

OVL

@R

W2+

d16,

AM

OV

@R

W2,

#8

MO

V@

RW

2+d1

6,#8

MO

VE

AA

,@R

W2

MO

VE

A A

,@

RW

2+d1

6

+B

JMP

P@

@R

W3

JMP

P @

@R

W3+

d16

CA

LLP

@@

RW

3C

ALL

P @

@R

W3+

d16

INC

L @R

W3

INC

L@

RW

3+d1

6D

EC

L@

RW

3D

EC

L@

RW

3+d1

6M

OV

LA

,@R

W3

MO

VL

A,

@R

W3+

d16

MO

VL

@R

W3,

AM

OVL

@R

W3+

d16,

AM

OV

@R

W3,

#8

MO

V@

RW

3+d1

6,#8

MO

VE

AA

,@R

W3

MO

VE

A A

,@

RW

3+d1

6

+C

JMP

P@

@R

W0+

JMPP

@@

RW

0+R

W7

CA

LLP

@@

RW

0+C

ALLP

@@

RW

0+R

W7

INC

L@

RW

0+IN

CL

@R

W0+

RW7

DE

CL

@R

W0+

DEC

L@

RW

0+R

W7

MO

VL

A,@

RW

0+M

OVL

A,

@R

W0+

RW7

MO

VL

@R

W0+

,AM

OVL

@RW

0+RW

7,A

MO

V@

RW

0+, #

8M

OV@

RW0+

RW7,

#8M

OV

EA

A,@

RW

0+M

OVE

A A,

@RW

0+R

W7

+D

JMP

P@

@R

W1+

JMPP

@@

RW

1+R

W7

CA

LLP

@@

RW

1+C

ALLP

@@

RW

1+R

W7

INC

L@

RW

1+IN

CL

@R

W1+

RW7

DE

CL

@R

W1+

DEC

L@

RW

1+R

W7

MO

VL

A,@

RW

1+M

OVL

A,

@R

W1+

RW7

MO

VL

@R

W1+

,AM

OVL

@RW

1+RW

7,A

MO

V@

RW

1+, #

8M

OV@

RW1+

RW7,

#8M

OV

EA

A,@

RW

1+M

OVE

A A,

@RW

1+R

W7

+E

JMP

P@

@R

W2+

JMPP

@@

PC+d

16C

ALL

P@

@R

W2+

CAL

LP@

@PC

+d16

INC

L@

RW

2+IN

CL

@P

C+

d16

DE

CL

@R

W2+

DE

CL

@P

C+

d16

MO

VL

A,@

RW

2+M

OV

L A

,@

PC

+d1

6M

OV

L@

RW

2+,A

MO

VL

@P

C+d

16, A

MO

V@

RW

2+, #

8M

OV

@P

C+d

16, #

8M

OV

EA

A,@

RW

2+M

OV

EA

A,

@P

C+

d16

+F

JMP

P@

@R

W3+

JMP

P@

addr

16C

ALL

P@

@R

W3+

CA

LLP

@ad

dr16

INC

L@

RW

3+IN

CL ad

dr16

DE

CL

@R

W3+

DE

CL ad

dr16

MO

VL

A,@

RW

3+M

OV

L A

,ad

dr16

MO

VL

@R

W3+

,AM

OV

Lad

dr16

, AM

OV

@R

W3+

, #8

MO

V addr

16, #

8M

OV

EA

A,@

RW

3+M

OV

EA

A,

addr

16

454



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

RO

LCR

0R

OLC

@R

W0+

d8R

OR

CR

0R

OR

C@

RW

0+d8

INC

R0

INC

@R

W0+

d8D

EC

R0

DE

C@

RW

0+d8

MO

VA

, R0

MO

V

A

,@

RW

0+d8

MO

VR

0, A

MO

V@

RW

0+d8

,AM

OV

X A, R

0M

OV

X

A,

@R

W0+

d8X

CH

A, R

0X

CH

A,

@R

W0+

d8

+1

RO

LCR

1R

OLC

@R

W1+

d8R

OR

CR

1R

OR

C@

RW

1+d8

INC

R1

INC

@R

W1+

d8D

EC

R1

DE

C@

RW

1+d8

MO

VA

, R1

MO

V

A

,@

RW

1+d8

MO

VR

1, A

MO

V@

RW

1+d8

,AM

OV

X A, R

1M

OV

X

A,

@R

W1+

d8X

CH

A, R

1X

CH

A,

@R

W1+

d8

+2

RO

LCR

2R

OLC

@R

W2+

d8R

OR

CR

2R

OR

C@

RW

2+d8

INC

R2

INC

@R

W2+

d8D

EC

R2

DE

C@

RW

2+d8

MO

VA

, R2

MO

V

A

,@

RW

2+d8

MO

VR

2, A

MO

V@

RW

2+d8

,AM

OV

X A, R

2M

OV

X

A,

@R

W2+

d8X

CH

A, R

2X

CH

A,

@R

W2+

d8

+3

RO

LCR

3R

OLC

@R

W3+

d8R

OR

CR

3R

OR

C@

RW

3+d8

INC

R3

INC

@R

W3+

d8D

EC

R3

DE

C@

RW

3+d8

MO

VA

, R3

MO

V

A

,@

RW

3+d8

MO

VR

3, A

MO

V@

RW

3+d8

,AM

OV

X A, R

3M

OV

X

A,

@R

W3+

d8X

CH

A, R

3X

CH

A,

@R

W3+

d8

+4

RO

LCR

4R

OLC

@R

W4+

d8R

OR

CR

4R

OR

C@

RW

4+d8

INC

R4

INC

@R

W4+

d8D

EC

R4

DE

C@

RW

4+d8

MO

VA

, R4

MO

V

A

,@

RW

4+d8

MO

VR

4, A

MO

V@

RW

4+d8

,AM

OV

X A, R

4M

OV

X

A,

@R

W4+

d8X

CH

A, R

4X

CH

A,

@R

W4+

d8

+5

RO

LCR

5R

OLC

@R

W5+

d8R

OR

CR

5R

OR

C@

RW

5+d8

INC

R5

INC

@R

W5+

d8D

EC

R5

DE

C@

RW

5+d8

MO

VA

, R5

MO

V

A

,@

RW

5+d8

MO

VR

5, A

MO

V@

RW

5+d8

,AM

OV

X A, R

5M

OV

X

A,

@R

W5+

d8X

CH

A, R

5X

CH

A,

@R

W5+

d8

+6

RO

LCR

6R

OLC

@R

W6+

d8R

OR

CR

6R

OR

C@

RW

6+d8

INC

R6

INC

@R

W6+

d8D

EC

R6

DE

C@

RW

6+d8

MO

VA

, R6

MO

V

A

,@

RW

6+d8

MO

VR

6, A

MO

V@

RW

6+d8

,AM

OV

X A, R

6M

OV

X

A,

@R

W6+

d8X

CH

A, R

6X

CH

A,

@R

W6+

d8

+7

RO

LCR

7R

OLC

@R

W7+

d8R

OR

CR

7R

OR

C@

RW

7+d8

INC

R7

INC

@R

W7+

d8D

EC

R7

DE

C@

RW

7+d8

MO

VA

, R7

MO

V

A

,@

RW

7+d8

MO

VR

7, A

MO

V@

RW

7+d8

,AM

OV

X A, R

7M

OV

X

A,

@R

W7+

d8X

CH

A, R

7X

CH

A,

@R

W7+

d8

+8

RO

LC @R

W0

RO

LC@

RW

0+d1

6R

OR

C@

RW

0R

OR

C@

RW

0+d1

6IN

C @R

W0

INC

@R

W0+

d16

DE

C @R

W0

DE

C@

RW

0+d1

6M

OV

A,@

RW

0M

OV

A,

@R

W0+

d16

MO

V@

RW

0, A

MO

V@

RW

0+d1

6,A

MO

VX

A,@

RW

0M

OV

X

A,

@R

W0+

d16

XC

HA

,@R

W0

XC

H

A

,@

RW

0+d1

6

+9

RO

LC @R

W1

RO

LC@

RW

1+d1

6R

OR

C@

RW

1R

OR

C@

RW

1+d1

6IN

C @R

W1

INC

@R

W1+

d16

DE

C @R

W1

DE

C@

RW

1+d1

6M

OV

A,@

RW

1M

OV

A,

@R

W1+

d16

MO

V@

RW

1, A

MO

V@

RW

1+d1

6,A

MO

VX

A,@

RW

1M

OV

X

A,

@R

W1+

d16

XC

HA

,@R

W1

XC

H

A

,@

RW

1+d1

6

+A

RO

LC @R

W2

RO

LC@

RW

2+d1

6R

OR

C@

RW

2R

OR

C@

RW

2+d1

6IN

C @R

W2

INC

@R

W2+

d16

DE

C @R

W2

DE

C@

RW

2+d1

6M

OV

A,@

RW

2M

OV

A,

@R

W2+

d16

MO

V@

RW

2, A

MO

V@

RW

2+d1

6,A

MO

VX

A,@

RW

2M

OV

X

A,

@R

W2+

d16

XC

HA

,@R

W2

XC

H

A

,@

RW

2+d1

6

+B

RO

LC @R

W3

RO

LC@

RW

3+d1

6R

OR

C@

RW

3R

OR

C@

RW

3+d1

6IN

C @R

W3

INC

@R

W3+

d16

DE

C @R

W3

DE

C@

RW

3+d1

6M

OV

A,@

RW

3M

OV

A,

@R

W3+

d16

MO

V@

RW

3, A

MO

V@

RW

3+d1

6,A

MO

VX

A,@

RW

3M

OV

X

A,

@R

W3+

d16

XC

HA

,@R

W3

XC

H

A

,@

RW

3+d1

6

+C

RO

LC@

RW

0+R

OLC

@RW

0+R

W7

RO

RC

@R

W0+

RORC

@R

W0+

RW7

INC @

RW

0+IN

C@

RW0+

RW

7D

EC @R

W0+

DEC

@RW

0+R

W7

MO

VA

,@R

W0+

MO

V

A,

@R

W0+

RW7

MO

V@

RW

0+, A

MO

V@

RW0+

RW7,

AM

OV

XA

,@R

W0+

MO

VX

A,@

RW0+

RW

7X

CH

A,@

RW

0+XC

H

A,

@R

W0+

RW7

+D

RO

LC@

RW

1+R

OLC

@RW

1+R

W7

RO

RC

@R

W1+

RORC

@R

W1+

RW7

INC @

RW

1+IN

C@

RW1+

RW

7D

EC @R

W1+

DEC

@RW

1+R

W7

MO

VA

,@R

W1+

MO

V

A,

@R

W1+

RW7

MO

V@

RW

1+, A

MO

V@

RW1+

RW7,

AM

OV

XA

,@R

W1+

MO

VX

A,@

RW1+

RW

7X

CH

A,@

RW

1+XC

H

A,

@R

W1+

RW7

+E

RO

LC@

RW

2+R

OLC

@P

C+

d16

RO

RC

@R

W2+

RO

RC

@P

C+

d16

INC @

RW

2+IN

C@

PC

+d1

6D

EC @R

W2+

DE

C@

PC

+d1

6M

OV

A,@

RW

2+M

OV

A,

@P

C+

d16

MO

V@

RW

2+, A

MO

V@

PC

+d16

, AM

OV

XA

,@R

W2+

MO

VX

A

,@

PC

+d1

6X

CH

A,@

RW

2+X

CH

A,

@P

C+

d16

+FR

OLC

@R

W3+

RO

LC addr

16R

OR

C@

RW

3+R

OR

C addr

16IN

C @R

W3+

INC

addr

16D

EC @R

W3+

DE

C addr

16M

OV

A,@

RW

3+M

OV

A,

addr

16M

OV

@R

W3+

, AM

OV addr

16, A

MO

VX

A,@

RW

3+M

OV

X

A,

addr

16X

CH

A,@

RW

3+X

CH

A,

addr

16

455



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0JM

P @R

W0

JMP

@@

RW

0+d8

CA

LLR

W0

CAL

L@

@RW

0+d8

INC

W RW

0IN

CW

@R

W0+

d8D

EC

W RW

0D

EC

W@

RW

0+d8

MO

VW

A, R

W0

MO

VW

A,

@R

W0+

d8M

OV

WR

W0,

AM

OV

W@

RW

0+d8

,AM

OV

WR

W0,

#16

MO

VW

@R

W0+

d8,#

16X

CH

WA

, RW

0X

CH

W

A,

@R

W0+

d8

+1JM

P @R

W1

JMP

@@

RW

1+d8

CA

LLR

W1

CAL

L@

@RW

1+d8

INC

W RW

1IN

CW

@R

W1+

d8D

EC

W RW

1D

EC

W@

RW

1+d8

MO

VW

A, R

W1

MO

VW

A,

@R

W1+

d8M

OV

WR

W1,

AM

OV

W@

RW

1+d8

,AM

OV

WR

W1,

#16

MO

VW

@R

W1+

d8,#

16X

CH

WA

, RW

1X

CH

W

A,

@R

W1+

d8

+2JM

P @R

W2

JMP

@@

RW

2+d8

CA

LLR

W2

CAL

L@

@RW

2+d8

INC

W RW

2IN

CW

@R

W2+

d8D

EC

W RW

2D

EC

W@

RW

2+d8

MO

VW

A, R

W2

MO

VW

A,

@R

W2+

d8M

OV

WR

W2,

AM

OV

W@

RW

2+d8

,AM

OV

WR

W2,

#16

MO

VW

@R

W2+

d8,#

16X

CH

WA

, RW

2X

CH

W

A,

@R

W2+

d8

+3JM

P @R

W3

JMP

@@

RW

3+d8

CA

LLR

W3

CAL

L@

@RW

3+d8

INC

W RW

3IN

CW

@R

W3+

d8D

EC

W RW

3D

EC

W@

RW

3+d8

MO

VW

A, R

W3

MO

VW

A,

@R

W3+

d8M

OV

WR

W3,

AM

OV

W@

RW

3+d8

,AM

OV

WR

W3,

#16

MO

VW

@R

W3+

d8,#

16X

CH

WA

, RW

3X

CH

W

A,

@R

W3+

d8

+4JM

P @R

W4

JMP

@@

RW

4+d8

CA

LLR

W4

CAL

L@

@RW

4+d8

INC

W RW

4IN

CW

@R

W4+

d8D

EC

W RW

4D

EC

W@

RW

4+d8

MO

VW

A, R

W4

MO

VW

A,

@R

W4+

d8M

OV

WR

W4,

AM

OV

W@

RW

4+d8

,AM

OV

WR

W4,

#16

MO

VW

@R

W4+

d8,#

16X

CH

WA

, RW

4X

CH

W

A,

@R

W4+

d8

+5JM

P @R

W5

JMP

@@

RW

5+d8

CA

LLR

W5

CAL

L@

@RW

5+d8

INC

W RW

5IN

CW

@R

W5+

d8D

EC

W RW

5D

EC

W@

RW

5+d8

MO

VW

A, R

W5

MO

VW

A,

@R

W5+

d8M

OV

WR

W5,

AM

OV

W@

RW

5+d8

,AM

OV

WR

W5,

#16

MO

VW

@R

W5+

d8,#

16X

CH

WA

, RW

5X

CH

W

A,

@R

W5+

d8

+6JM

P @R

W6

JMP

@@

RW

6+d8

CA

LLR

W6

CAL

L@

@RW

6+d8

INC

W RW

6IN

CW

@R

W6+

d8D

EC

W RW

6D

EC

W@

RW

6+d8

MO

VW

A, R

W6

MO

VW

A,

@R

W6+

d8M

OV

WR

W6,

AM

OV

W@

RW

6+d8

,AM

OV

WR

W6,

#16

MO

VW

@R

W6+

d8,#

16X

CH

WA

, RW

6X

CH

W

A,

@R

W6+

d8

+7JM

P @R

W7

JMP

@@

RW

7+d8

CA

LLR

W7

CAL

L@

@RW

7+d8

INC

W RW

7IN

CW

@R

W7+

d8D

EC

W RW

7D

EC

W@

RW

7+d8

MO

VW

A, R

W7

MO

VW

A,

@R

W7+

d8M

OV

WR

W7,

AM

OV

W@

RW

7+d8

,AM

OV

WR

W7,

#16

MO

VW

@R

W7+

d8,#

16X

CH

WA

, RW

7X

CH

W

A,

@R

W7+

d8

+8JM

P@

@R

W0

JMP

@@

RW

0+d1

6C

ALL

@@

RW

0C

ALL

@@

RW

0+d1

6IN

CW

@R

W0

INC

W

@@

RW

0+d1

6D

EC

W@

RW

0D

EC

W@

RW

0+d1

6M

OV

WA

,@R

W0

MO

VW

A,

@R

W0+

d16

MO

VW

@R

W0,

AM

OVW

@RW

0+d1

6,A

MO

VW

@R

W0,

#16

MO

VW@

RW

0+d1

6,#1

6X

CH

WA

,@R

W0

XC

HW

A

,@

RW

0+d1

6

+9JM

P@

@R

W1

JMP

@@

RW

1+d1

6C

ALL

@@

RW

1C

ALL

@@

RW

1+d1

6IN

CW

@R

W1

INC

W

@@

RW

1+d1

6D

EC

W@

RW

1D

EC

W@

RW

1+d1

6M

OV

WA

,@R

W1

MO

VW

A,

@R

W1+

d16

MO

VW

@R

W1,

AM

OVW

@RW

1+d1

6,A

MO

VW

@R

W1,

#16

MO

VW@

RW

1+d1

6,#1

6X

CH

WA

,@R

W1

XC

HW

A

,@

RW

1+d1

6

+A

JMP

@@

RW

2JM

P @

@R

W2+

d16

CA

LL@

@R

W2

CA

LL @

@R

W2+

d16

INC

W@

RW

2IN

CW

@

@R

W2+

d16

DE

CW

@R

W2

DE

CW

@R

W2+

d16

MO

VW

A,@

RW

2M

OV

W A

,@

RW

2+d1

6M

OV

W@

RW

2, A

MO

VW@

RW2+

d16,

AM

OV

W@

RW

2, #

16M

OVW

@R

W2+

d16,

#16

XC

HW

A,@

RW

2X

CH

W

A,

@R

W2+

d16

+B

JMP

@@

RW

3JM

P @

@R

W3+

d16

CA

LL@

@R

W3

CA

LL @

@R

W3+

d16

INC

W@

RW

3IN

CW

@

@R

W3+

d16

DE

CW

@R

W3

DE

CW

@R

W3+

d16

MO

VW

A,@

RW

3M

OV

W A

,@

RW

3+d1

6M

OV

W@

RW

3, A

MO

VW@

RW3+

d16,

AM

OV

W@

RW

3, #

16M

OVW

@R

W3+

d16,

#16

XC

HW

A,@

RW

3X

CH

W

A,

@R

W3+

d16

+C

JMP

@@

RW

0+JM

P @

@R

W0+

RW7

CA

LL@

@R

W0+

CAL

L @

@R

W0+

RW7

INC

W@

RW

0+IN

CW

@

@R

W0+

RW7

DE

CW

@R

W0+

DEC

W@

RW

0+RW

7M

OV

WA

,@R

W0+

MO

VW A

,@

RW

0+RW

7M

OV

W@

RW

0+, A

MO

VW@

RW0+

RW7,

AM

OV

W@

RW

0+, #

16M

OVW

@RW

0+RW

7,#1

6X

CH

WA

,@R

W0+

XCHW

A,

@R

W0+

RW

7

+D

JMP

@@

RW

1+JM

P @

@R

W1+

RW7

CA

LL@

@R

W1+

CAL

L @

@R

W1+

RW7

INC

W@

RW

1+IN

CW

@

@R

W1+

RW7

DE

CW

@R

W1+

DEC

W@

RW

1+RW

7M

OV

WA

,@R

W1+

MO

VW A

,@

RW

1+RW

7M

OV

W@

RW

1+, A

MO

VW@

RW1+

RW7,

AM

OV

W@

RW

1+, #

16M

OVW

@RW

1+RW

7,#1

6X

CH

WA

,@R

W1+

XCHW

A,

@R

W1+

RW

7

+E

JMP

@@

RW

2+JM

P@

@PC

+d16

CA

LL@

@R

W2+

CAL

L@

@PC

+d16

INC

W@

RW

2+IN

CW

@@

PC+d

16D

EC

W@

RW

2+D

EC

W@

PC

+d1

6M

OV

WA

,@R

W2+

MO

VW

A,

@P

C+

d16

MO

VW

@R

W2+

, AM

OV

W@

PC

+d16

, AM

OV

W@

RW

2+, #

16M

OV

W@

PC

+d16

, #16

XC

HW

A,@

RW

2+X

CH

W

A,

@P

C+

d16

+F

JMP

@@

RW

3+JM

P @ad

dr16

CA

LL@

@R

W3+

CA

LL@

addr

16IN

CW

@R

W3+

INC

W addr

16D

EC

W@

RW

3+D

EC

W addr

16M

OV

WA

,@R

W3+

MO

VW

A,

addr

16M

OV

W@

RW

3+, A

MO

VW

addr

16, A

MO

VW

@R

W3+

, #16

MO

VW

addr

16, #

16X

CH

WA

,@R

W3+

XC

HW

A

,ad

dr16

456



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

AD

DA

, R0

AD

D

A

,@

RW

0+d8

SU

BA

, R0

SU

B

A

,@

RW

0+d8

AD

DC A

, R0

AD

DC

A

,@

RW

0+d8

CM

PA

, R0

CM

P

A

,@

RW

0+d8

AN

DA

, R0

AN

D

A

,@

RW

0+d8

OR

A, R

0O

R

A,

@R

W0+

d8X

OR

A, R

0X

OR

A,

@R

W0+

d8D

BN

Z R0,

rD

BN

Z

@R

W0+

d8, r

+1

AD

DA

, R1

AD

D

A

,@

RW

1+d8

SU

BA

, R1

SU

B

A

,@

RW

1+d8

AD

DC A

, R1

AD

DC

A

,@

RW

1+d8

CM

PA

, R1

CM

P

A

,@

RW

1+d8

AN

DA

, R1

AN

D

A

,@

RW

1+d8

OR

A, R

1O

R

A,

@R

W1+

d8X

OR

A, R

1X

OR

A,

@R

W1+

d8D

BN

Z R1,

rD

BN

Z

@R

W1+

d8, r

+2

AD

DA

, R2

AD

D

A

,@

RW

2+d8

SU

BA

, R2

SU

B

A

,@

RW

2+d8

AD

DC A

, R2

AD

DC

A

,@

RW

2+d8

CM

PA

, R2

CM

P

A

,@

RW

2+d8

AN

DA

, R2

AN

D

A

,@

RW

2+d8

OR

A, R

2O

R

A,

@R

W2+

d8X

OR

A, R

2X

OR

A,

@R

W2+

d8D

BN

Z R2,

rD

BN

Z

@R

W2+

d8, r

+3

AD

DA

, R3

AD

D

A

,@

RW

3+d8

SU

BA

, R3

SU

B

A

,@

RW

3+d8

AD

DC A

, R3

AD

DC

A

,@

RW

3+d8

CM

PA

, R3

CM

P

A

,@

RW

3+d8

AN

DA

, R3

AN

D

A

,@

RW

3+d8

OR

A, R

3O

R

A,

@R

W3+

d8X

OR

A, R

3X

OR

A,

@R

W3+

d8D

BN

Z R3,

rD

BN

Z

@R

W3+

d8, r

+4

AD

DA

, R4

AD

D

A

,@

RW

4+d8

SU

BA

, R4

SU

B

A

,@

RW

4+d8

AD

DC A

, R4

AD

DC

A

,@

RW

4+d8

CM

PA

, R4

CM

P

A

,@

RW

4+d8

AN

DA

, R4

AN

D

A

,@

RW

4+d8

OR

A, R

4O

R

A,

@R

W4+

d8X

OR

A, R

4X

OR

A,

@R

W4+

d8D

BN

Z R4,

rD

BN

Z

@R

W4+

d8, r

+5

AD

DA

, R5

AD

D

A

,@

RW

5+d8

SU

BA

, R5

SU

B

A

,@

RW

5+d8

AD

DC A

, R5

AD

DC

A

,@

RW

5+d8

CM

PA

, R5

CM

P

A

,@

RW

5+d8

AN

DA

, R5

AN

D

A

,@

RW

5+d8

OR

A, R

5O

R

A,

@R

W5+

d8X

OR

A, R

5X

OR

A,

@R

W5+

d8D

BN

Z R5,

rD

BN

Z

@R

W5+

d8, r

+6

AD

DA

, R6

AD

D

A

,@

RW

6+d8

SU

BA

, R6

SU

B

A

,@

RW

6+d8

AD

DC A

, R6

AD

DC

A

,@

RW

6+d8

CM

PA

, R6

CM

P

A

,@

RW

6+d8

AN

DA

, R6

AN

D

A

,@

RW

6+d8

OR

A, R

6O

R

A,

@R

W6+

d8X

OR

A, R

6X

OR

A,

@R

W6+

d8D

BN

Z R6,

rD

BN

Z

@R

W6+

d8, r

+7

AD

DA

, R7

AD

D

A

,@

RW

7+d8

SU

BA

, R7

SU

B

A

,@

RW

7+d8

AD

DC A

, R7

AD

DC

A

,@

RW

7+d8

CM

PA

, R7

CM

P

A

,@

RW

7+d8

AN

DA

, R7

AN

D

A

,@

RW

7+d8

OR

A, R

7O

R

A,

@R

W7+

d8X

OR

A, R

7X

OR

A,

@R

W7+

d8D

BN

Z R7,

rD

BN

Z

@R

W7+

d8, r

+8

AD

DA

,@R

W0

AD

D

A

,@

RW

0+d1

6S

UB

A,@

RW

0S

UB

A,

@R

W0+

d16

AD

DC

A,@

RW

0A

DD

C

A,

@R

W0+

d16

CM

PA

,@R

W0

CM

P

A

,@

RW

0+d1

6A

ND

A,@

RW

0A

ND

A,

@R

W0+

d16

OR A,@

RW

0O

R

A,

@R

W0+

d16

XO

RA

,@R

W0

XO

R

A

,@

RW

0+d1

6D

BN

Z@

RW

0, r

DB

NZ

@R

W0+

d16,

r

+9

AD

DA

,@R

W1

AD

D

A

,@

RW

1+d1

6S

UB

A,@

RW

1S

UB

A,

@R

W1+

d16

AD

DC

A,@

RW

1A

DD

C

A,

@R

W1+

d16

CM

PA

,@R

W1

CM

P

A

,@

RW

1+d1

6A

ND

A,@

RW

1A

ND

A,

@R

W1+

d16

OR A,@

RW

1O

R

A,

@R

W1+

d16

XO

RA

,@R

W1

XO

R

A

,@

RW

1+d1

6D

BN

Z@

RW

1, r

DB

NZ

@R

W1+

d16,

r

+AA

DD

A,@

RW

2A

DD

A,

@R

W2+

d16

SU

BA

,@R

W2

SU

B

A

,@

RW

2+d1

6A

DD

CA

,@R

W2

AD

DC

A

,@

RW

2+d1

6C

MP

A,@

RW

2C

MP

A,

@R

W2+

d16

AN

DA

,@R

W2

AN

D

A

,@

RW

2+d1

6O

R A,@

RW

2O

R

A,

@R

W2+

d16

XO

RA

,@R

W2

XO

R

A

,@

RW

2+d1

6D

BN

Z@

RW

2, r

DB

NZ

@R

W2+

d16,

r

+BA

DD

A,@

RW

3A

DD

A,

@R

W3+

d16

SU

BA

,@R

W3

SU

B

A

,@

RW

3+d1

6A

DD

CA

,@R

W3

AD

DC

A

,@

RW

3+d1

6C

MP

A,@

RW

3C

MP

A,

@R

W3+

d16

AN

DA

,@R

W3

AN

D

A

,@

RW

3+d1

6O

R A,@

RW

3O

R

A,

@R

W3+

d16

XO

RA

,@R

W3

XO

R

A

,@

RW

3+d1

6D

BN

Z@

RW

3, r

DB

NZ

@R

W3+

d16,

r

+C

AD

DA

,@R

W0+

ADD

A

,@

RW

0+R

W7

SU

BA

,@R

W0+

SUB

A

,@

RW0+

RW

7A

DD

CA

,@R

W0+

ADD

C

A,

@R

W0+

RW7

CM

PA

,@R

W0+

CM

P

A,

@R

W0+

RW

7A

ND

A,@

RW

0+AN

D

A

,@

RW0+

RW

7O

R A,@

RW

0+O

R

A,@

RW0+

RW

7X

OR

A,@

RW

0+XO

R

A,

@R

W0+

RW7

DB

NZ

@R

W0+

, rD

BN

Z @

RW

0+R

W7,

r

+D

AD

DA

,@R

W1+

ADD

A

,@

RW

1+R

W7

SU

BA

,@R

W1+

SUB

A

,@

RW1+

RW

7A

DD

CA

,@R

W1+

ADD

C

A,

@R

W1+

RW7

CM

PA

,@R

W1+

CM

P

A,

@R

W1+

RW

7A

ND

A,@

RW

1+AN

D

A

,@

RW1+

RW

7O

R A,@

RW

1+O

R

A,@

RW1+

RW

7X

OR

A,@

RW

1+XO

R

A,

@R

W1+

RW7

DB

NZ

@R

W1+

, rD

BN

Z @

RW

1+R

W7,

r

+EA

DD

A,@

RW

2+A

DD

A,

@P

C+

d16

SU

BA

,@R

W2+

SU

B

A

,@

PC

+d1

6A

DD

CA

,@R

W2+

AD

DC

A

,@

PC

+d1

6C

MP

A,@

RW

2+C

MP

A,

@P

C+

d16

AN

DA

,@R

W2+

AN

D

A

,@

PC

+d1

6O

R A,@

RW

2+O

R

A,

@P

C+

d16,

XO

RA

,@R

W2+

XO

R

A

,@

PC

+d1

6D

BN

Z@

RW

2+, r

DB

NZ

@

PC

+d1

6, r

+F

AD

DA

,@R

W3+

AD

DA

, add

r16

SU

BA

,@R

W3+

SU

B

A, a

ddr1

6A

DD

CA

,@R

W3+

AD

DC

A, a

ddr1

6C

MP

A,@

RW

3+C

MP

A, a

ddr1

6A

ND

A,@

RW

3+A

ND

A, a

ddr1

6O

R A,@

RW

3+O

R A, a

ddr1

6X

OR

A,@

RW

3+X

OR

A, a

ddr1

6D

BN

Z@

RW

3+, r

DB

NZ

addr

16, r

457



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

AD

DR

0, A

ADD

@RW

0+d8

, AS

UB

R0,

ASU

B@

RW0+

d8, A

SU

BC A

, R0

SU

BC

A

,@

RW

0+d8

NE

GR

0N

EG

A,

@R

W0+

d8A

ND

R0,

AAN

D@

RW

0+d8

, AO

RR

0, A

OR

@R

W0+

d8, A

XO

RR

0, A

XO

R@

RW

0+d8

, AN

OT

R0

NO

T@

RW

0+d8

+1

AD

DR

1, A

ADD

@RW

1+d8

, AS

UB

R1,

ASU

B@

RW1+

d8, A

SU

BC A

, R1

SU

BC

A

,@

RW

1+d8

NE

GR

1N

EG

A,

@R

W1+

d8A

ND

R1,

AAN

D@

RW

1+d8

, AO

RR

1, A

OR

@R

W1+

d8, A

XO

RR

1, A

XO

R@

RW

1+d8

, AN

OT

R1

NO

T@

RW

1+d8

+2

AD

DR

2, A

ADD

@RW

2+d8

,AS

UB

R2,

ASU

B@

RW2+

d8,A

SU

BC A

, R2

SU

BC

A

,@

RW

2+d8

NE

GR

2N

EG

A,

@R

W2+

d8A

ND

R2,

AAN

D@

RW

2+d8

,AO

RR

2, A

OR

@R

W2+

d8,A

XO

RR

2, A

XO

R@

RW

2+d8

,AN

OT

R2

NO

T@

RW

2+d8

+3

AD

DR

3, A

ADD

@RW

3+d8

, AS

UB

R3,

ASU

B@

RW3+

d8, A

SU

BC A

, R3

SU

BC

A

,@

RW

3+d8

NE

GR

3N

EG

A,

@R

W3+

d8A

ND

R3,

AAN

D@

RW

3+d8

, AO

RR

3, A

OR

@R

W3+

d8, A

XO

RR

3, A

XO

R@

RW

3+d8

, AN

OT

R3

NO

T@

RW

3+d8

+4

AD

DR

4, A

ADD

@RW

4+d8

, AS

UB

R4,

ASU

B@

RW4+

d8, A

SU

BC A

, R4

SU

BC

A

,@

RW

4+d8

NE

GR

4N

EG

A,

@R

W4+

d8A

ND

R4,

AAN

D@

RW

4+d8

, AO

RR

4, A

OR

@R

W4+

d8, A

XO

RR

4, A

XO

R@

RW

4+d8

, AN

OT

R4

NO

T@

RW

4+d8

+5

AD

DR

5, A

ADD

@RW

5+d8

, AS

UB

R5,

ASU

B@

RW5+

d8, A

SU

BC A

, R5

SU

BC

A

,@

RW

5+d8

NE

GR

5N

EG

A,

@R

W5+

d8A

ND

R5,

AAN

D@

RW

5+d8

, AO

RR

5, A

OR

@R

W5+

d8, A

XO

RR

5, A

XO

R@

RW

5+d8

, AN

OT

R5

NO

T@

RW

5+d8

+6

AD

DR

6, A

ADD

@RW

6+d8

, AS

UB

R6,

ASU

B@

RW6+

d8, A

SU

BC A

, R6

SU

BC

A

,@

RW

6+d8

NE

GR

6N

EG

A,

@R

W6+

d8A

ND

R6,

AAN

D@

RW

6+d8

, AO

RR

6, A

OR

@R

W6+

d8, A

XO

RR

6, A

XO

R@

RW

6+d8

, AN

OT

R6

NO

T@

RW

6+d8

+7

AD

DR

7, A

ADD

@RW

7+d8

, AS

UB

R7,

ASU

B@

RW7+

d8, A

SU

BC A

, R7

SU

BC

A

,@

RW

7+d8

NE

GR

7N

EG

A,

@R

W7+

d8A

ND

R7,

AAN

D@

RW

7+d8

, AO

RR

7, A

OR

@R

W7+

d8, A

XO

RR

7, A

XO

R@

RW

7+d8

, AN

OT

R7

NO

T@

RW

7+d8

+8

AD

D@

RW

0, A

ADD

@RW

0+d1

6,A

SU

B@

RW

0, A

SUB

@RW

0+d1

6,A

SU

BC

A, @

RW

0S

UB

C

A,

@R

W0+

d16

NE

G @R

W0

NE

G A

,@

RW

0+d1

6A

ND

@R

W0,

AAN

D@

RW0+

d16,

AO

R@

RW

0, A

OR

@R

W0+

d16,

AX

OR

@R

W0,

AX

OR

@R

W0+

d16,

AN

OT @R

W0

NO

T@

RW

0+d1

6

+9

AD

D@

RW

1, A

ADD

@

R@

RW1+

d16,

AS

UB

@R

W1,

ASU

B@

RW1+

d16,

AS

UB

CA

, @R

W1

SU

BC

A

,@

RW

1+d1

6N

EG @

RW

1N

EG

A,

@R

W1+

d16

AN

D@

RW

1, A

AND

@RW

1+d1

6,A

OR

@R

W1,

AO

R@

RW

1+d1

6,A

XO

R@

RW

1, A

XO

R@

RW

1+d1

6,A

NO

T @R

W1

NO

T@

RW

1+d1

6

+A

AD

D@

RW

2, A

ADD

@

R@

RW2+

d16,

AS

UB

@R

W2,

ASU

B@

RW2+

d16,

AS

UB

CA

, @R

W2

SU

BC

A

,@

RW

2+d1

6N

EG @

RW

2N

EG

A,

@R

W2+

d16

AN

D@

RW

2, A

AND

@RW

2+d1

6,A

OR

@R

W2,

AO

R@

RW

2+d1

6,A

XO

R@

RW

2, A

XO

R@

RW

2+d1

6,A

NO

T @R

W2

NO

T@

RW

2+d1

6

+B

AD

D@

RW

3, A

ADD

@

R@

RW3+

d16,

AS

UB

@R

W3,

ASU

B@

RW3+

d16,

AS

UB

CA

, @R

W3

SU

BC

A

,@

RW

3+d1

6N

EG @

RW

3N

EG

A,

@R

W3+

d16

AN

D@

RW

3, A

AND

@RW

3+d1

6,A

OR

@R

W3,

AO

R@

RW

3+d1

6,A

XO

R@

RW

3, A

XO

R@

RW

3+d1

6,A

NO

T @R

W3

NO

T@

RW

3+d1

6

+C

AD

D@

RW

0+, A

ADD

@

R@

RW

0+R

W7,

AS

UB

@R

W0+

, ASU

B@

RW

0+R

W7,

AS

UB

CA

,@R

W0+

SUBC

A

,@

RW

0+RW

7N

EG

@R

W0+

NEG

A,

@RW

0+R

W7

AND

@R

W0+

, AAN

D@

RW

0+R

W7,

AO

R@

RW

0+, A

OR

@R

W0+

RW

7,A

XO

R@

RW

0+, A

XO

R@

RW

0+R

W7,

AN

OT

@R

W0+

NOT

@RW

0+R

W7

+D

AD

D@

RW

1+, A

ADD

@

R@

RW

1+R

W7,

AS

UB

@R

W1+

, ASU

B@

RW

1+R

W7,

AS

UB

CA

,@R

W1+

SUBC

A

,@

RW

1+RW

7N

EG

@R

W1+

NEG

A,

@RW

1+R

W7

AND

@R

W1+

, AAN

D@

RW

1+R

W7,

AO

R@

RW

1+, A

OR

@R

W1+

RW

7,A

XO

R@

RW

1+, A

XO

R@

RW

1+R

W7,

AN

OT

@R

W1+

NOT

@RW

1+R

W7

+E

AD

D@

RW

2+, A

ADD

@PC

+d16

,AS

UB

@R

W2+

, ASU

B@

PC+d

16,A

SU

BC

A,@

RW

2+S

UB

C

A,

@P

C+

d16

NE

G@

RW

2+N

EG

A,

@P

C+

d16

AND

@R

W2+

, AA

ND

@P

C+d

16,A

OR

@R

W2+

, AO

R@

PC

+d16

,AX

OR

@R

W2+

, AX

OR

@P

C+

d16,

AN

OT

@R

W2+

NO

T@

PC

+d1

6

+F

AD

D@

RW

3+, A

AD

Dad

dr16

, AS

UB

@R

W3+

, AS

UB

addr

16, A

SU

BC

A,@

RW

3+S

UB

C

A,

addr

16N

EG

@R

W3+

NE

G A

,ad

dr16

AND

@R

W3+

, AA

ND

addr

16, A

OR

@R

W3+

, AO

Rad

dr16

, AX

OR

@R

W3+

, AX

OR

addr

16, A

NO

T@

RW

3+N

OT ad

dr16

458



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

AD

DW

A, R

W0

AD

DW

A

,@

RW

0+d8

SU

BW

A, R

W0

SU

BW

A

,@

RW

0+d8

AD

DC

WA

, RW

0A

DD

CW

A,

@R

W0+

d8C

MP

WA

, RW

0C

MP

W A

,@

RW

0+d8

AN

DW

A, R

W0

AN

DW

A

,@

RW

0+d8

OR

W A, R

W0

OR

W

A

,@

RW

0+d8

XO

RW

A, R

W0

XO

RW

A

,@

RW

0+d8

DW

BN

ZR

W0,

rD

WB

NZ

@R

W0+

d8,r

+1

AD

DW

A, R

W1

AD

DW

A

,@

RW

1+d8

SU

BW

A, R

W1

SU

BW

A

,@

RW

1+d8

AD

DC

WA

, RW

1A

DD

CW

A,

@R

W1+

d8C

MP

WA

, RW

1C

MP

W A

,@

RW

1+d8

AN

DW

A, R

W1

AN

DW

A

,@

RW

1+d8

OR

W A, R

W1

OR

W

A

,@

RW

1+d8

XO

RW

A, R

W1

XO

RW

A

,@

RW

1+d8

DW

BN

ZR

W1,

rD

WB

NZ

@R

W1+

d8,r

+2

AD

DW

A, R

W2

AD

DW

A

,@

RW

2+d8

SU

BW

A, R

W2

SU

BW

A

,@

RW

2+d8

AD

DC

WA

, RW

2A

DD

CW

A,

@R

W2+

d8C

MP

WA

, RW

2C

MP

W A

,@

RW

2+d8

AN

DW

A, R

W2

AN

DW

A

,@

RW

2+d8

OR

W A, R

W2

OR

W

A

,@

RW

2+d8

XO

RW

A, R

W2

XO

RW

A

,@

RW

2+d8

DW

BN

ZR

W2,

rD

WB

NZ

@R

W2+

d8,r

+3

AD

DW

A, R

W3

AD

DW

A

,@

RW

3+d8

SU

BW

A, R

W3

SU

BW

A

,@

RW

3+d8

AD

DC

WA

, RW

3A

DD

CW

A,

@R

W3+

d8C

MP

WA

, RW

3C

MP

W A

,@

RW

3+d8

AN

DW

A, R

W3

AN

DW

A

,@

RW

3+d8

OR

W A, R

W3

OR

W

A

,@

RW

3+d8

XO

RW

A, R

W3

XO

RW

A

,@

RW

3+d8

DW

BN

ZR

W3,

rD

WB

NZ

@R

W3+

d8,r

+4

AD

DW

A, R

W4

AD

DW

A

,@

RW

4+d8

SU

BW

A, R

W4

SU

BW

A

,@

RW

4+d8

AD

DC

WA

, RW

4A

DD

CW

A,

@R

W4+

d8C

MP

WA

, RW

4C

MP

W A

,@

RW

4+d8

AN

DW

A, R

W4

AN

DW

A

,@

RW

4+d8

OR

W A, R

W4

OR

W

A

,@

RW

4+d8

XO

RW

A, R

W4

XO

RW

A

,@

RW

4+d8

DW

BN

ZR

W4,

rD

WB

NZ

@R

W4+

d8,r

+5

AD

DW

A, R

W5

AD

DW

A

,@

RW

5+d8

SU

BW

A, R

W5

SU

BW

A

,@

RW

5+d8

AD

DC

WA

, RW

5A

DD

CW

A,

@R

W5+

d8C

MP

WA

, RW

5C

MP

W A

,@

RW

5+d8

AN

DW

A, R

W5

AN

DW

A

,@

RW

5+d8

OR

W A, R

W5

OR

W

A

,@

RW

5+d8

XO

RW

A, R

W5

XO

RW

A

,@

RW

5+d8

DW

BN

ZR

W5,

rD

WB

NZ

@R

W5+

d8,r

+6

AD

DW

A, R

W6

AD

DW

A

,@

RW

6+d8

SU

BW

A, R

W6

SU

BW

A

,@

RW

6+d8

AD

DC

WA

, RW

6A

DD

CW

A,

@R

W6+

d8C

MP

WA

, RW

6C

MP

W A

,@

RW

6+d8

AN

DW

A, R

W6

AN

DW

A

,@

RW

6+d8

OR

W A, R

W6

OR

W

A

,@

RW

6+d8

XO

RW

A, R

W6

XO

RW

A

,@

RW

6+d8

DW

BN

ZR

W6,

rD

WB

NZ

@R

W6+

d8,r

+7

AD

DW

A, R

W7

AD

DW

A

,@

RW

7+d8

SU

BW

A, R

W7

SU

BW

A

,@

RW

7+d8

AD

DC

WA

, RW

7A

DD

CW

A,

@R

W7+

d8C

MP

WA

, RW

7C

MP

W A

,@

RW

7+d8

AN

DW

A, R

W7

AN

DW

A

,@

RW

7+d8

OR

W A, R

W7

OR

W

A

,@

RW

7+d8

XO

RW

A, R

W7

XO

RW

A

,@

RW

7+d8

DW

BN

ZR

W7,

rD

WB

NZ

@R

W7+

d8,r

+8

AD

DW

A,@

RW

0A

DD

W

A,

@R

W0+

d16

SU

BW

A,@

RW

0S

UB

W

A,

@R

W0+

d16

AD

DC

WA

,@R

W0

AD

DC

W A

,@

RW

0+d1

6C

MP

WA

,@R

W0

CM

PW

A,

@R

W0+

d16

AN

DW

A,@

RW

0A

ND

W

A,

@R

W0+

d16

OR

WA

,@R

W0

OR

W

A

,@

RW

0+d1

6X

OR

WA

,@R

W0

XO

RW

A

,@

RW

0+d1

6D

WB

NZ

@R

W0,

rD

WBN

Z@

RW

0+d1

6,r

+9

AD

DW

A,@

RW

1A

DD

W

A,

@R

W1+

d16

SU

BW

A,@

RW

1S

UB

W

A,

@R

W1+

d16

AD

DC

WA

,@R

W1

AD

DC

W A

,@

RW

1+d1

6C

MP

WA

,@R

W1

CM

PW

A,

@R

W1+

d16

AN

DW

A,@

RW

1A

ND

W

A,

@R

W1+

d16

OR

WA

,@R

W1

OR

W

A

,@

RW

1+d1

6X

OR

WA

,@R

W1

XO

RW

A

,@

RW

1+d1

6D

WB

NZ

@R

W1,

rD

WBN

Z@

RW

1+d1

6,r

+A

AD

DW

A,@

RW

2A

DD

W

A,

@R

W2+

d16

SU

BW

A,@

RW

2S

UB

W

A,

@R

W2+

d16

AD

DC

WA

,@R

W2

AD

DC

W A

,@

RW

2+d1

6C

MP

WA

,@R

W2

CM

PW

A,

@R

W2+

d16

AN

DW

A,@

RW

2A

ND

W

A,

@R

W2+

d16

OR

WA

,@R

W2

OR

W

A

,@

RW

2+d1

6X

OR

WA

,@R

W2

XO

RW

A

,@

RW

2+d1

6D

WB

NZ

@R

W2,

rD

WBN

Z@

RW

2+d1

6,r

+B

AD

DW

A,@

RW

3A

DD

W

A,

@R

W3+

d16

SU

BW

A,@

RW

3S

UB

W

A,

@R

W3+

d16

AD

DC

WA

,@R

W3

AD

DC

W A

,@

RW

3+d1

6C

MP

WA

,@R

W3

CM

PW

A,

@R

W3+

d16

AN

DW

A,@

RW

3A

ND

W

A,

@R

W3+

d16

OR

WA

,@R

W3

OR

W

A

,@

RW

3+d1

6X

OR

WA

,@R

W3

XO

RW

A

,@

RW

3+d1

6D

WB

NZ

@R

W3,

rD

WBN

Z@

RW

3+d1

6,r

+C

AD

DW

A,@

RW

0+AD

DW

A,

@R

W0+

RW7

SU

BW

A,@

RW

0+SU

BW

A,@

RW

0+R

W7

AD

DC

WA

,@R

W0+

ADD

CW A

,@

RW0+

RW

7C

MP

WA

,@R

W0+

CM

PW A

,@

RW0+

RW

7A

ND

WA

,@R

W0+

ANDW

A,

@R

W0+

RW

7O

RW

A,@

RW

0+O

RW

A

,@

RW0+

RW

7X

OR

WA

,@R

W0+

XOR

W

A,@

RW

0+RW

7D

WB

NZ

@R

W0+

, rD

WBN

Z@

RW

0+RW

7,r

+D

AD

DW

A,@

RW

1+AD

DW

A,

@R

W1+

RW7

SU

BW

A,@

RW

1+SU

BW

A,@

RW

1+R

W7

AD

DC

WA

,@R

W1+

ADD

CW A

,@

RW1+

RW

7C

MP

WA

,@R

W1+

CM

PW A

,@

RW1+

RW

7A

ND

WA

,@R

W1+

ANDW

A,

@R

W1+

RW

7O

RW

A,@

RW

1+O

RW

A

,@

RW1+

RW

7X

OR

WA

,@R

W1+

XOR

W

A,@

RW

1+RW

7D

WB

NZ

@R

W1+

, rD

WBN

Z@

RW

1+RW

7,r

+E

AD

DW

A,@

RW

2+A

DD

W

A,

@P

C+

d16

SU

BW

A,@

RW

2+S

UB

W

A,

@P

C+

d16

AD

DC

WA

,@R

W2+

AD

DC

W A

,@

PC

+d1

6C

MP

WA

,@R

W2+

CM

PW

A,

@P

C+

d16

AN

DW

A,@

RW

2+A

ND

W

A,

@P

C+

d16

OR

WA

,@R

W2+

OR

W

A

,@

PC

+d1

6,X

OR

WA

,@R

W2+

XO

RW

A

,@

PC

+d1

6D

WB

NZ

@R

W2+

, rD

WB

NZ

@P

C+

d16,

r

+F

AD

DW

A,@

RW

3+A

DD

W

A,

addr

16

SU

BW

A,@

RW

3+S

UB

W

A,

addr

16

AD

DC

WA

,@R

W3+

AD

DC

W A

,ad

dr 1

6C

MP

WA

,@R

W3+

CM

PW

A,

addr

16

AN

DW

A,@

RW

3+A

ND

W

A,

addr

16

OR

WA

,@R

W3+

OR

W

A

,ad

dr16

XO

RW

A,@

RW

3+X

OR

W

A,

addr

16

DW

BN

Z@

RW

3+, r

DW

BN

Zad

dr16

, r

459



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

AD

DW

RW

0, A

ADD

W@

RW

0+d8

, AS

UB

WR

W0,

ASU

BW@

RW

0+d8

, AS

UB

CW

A, R

W0

SU

BC

W A

,@

RW

0+d8

NE

GW R

W0

NE

GW

@R

W0+

d8A

ND

WR

W0,

AAN

DW

@RW

0+d8

, AO

RW RW

0, A

ORW

@RW

0+d8

, AX

OR

WR

W0,

AXO

RW

@R

W0+

d8, A

NO

TW R

W0

NO

TW

@R

W0+

d8

+1

AD

DW

RW

1, A

ADD

W@

RW

1+d8

, AS

UB

WR

W1,

ASU

BW@

RW

1+d8

, AS

UB

CW

A, R

W1

SU

BC

W A

,@

RW

1+d8

NE

GW R

W1

NE

GW

@R

W1+

d8A

ND

WR

W1,

AAN

DW

@RW

1+d8

, AO

RW RW

1, A

ORW

@RW

1+d8

, AX

OR

WR

W1,

AXO

RW

@R

W1+

d8, A

NO

TW R

W1

NO

TW

@R

W1+

d8

+2

AD

DW

RW

2, A

ADD

W@

RW

2+d8

,AS

UB

WR

W2,

ASU

BW@

RW

2+d8

,AS

UB

CW

A, R

W2

SU

BC

W A

,@

RW

2+d8

NE

GW R

W2

NE

GW

@R

W2+

d8A

ND

WR

W2,

AAN

DW

@RW

2+d8

,AO

RW RW

2, A

OR

W@

RW

2+d8

,AX

OR

WR

W2,

AXO

RW

@R

W2+

d8,A

NO

TW R

W2

NO

TW

@R

W2+

d8

+3

AD

DW

RW

3, A

ADD

W@

RW

3+d8

, AS

UB

WR

W3,

ASU

BW@

RW

3+d8

, AS

UB

CW

A, R

W3

SU

BC

W A

,@

RW

3+d8

NE

GW R

W3

NE

GW

@R

W3+

d8A

ND

WR

W3,

AAN

DW

@RW

3+d8

, AO

RW RW

3, A

ORW

@RW

3+d8

, AX

OR

WR

W3,

AXO

RW

@R

W3+

d8, A

NO

TW R

W3

NO

TW

@R

W3+

d8

+4

AD

DW

RW

4, A

ADD

W@

RW

4+d8

, AS

UB

WR

W4,

ASU

BW@

RW

4+d8

, AS

UB

CW

A, R

W4

SU

BC

W A

,@

RW

4+d8

NE

GW R

W4

NE

GW

@R

W4+

d8A

ND

WR

W4,

AAN

DW

@RW

4+d8

, AO

RW RW

4, A

ORW

@RW

4+d8

, AX

OR

WR

W4,

AXO

RW

@R

W4+

d8, A

NO

TW R

W4

NO

TW

@R

W4+

d8

+5

AD

DW

RW

5, A

ADD

W@

RW

5+d8

, AS

UB

WR

W5,

ASU

BW@

RW

5+d8

, AS

UB

CW

A, R

W5

SU

BC

W A

,@

RW

5+d8

NE

GW R

W5

NE

GW

@R

W5+

d8A

ND

WR

W5,

AAN

DW

@RW

5+d8

, AO

RW RW

5, A

ORW

@RW

5+d8

, AX

OR

WR

W5,

AXO

RW

@R

W5+

d8, A

NO

TW R

W5

NO

TW

@R

W5+

d8

+6

AD

DW

RW

6, A

ADD

W@

RW

6+d8

, AS

UB

WR

W6,

ASU

BW@

RW

6+d8

, AS

UB

CW

A, R

W6

SU

BC

W A

,@

RW

6+d8

NE

GW R

W6

NE

GW

@R

W6+

d8A

ND

WR

W6,

AAN

DW

@RW

6+d8

, AO

RW RW

6, A

ORW

@RW

6+d8

, AX

OR

WR

W6,

AXO

RW

@R

W6+

d8, A

NO

TW R

W6

NO

TW

@R

W6+

d8

+7

AD

DW

RW

7, A

ADD

W@

RW

7+d8

, AS

UB

WR

W7,

ASU

BW@

RW

7+d8

, AS

UB

CW

A, R

W7

SU

BC

W A

,@

RW

7+d8

NE

GW R

W7

NE

GW

@R

W7+

d8A

ND

WR

W7,

AAN

DW

@RW

7+d8

, AO

RW RW

7, A

ORW

@RW

7+d8

, AX

OR

WR

W7,

AXO

RW

@R

W7+

d8, A

NO

TW R

W7

NO

TW

@R

W7+

d8

+8

AD

DW

@R

W0,

AAD

DW

@RW

0+d1

6,A

SU

BW

@R

W0,

ASU

BW@

RW

0+d1

6,A

SU

BC

WA

, @R

W0

SU

BC

W A

,@

RW

0+d1

6N

EG

W@

RW

0N

EG

W@

RW

0+d1

6A

ND

W@

RW

0, A

AND

W@

RW0+

d16,

AO

RW

@R

W0,

AO

RW

@R

W0+

d16,

AX

OR

W@

RW

0, A

XOR

W@

RW

0+d1

6,A

NO

TW

@R

W0

NO

TW@

RW

0+d1

6

+9

AD

DW

@R

W1,

AAD

DW

@RW

1+d1

6,A

SU

BW

@R

W1,

ASU

BW@

RW

1+d1

6,A

SU

BC

WA

, @R

W1

SU

BC

W A

,@

RW

1+d1

6N

EG

W@

RW

1N

EG

W@

RW

1+d1

6A

ND

W@

RW

1, A

AND

W@

RW1+

d16,

AO

RW

@R

W1,

AO

RW

@R

W1+

d16,

AX

OR

W@

RW

1, A

XOR

W@

RW

1+d1

6,A

NO

TW

@R

W1

NO

TW@

RW

1+d1

6

+A

AD

DW

@R

W2,

AAD

DW

@RW

2+d1

6,A

SU

BW

@R

W2,

ASU

BW@

RW

2+d1

6,A

SU

BC

WA

, @R

W2

SU

BC

W A

,@

RW

2+d1

6N

EG

W@

RW

2N

EG

W@

RW

2+d1

6A

ND

W@

RW

2, A

AND

W@

RW2+

d16,

AO

RW

@R

W2,

AO

RW@

RW2+

d16,

AX

OR

W@

RW

2, A

XOR

W@

RW

2+d1

6,A

NO

TW

@R

W2

NO

TW@

RW

2+d1

6

+B

AD

DW

@R

W3,

AAD

DW

@RW

3+d1

6,A

SU

BW

@R

W3,

ASU

BW@

RW

3+d1

6,A

SU

BC

WA

, @R

W3

SU

BC

W A

,@

RW

3+d1

6N

EG

W@

RW

3N

EG

W@

RW

3+d1

6A

ND

W@

RW

3, A

AND

W@

RW3+

d16,

AO

RW

@R

W3,

AO

RW@

RW3+

d16,

AX

OR

W@

RW

3, A

XOR

W@

RW

3+d1

6,A

NO

TW

@R

W3

NO

TW@

RW

3+d1

6

+C

ADD

W@

RW

0+, A

ADD

W@

RW

0+R

W7,

AS

UB

W@

RW

0+, A

SUBW

@R

W0+

RW

7,A

SU

BC

WA

,@R

W0+

SUBC

W A

,@

RW

0+RW

7N

EG

W@

RW

0+NE

GW

@R

W0+

RW7

AN

DW

@R

W0+

, AAN

DW

@R

W0+

RW

7,A

OR

W@

RW

0+, A

OR

W@

RW

0+R

W7,

AX

OR

W@

RW

0+, A

XO

RW

@R

W0+

RW

7,A

NO

TW

@R

W0+

NOTW

@R

W0+

RW7

+D

ADD

W@

RW

1+, A

ADD

W@

RW

1+R

W7,

AS

UB

W@

RW

1+, A

SUBW

@R

W1+

RW

7,A

SU

BC

WA

,@R

W1+

SUBC

W A

,@

RW

1+RW

7N

EG

W@

RW

1+NE

GW

@R

W1+

RW7

AN

DW

@R

W1+

, AAN

DW

@R

W1+

RW

7,A

OR

W@

RW

1+, A

OR

W@

RW

1+R

W7,

AX

OR

W@

RW

1+, A

XO

RW

@R

W1+

RW

7,A

NO

TW

@R

W1+

NOTW

@R

W1+

RW7

+E

ADD

W@

RW

2+, A

ADD

W@

PC+d

16,A

SU

BW

@R

W2+

, ASU

BW@

PC+d

16,A

SU

BC

WA

,@R

W2+

SU

BC

W A

,@

PC

+d1

6N

EG

W@

RW

2+N

EG

W@

PC

+d1

6A

ND

W@

RW

2+, A

AN

DW

@P

C+d

16,A

OR

W@

RW

2+, A

OR

W@

PC

+d16

,AX

OR

W@

RW

2+, A

XO

RW

@P

C+d

16,A

NO

TW

@R

W2+

NO

TW

@P

C+

d16

+F

ADD

W@

RW

3+, A

AD

DW

addr

16, A

SU

BW

@R

W3+

, AS

UB

Wad

dr16

, AS

UB

CW

A,@

RW

3+S

UB

CW

A,

addr

16N

EG

W@

RW

3+N

EG

W addr

16A

ND

W@

RW

3+, A

AN

DW

addr

16, A

OR

W@

RW

3+, A

OR

Wad

dr16

, AX

OR

W@

RW

3+, A

XO

RW

addr

16, A

NO

TW

@R

W3+

NO

TW ad

dr16

460



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MU

LU A, R

0M

ULU

A

,@

RW

0+d8

MU

LUW

A, R

W0

MU

LUW

A,

@R

W0+

d8M

UL A

, R0

MU

L

A,

@R

W0+

d8M

ULW A, R

W0

MU

LW A

,@

RW

0+d8

DIV

U A, R

0D

IVU

A,

@R

W0+

d8D

IVU

WA

, RW

0D

IVU

W

A,

@R

W0+

d8D

IVA

, R0

DIV

A

,@

RW

0+d8

DIV

W A, R

W0

DIV

W

A,

@R

W0+

d8

+1

MU

LU A, R

1M

ULU

A

,@

RW

1+d8

MU

LUW

A, R

W1

MU

LUW

A,

@R

W1+

d8M

UL A

, R1

MU

L

A,

@R

W1+

d8M

ULW A, R

W1

MU

LW A

,@

RW

1+d8

DIV

U A, R

1D

IVU

A,

@R

W1+

d8D

IVU

WA

, RW

1D

IVU

W

A,

@R

W1+

d8D

IVA

, R1

DIV

A

,@

RW

1+d8

DIV

W A, R

W1

DIV

W

A,

@R

W1+

d8

+2

MU

LU A, R

2M

ULU

A

,@

RW

2+d8

MU

LUW

A, R

W2

MU

LUW

A,

@R

W2+

d8M

UL A

, R2

MU

L

A,

@R

W2+

d8M

ULW A, R

W2

MU

LW A

,@

RW

2+d8

DIV

U A, R

2D

IVU

A,

@R

W2+

d8D

IVU

WA

, RW

2D

IVU

W

A,

@R

W2+

d8D

IVA

, R2

DIV

A

,@

RW

2+d8

DIV

W A, R

W2

DIV

W

A,

@R

W2+

d8

+3

MU

LU A, R

3M

ULU

A

,@

RW

3+d8

MU

LUW

A, R

W3

MU

LUW

A,

@R

W3+

d8M

UL A

, R3

MU

L

A,

@R

W3+

d8M

ULW A, R

W3

MU

LW A

,@

RW

3+d8

DIV

U A, R

3D

IVU

A,

@R

W3+

d8D

IVU

WA

, RW

3D

IVU

W

A,

@R

W3+

d8D

IVA

, R3

DIV

A

,@

RW

3+d8

DIV

W A, R

W3

DIV

W

A,

@R

W3+

d8

+4

MU

LU A, R

4M

ULU

A

,@

RW

4+d8

MU

LUW

A, R

W4

MU

LUW

A,

@R

W4+

d8M

UL A

, R4

MU

L

A,

@R

W4+

d8M

ULW A, R

W4

MU

LW A

,@

RW

4+d8

DIV

U A, R

4D

IVU

A,

@R

W4+

d8D

IVU

WA

, RW

4D

IVU

W

A,

@R

W4+

d8D

IVA

, R4

DIV

A

,@

RW

4+d8

DIV

W A, R

W4

DIV

W

A,

@R

W4+

d8

+5

MU

LU A, R

5M

ULU

A

,@

RW

5+d8

MU

LUW

A, R

W5

MU

LUW

A,

@R

W5+

d8M

UL A

, R5

MU

L

A,

@R

W5+

d8M

ULW A, R

W5

MU

LW A

,@

RW

5+d8

DIV

U A, R

5D

IVU

A,

@R

W5+

d8D

IVU

WA

, RW

5D

IVU

W

A,

@R

W5+

d8D

IVA

, R5

DIV

A

,@

RW

5+d8

DIV

W A, R

W5

DIV

W

A,

@R

W5+

d8

+6

MU

LU A, R

6M

ULU

A

,@

RW

6+d8

MU

LUW

A, R

W6

MU

LUW

A,

@R

W6+

d8M

UL A

, R6

MU

L

A,

@R

W6+

d8M

ULW A, R

W6

MU

LW A

,@

RW

6+d8

DIV

U A, R

6D

IVU

A,

@R

W6+

d8D

IVU

WA

, RW

6D

IVU

W

A,

@R

W6+

d8D

IVA

, R6

DIV

A

,@

RW

6+d8

DIV

W A, R

W6

DIV

W

A,

@R

W6+

d8

+7

MU

LU A, R

7M

ULU

A

,@

RW

7+d8

MU

LUW

A, R

W7

MU

LUW

A,

@R

W7+

d8M

UL A

, R7

MU

L

A,

@R

W7+

d8M

ULW A, R

W7

MU

LW A

,@

RW

7+d8

DIV

U A, R

7D

IVU

A,

@R

W7+

d8D

IVU

WA

, RW

7D

IVU

W

A,

@R

W7+

d8D

IVA

, R7

DIV

A

,@

RW

7+d8

DIV

W A, R

W7

DIV

W

A,

@R

W7+

d8

+8

MU

LUA

,@R

W0

MU

LU

A,

@R

W0+

d16

MU

LUW

A,@

RW

0M

ULU

W A

,@

RW

0+d1

6M

UL

A, @

RW

0M

UL

A

,@

RW

0+d1

6M

ULW

A,@

RW

0M

ULW

A,

@R

W0+

d16

DIV

UA

,@R

W0

DIV

U

A

,@

RW

0+d1

6D

IVU

WA

,@R

W0

DIV

UW

A

,@

RW

0+d1

6D

IV A,@

RW

0D

IV

A,

@R

W0+

d16

DIV

WA

,@R

W0

DIV

W

A,

@R

W0+

d16

+9

MU

LUA

,@R

W1

MU

LU

A,

@R

W1+

d16

MU

LUW

A,@

RW

1M

ULU

W A

,@

RW

1+d1

6M

UL

A, @

RW

1M

UL

A

,@

RW

1+d1

6M

ULW

A,@

RW

1M

ULW

A,

@R

W1+

d16

DIV

UA

,@R

W1

DIV

U

A

,@

RW

1+d1

6D

IVU

WA

,@R

W1

DIV

UW

A

,@

RW

1+d1

6D

IV A,@

RW

1D

IV

A,

@R

W1+

d16

DIV

WA

,@R

W1

DIV

W

A,

@R

W1+

d16

+A

MU

LUA

,@R

W2

MU

LU

A,

@R

W2+

d16

MU

LUW

A,@

RW

2M

ULU

W A

,@

RW

2+d1

6M

UL

A, @

RW

2M

UL

A

,@

RW

2+d1

6M

ULW

A,@

RW

2M

ULW

A,

@R

W2+

d16

DIV

UA

,@R

W2

DIV

U

A

,@

RW

2+d1

6D

IVU

WA

,@R

W2

DIV

UW

A

,@

RW

2+d1

6D

IV A,@

RW

2D

IV

A,

@R

W2+

d16

DIV

WA

,@R

W2

DIV

W

A,

@R

W2+

d16

+B

MU

LUA

,@R

W3

MU

LU

A,

@R

W3+

d16

MU

LUW

A,@

RW

3M

ULU

W A

,@

RW

3+d1

6M

UL

A, @

RW

3M

UL

A

,@

RW

3+d1

6M

ULW

A,@

RW

3M

ULW

A,

@R

W3+

d16

DIV

UA

,@R

W3

DIV

U

A

,@

RW

3+d1

6D

IVU

WA

,@R

W3

DIV

UW

A

,@

RW

3+d1

6D

IV A,@

RW

3D

IV

A,

@R

W3+

d16

DIV

WA

,@R

W3

DIV

W

A,

@R

W3+

d16

+C

MU

LUA

,@R

W0+

MU

LU

A,

@R

W0+

RW

7M

ULU

WA

,@R

W0+

MU

LUW

A,

@R

W0+

RW

7M

UL

A,@

RW

0+M

UL

A

,@

RW

0+R

W7

MU

LWA

,@R

W0+

MUL

W A

,@

RW

0+RW

7D

IVU

A,@

RW

0+DI

VU

A,

@RW

0+R

W7

DIV

UW

A,@

RW

0+DI

VUW

A,

@R

W0+

RW7

DIV A,@

RW

0+D

IV

A,

@R

W0+

RW

7D

IVW

A,@

RW

0+DI

VW

A,

@R

W0+

RW7

+D

MU

LUA

,@R

W1+

MU

LU

A,

@R

W1+

RW

7M

ULU

WA

,@R

W1+

MU

LUW

A,

@R

W1+

RW

7M

UL

A,@

RW

1+M

UL

A

,@

RW

1+R

W7

MU

LWA

,@R

W1+

MUL

W A

,@

RW

1+RW

7D

IVU

A,@

RW

1+DI

VU

A,

@RW

1+R

W7

DIV

UW

A,@

RW

1+DI

VUW

A,

@R

W1+

RW7

DIV A,@

RW

1+D

IV

A,

@R

W1+

RW

7D

IVW

A,@

RW

1+DI

VW

A,

@R

W1+

RW7

+E

MU

LUA

,@R

W2+

MU

LU

A,

@P

C+

d16

MU

LUW

A,@

RW

2+M

ULU

W A

,@

PC

+d1

6M

UL

A,@

RW

2+M

UL

A

,@

PC

+d1

6M

ULW

A,@

RW

2+M

ULW

A,

@P

C+

d16

DIV

UA

,@R

W2+

DIV

U

A

,@

PC

+d1

6D

IVU

WA

,@R

W2+

DIV

UW

A

,@

PC

+d1

6D

IV A,@

RW

2+D

IV

A,

@P

C+

d16

DIV

WA

,@R

W2+

DIV

W

A,

@P

C+

d16

+F

MU

LUA

, @R

W3+

MU

LU

A,

addr

16M

ULU

WA

,@R

W3+

MU

LUW

A,

addr

16M

UL

A,@

RW

3+M

UL

A

,ad

dr16

MU

LWA

,@R

W3+

MU

LW A

,ad

dr16

DIV

UA

,@R

W3+

DIV

U

A

,ad

dr16

DIV

UW

A,@

RW

3+D

IVU

W

A,

addr

16D

IV A,@

RW

3+D

IV

A,

addr

16D

IVW

A,@

RW

3+D

IVW

A

,ad

dr16

461


Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

VE

AR

W0,

RW

0M

OVE

A R

W0

,@R

W0+

d8M

OV

EA

RW

1,R

W0

MO

VEA

RW1

,@RW

0+d8

MO

VE

AR

W2,

RW

0M

OVE

A RW

2,@

RW0+

d8M

OV

EA

RW

3,R

W0

MO

VEA

RW3

,@RW

0+d8

MO

VE

AR

W4,

RW

0M

OVE

A RW

4,@

RW0+

d8M

OV

EA

RW

5,R

W0

MO

VE

A R

W5

,@R

W0+

d8M

OV

EA

RW

6,R

W0

MO

VEA

RW6

,@RW

0+d8

MO

VE

AR

W7,

RW

0M

OVE

A RW

7,@

RW0+

d8

+1

MO

VE

AR

W0,

RW

1M

OVE

A R

W0

,@R

W1+

d8M

OV

EA

RW

1,R

W1

MO

VEA

RW1

,@RW

1+d8

MO

VE

AR

W2,

RW

1M

OVE

A RW

2,@

RW1+

d8M

OV

EA

RW

3,R

W1

MO

VEA

RW3

,@RW

1+d8

MO

VE

AR

W4,

RW

1M

OVE

A RW

4,@

RW1+

d8M

OV

EA

RW

5,R

W1

MO

VE

A R

W5

,@R

W1+

d8M

OV

EA

RW

6,R

W1

MO

VEA

RW6

,@RW

1+d8

MO

VE

AR

W7,

RW

1M

OVE

A RW

7,@

RW1+

d8

+2

MO

VE

AR

W0,

RW

2M

OVE

A R

W0

,@R

W2+

d8M

OV

EA

RW

1,R

W2

MO

VEA

RW1

,@RW

2+d8

MO

VE

AR

W2,

RW

2M

OVE

A RW

2,@

RW2+

d8M

OV

EA

RW

3,R

W2

MO

VEA

RW3

,@RW

2+d8

MO

VE

AR

W4,

RW

2M

OVE

A RW

4,@

RW2+

d8M

OV

EA

RW

5,R

W2

MO

VE

A R

W5

,@R

W2+

d8M

OV

EA

RW

6,R

W2

MO

VEA

RW6

,@RW

2+d8

MO

VE

AR

W7,

RW

2M

OVE

A RW

7,@

RW2+

d8

+3

MO

VE

AR

W0,

RW

3M

OVE

A R

W0

,@R

W3+

d8M

OV

EA

RW

1,R

W3

MO

VEA

RW1

,@RW

3+d8

MO

VE

AR

W2,

RW

3M

OVE

A RW

2,@

RW3+

d8M

OV

EA

RW

3,R

W3

MO

VEA

RW3

,@RW

3+d8

MO

VE

AR

W4,

RW

3M

OVE

A RW

4,@

RW3+

d8M

OV

EA

RW

5,R

W3

MO

VE

A R

W5

,@R

W3+

d8M

OV

EA

RW

6,R

W3

MO

VEA

RW6

,@RW

3+d8

MO

VE

AR

W7,

RW

3M

OVE

A RW

7,@

RW3+

d8

+4

MO

VE

AR

W0,

RW

4M

OVE

A R

W0

,@R

W4+

d8M

OV

EA

RW

1,R

W4

MO

VEA

RW1

,@RW

4+d8

MO

VE

AR

W2,

RW

4M

OVE

A RW

2,@

RW4+

d8M

OV

EA

RW

3,R

W4

MO

VEA

RW3

,@RW

4+d8

MO

VE

AR

W4,

RW

4M

OVE

A RW

4,@

RW4+

d8M

OV

EA

RW

5,R

W4

MO

VE

A R

W5

,@R

W4+

d8M

OV

EA

RW

6,R

W4

MO

VEA

RW6

,@RW

4+d8

MO

VE

AR

W7,

RW

4M

OVE

A RW

7,@

RW4+

d8

+5

MO

VE

AR

W0,

RW

5M

OVE

A R

W0

,@R

W5+

d8M

OV

EA

RW

1,R

W5

MO

VEA

RW1

,@RW

5+d8

MO

VE

AR

W2,

RW

5M

OVE

A RW

2,@

RW5+

d8M

OV

EA

RW

3,R

W5

MO

VEA

RW3

,@RW

5+d8

MO

VE

AR

W4,

RW

5M

OVE

A RW

4,@

RW5+

d8M

OV

EA

RW

5,R

W5

MO

VE

A R

W5

,@R

W5+

d8M

OV

EA

RW

6,R

W5

MO

VEA

RW6

,@RW

5+d8

MO

VE

AR

W7,

RW

5M

OVE

A RW

7,@

RW5+

d8

+6

MO

VE

AR

W0,

RW

6M

OVE

A R

W0

,@R

W6+

d8M

OV

EA

RW

1,R

W6

MO

VEA

RW1

,@RW

6+d8

MO

VE

AR

W2,

RW

6M

OVE

A RW

2,@

RW6+

d8M

OV

EA

RW

3,R

W6

MO

VEA

RW3

,@RW

6+d8

MO

VE

AR

W4,

RW

6M

OVE

A RW

4,@

RW6+

d8M

OV

EA

RW

5,R

W6

MO

VE

A R

W5

,@R

W6+

d8M

OV

EA

RW

6,R

W6

MO

VEA

RW6

,@RW

6+d8

MO

VE

AR

W7,

RW

6M

OVE

A RW

7,@

RW6+

d8

+7

MO

VE

AR

W0,

RW

7M

OVE

A R

W0

,@R

W7+

d8M

OV

EA

RW

1,R

W7

MO

VEA

RW1

,@RW

7+d8

MO

VE

AR

W2,

RW

7M

OVE

A RW

2,@

RW7+

d8M

OV

EA

RW

3,R

W7

MO

VEA

RW3

,@RW

7+d8

MO

VE

AR

W4,

RW

7M

OVE

A RW

4,@

RW7+

d8M

OV

EA

RW

5,R

W7

MO

VE

A R

W5

,@R

W7+

d8M

OV

EA

RW

6,R

W7

MO

VEA

RW6

,@RW

7+d8

MO

VE

AR

W7,

RW

7M

OVE

A RW

7,@

RW7+

d8

+8

MO

VE

AR

W0,

@R

W0

MO

VEA

RW

0,@

RW

0+d1

6M

OV

EA

RW

1,@

RW

0M

OVE

A RW

1,@

RW0+

d16

MO

VE

AR

W2,

@R

W0

MO

VEA

RW2

,@RW

0+d1

6M

OV

EA

RW

3,@

RW

0M

OVE

A RW

3,@

RW0+

d16

MO

VE

AR

W4,

@R

W0

MO

VEA

RW4

,@RW

0+d1

6M

OV

EA

RW

5,@

RW

0M

OV

EA

RW

5,@

RW

0+d1

6M

OV

EA

RW

6,@

RW

0M

OVE

A RW

6,@

RW0+

d16

MO

VE

AR

W7,

@R

W0

MO

VEA

RW7

,@RW

0+d1

6

+9

MO

VE

AR

W0,

@R

W1

MO

VEA

RW

0,@

RW

1+d1

6M

OV

EA

RW

1,@

RW

1M

OVE

A RW

1,@

RW1+

d16

MO

VE

AR

W2,

@R

W1

MO

VEA

RW2

,@RW

1+d1

6M

OV

EA

RW

3,@

RW

1M

OVE

A RW

3,@

RW1+

d16

MO

VE

AR

W4,

@R

W1

MO

VEA

RW4

,@RW

1+d1

6M

OV

EA

RW

5,@

RW

1M

OV

EA

RW

5,@

RW

1+d1

6M

OV

EA

RW

6,@

RW

1M

OVE

A RW

6,@

RW1+

d16

MO

VE

AR

W7,

@R

W1

MO

VEA

RW7

,@RW

1+d1

6

+A

MO

VE

AR

W0,

@R

W2

MO

VEA

RW

0,@

RW

2+d1

6M

OV

EA

RW

1,@

RW

2M

OVE

A RW

1,@

RW2+

d16

MO

VE

AR

W2,

@R

W2

MO

VEA

RW2

,@RW

2+d1

6M

OV

EA

RW

3,@

RW

2M

OVE

A RW

3,@

RW2+

d16

MO

VE

AR

W4,

@R

W2

MO

VEA

RW4

,@RW

2+d1

6M

OV

EA

RW

5,@

RW

2M

OV

EA

RW

5,@

RW

2+d1

6M

OV

EA

RW

6,@

RW

2M

OVE

A RW

6,@

RW2+

d16

MO

VE

AR

W7,

@R

W2

MO

VEA

RW7

,@RW

2+d1

6

+B

MO

VE

AR

W0,

@R

W3

MO

VEA

RW

0,@

RW

3+d1

6M

OV

EA

RW

1,@

RW

3M

OVE

A RW

1,@

RW3+

d16

MO

VE

AR

W2,

@R

W3

MO

VEA

RW2

,@RW

3+d1

6M

OV

EA

RW

3,@

RW

3M

OVE

A RW

3,@

RW3+

d16

MO

VE

AR

W4,

@R

W3

MO

VEA

RW4

,@RW

3+d1

6M

OV

EA

RW

5,@

RW

3M

OV

EA

RW

5,@

RW

3+d1

6M

OV

EA

RW

6,@

RW

3M

OVE

A RW

6,@

RW3+

d16

MO

VE

AR

W7,

@R

W3

MO

VEA

RW7

,@RW

3+d1

6

+C

MO

VEA

RW0,

@R

W0+

MO

VEA

RW

0,@

RW

0+R

W7

MO

VEA

RW1,

@RW

0+M

OVE

A RW

1,@

RW0+

RW7

MO

VEA

RW2,

@RW

0+M

OVE

A RW

2,@

RW0+

RW7

MO

VEA

RW3,

@RW

0+M

OVE

A RW

3,@

RW0+

RW7

MO

VEA

RW4,

@RW

0+M

OVE

A RW

4,@

RW0+

RW7

MO

VEA

RW5,

@RW

0+M

OV

EA

RW

5,@

RW

0+R

W7

MO

VEA

RW6,

@RW

0+M

OVE

A RW

6,@

RW0+

RW7

MO

VEA

RW7,

@RW

0+M

OVE

A RW

7,@

RW0+

RW7

+D

MO

VEA

RW0,

@R

W1+

MO

VEA

RW

0,@

RW

1+R

W7

MO

VEA

RW1,

@RW

1+M

OVE

A RW

1,@

RW1+

RW7

MO

VEA

RW2,

@RW

1+M

OVE

A RW

2,@

RW1+

RW7

MO

VEA

RW3,

@RW

1+M

OVE

A RW

3,@

RW1+

RW7

MO

VEA

RW4,

@RW

1+M

OVE

A RW

4,@

RW1+

RW7

MO

VEA

RW5,

@RW

1+M

OV

EA

RW

5,@

RW

1+R

W7

MO

VEA

RW6,

@RW

1+M

OVE

A RW

6,@

RW1+

RW7

MO

VEA

RW7,

@RW

1+M

OVE

A RW

7,@

RW1+

RW7

+E

MO

VEA

RW0,

@R

W2+

MO

VEA

RW

0,@

PC+d

16M

OVE

ARW

1,@

RW2+

MO

VEA

RW1

,@PC

+d16

MO

VEA

RW2,

@RW

2+M

OVE

A RW

2,@

PC+d

16M

OVE

ARW

3,@

RW2+

MO

VEA

RW3

,@PC

+d16

MO

VEA

RW4,

@RW

2+M

OVE

A RW

4,@

PC+d

16M

OVE

ARW

5,@

RW2+

MO

VE

A R

W5

,@P

C+d

16M

OVE

ARW

6,@

RW2+

MO

VEA

RW6

,@PC

+d16

MO

VEA

RW7,

@RW

2+M

OVE

A RW

7,@

PC+d

16

+FM

OVE

ARW

0,@

RW

3+M

OV

EA

R

W0,

add

r16

MO

VEA

RW1,

@RW

3+M

OV

EA

R

W1,

add

r16

MO

VEA

RW2,

@RW

3+M

OV

EA

R

W2,

add

r16

MO

VEA

RW3,

@RW

3+M

OV

EA

R

W3,

add

r16

MO

VEA

RW4,

@RW

3+M

OV

EA

R

W4,

add

r16

MO

VEA

RW5,

@RW

3+M

OV

EA

R

W5,

add

r16

MO

VEA

RW6,

@RW

3+M

OV

EA

R

W6,

add

r16

MO

VEA

RW7@

RW3+

MO

VE

A

RW

7, a

ddr1

6

462


Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

V R0,

R0

MO

V

R0,

@R

W0+

d8M

OV R

1, R

0M

OV

R

1,@

RW

0+d8

MO

V R2,

R0

MO

V

R2,

@R

W0+

d8M

OV R

3, R

0M

OV

R

3,@

RW

0+d8

MO

V R4,

R0

MO

V

R4,

@R

W0+

d8M

OV R

5, R

0M

OV

R

5,@

RW

0+d8

MO

V R6,

R0

MO

V

R6,

@R

W0+

d8M

OV R

7, R

0M

OV

R

7,@

RW

0+d8

+1

MO

V R0,

R1

MO

V

R0,

@R

W1+

d8M

OV R

1, R

1M

OV

R

1,@

RW

1+d8

MO

V R2,

R1

MO

V

R2,

@R

W1+

d8M

OV R

3, R

1M

OV

R

3,@

RW

1+d8

MO

V R4,

R1

MO

V

R4,

@R

W1+

d8M

OV R

5, R

1M

OV

R

5,@

RW

1+d8

MO

V R6,

R1

MO

V

R6,

@R

W1+

d8M

OV R

7, R

1M

OV

R

7,@

RW

1+d8

+2

MO

V R0,

R2

MO

V

R0,

@R

W2+

d8M

OV R

1, R

2M

OV

R

1,@

RW

2+d8

MO

V R2,

R2

MO

V

R2,

@R

W2+

d8M

OV R

3, R

2M

OV

R

3,@

RW

2+d8

MO

V R4,

R2

MO

V

R4,

@R

W2+

d8M

OV R

5, R

2M

OV

R

5,@

RW

2+d8

MO

V R6,

R2

MO

V

R6,

@R

W2+

d8M

OV R

7, R

2M

OV

R

7,@

RW

2+d8

+3

MO

V R0,

R3

MO

V

R0,

@R

W3+

d8M

OV R

1, R

3M

OV

R

1,@

RW

3+d8

MO

V R2,

R3

MO

V

R2,

@R

W3+

d8M

OV R

3, R

3M

OV

R

3,@

RW

3+d8

MO

V R4,

R3

MO

V

R4,

@R

W3+

d8M

OV R

5, R

3M

OV

R

5,@

RW

3+d8

MO

V R6,

R3

MO

V

R6,

@R

W3+

d8M

OV R

7, R

3M

OV

R

7,@

RW

3+d8

+4

MO

V R0,

R4

MO

V

R0,

@R

W4+

d8M

OV R

1, R

4M

OV

R

1,@

RW

4+d8

MO

V R2,

R4

MO

V

R2,

@R

W4+

d8M

OV R

3, R

4M

OV

R

3,@

RW

4+d8

MO

V R4,

R4

MO

V

R4,

@R

W4+

d8M

OV R

5, R

4M

OV

R

5,@

RW

4+d8

MO

V R6,

R4

MO

V

R6,

@R

W4+

d8M

OV R

7, R

4M

OV

R

7,@

RW

4+d8

+5

MO

V R0,

R5

MO

V

R0,

@R

W5+

d8M

OV R

1, R

5M

OV

R

1,@

RW

5+d8

MO

V R2,

R5

MO

V

R2,

@R

W5+

d8M

OV R

3, R

5M

OV

R

3,@

RW

5+d8

MO

V R4,

R5

MO

V

R4,

@R

W5+

d8M

OV R

5, R

5M

OV

R

5,@

RW

5+d8

MO

V R6,

R5

MO

V

R6,

@R

W5+

d8M

OV R

7, R

5M

OV

R

7,@

RW

5+d8

+6

MO

V R0,

R6

MO

V

R0,

@R

W6+

d8M

OV R

1, R

6M

OV

R

1,@

RW

6+d8

MO

V R2,

R6

MO

V

R2,

@R

W6+

d8M

OV R

3, R

6M

OV

R

3,@

RW

6+d8

MO

V R4,

R6

MO

V

R4,

@R

W6+

d8M

OV R

5, R

6M

OV

R

5,@

RW

6+d8

MO

V R6,

R6

MO

V

R6,

@R

W6+

d8M

OV R

7, R

6M

OV

R

7,@

RW

6+d8

+7

MO

V R0,

R7

MO

V

R0,

@R

W7+

d8M

OV R

1, R

7M

OV

R

1,@

RW

7+d8

MO

V R2,

R7

MO

V

R2,

@R

W7+

d8M

OV R

3, R

7M

OV

R

3,@

RW

7+d8

MO

V R4,

R7

MO

V

R4,

@R

W7+

d8M

OV R

5, R

7M

OV

R

5,@

RW

7+d8

MO

V R6,

R7

MO

V

R6,

@R

W7+

d8M

OV R

7, R

7M

OV

R

7,@

RW

7+d8

+8

MO

VR

0,@

RW

0M

OV

R

0,@

RW

0+d1

6M

OV

R1,

@R

W0

MO

V

R1,

@R

W0+

d16

MO

VR

2,@

RW

0M

OV

R

2,@

RW

0+d1

6M

OV

R3,

@R

W0

MO

V

R3,

@R

W0+

d16

MO

VR

4,@

RW

0M

OV

R

4,@

RW

0+d1

6M

OV

R5,

@R

W0

MO

V

R5,

@R

W0+

d16

MO

VR

6,@

RW

0M

OV

R

6,@

RW

0+d1

6M

OV

R7,

@R

W0

MO

V

R7,

@R

W0+

d16

+9

MO

VR

0,@

RW

1M

OV

R

0,@

RW

1+d1

6M

OV

R1,

@R

W1

MO

V

R1,

@R

W1+

d16

MO

VR

2,@

RW

1M

OV

R

2,@

RW

1+d1

6M

OV

R3,

@R

W1

MO

V

R3,

@R

W1+

d16

MO

VR

4,@

RW

1M

OV

R

4,@

RW

1+d1

6M

OV

R5,

@R

W1

MO

V

R5,

@R

W1+

d16

MO

VR

6,@

RW

1M

OV

R

6,@

RW

1+d1

6M

OV

R7,

@R

W1

MO

V

R7,

@R

W1+

d16

+AM

OV

R0,

@R

W2

MO

V

R0,

@R

W2+

d16

MO

VR

1,@

RW

2M

OV

R

1,@

RW

2+d1

6M

OV

R2,

@R

W2

MO

V

R2,

@R

W2+

d16

MO

VR

3,@

RW

2M

OV

R

3,@

RW

2+d1

6M

OV

R4,

@R

W2

MO

V

R4,

@R

W2+

d16

MO

VR

5,@

RW

2M

OV

R

5,@

RW

2+d1

6M

OV

R6,

@R

W2

MO

V

R6,

@R

W2+

d16

MO

VR

7,@

RW

2M

OV

R

7,@

RW

2+d1

6

+BM

OV

R0,

@R

W3

MO

V

R0,

@R

W3+

d16

MO

VR

1,@

RW

3M

OV

R

1,@

RW

3+d1

6M

OV

R2,

@R

W3

MO

V

R2,

@R

W3+

d16

MO

VR

3,@

RW

3M

OV

R

3,@

RW

3+d1

6M

OV

R4,

@R

W3

MO

V

R4,

@R

W3+

d16

MO

VR

5,@

RW

3M

OV

R

5,@

RW

3+d1

6M

OV

R6,

@R

W3

MO

V

R6,

@R

W3+

d16

MO

VR

7,@

RW

3M

OV

R

7,@

RW

3+d1

6

+C

MO

V

R0,

@R

W0+

MO

V R

0,@

RW0+

RW

7M

OV

R

1,@

RW

0+M

OV

R1,

@RW

0+R

W7

MO

V

R2,

@R

W0+

MO

V R

2,@

RW

0+RW

7M

OV

R

3,@

RW

0+M

OV

R3,

@R

W0+

RW7

MO

V

R4,

@R

W0+

MO

V R

4,@

RW

0+RW

7M

OV

R

5,@

RW

0+M

OV

R5,

@RW

0+R

W7

MO

V

R6,

@R

W0+

MO

V R

6,@

RW0+

RW

7M

OV

R

7,@

RW

0+M

OV

R7,

@RW

0+R

W7

+D

MO

V

R0,

@R

W1+

MO

V R

0,@

RW1+

RW

7M

OV

R

1,@

RW

1+M

OV

R1,

@RW

1+R

W7

MO

V

R2,

@R

W1+

MO

V R

2,@

RW

1+RW

7M

OV

R

3,@

RW

1+M

OV

R3,

@R

W1+

RW7

MO

V

R4,

@R

W1+

MO

V R

4,@

RW

1+RW

7M

OV

R

5,@

RW

1+M

OV

R5,

@RW

1+R

W7

MO

V

R6,

@R

W1+

MO

V R

6,@

RW1+

RW

7M

OV

R

7,@

RW

1+M

OV

R7,

@RW

1+R

W7

+EM

OV

R

0,@

RW

2+M

OV

R

0,@

PC

+d1

6M

OV

R

1,@

RW

2+M

OV

R

1,@

PC

+d1

6M

OV

R

2,@

RW

2+M

OV

R

2,@

PC

+d1

6M

OV

R

3,@

RW

2+M

OV

R

3,@

PC

+d1

6M

OV

R

4,@

RW

2+M

OV

R

4,@

PC

+d1

6M

OV

R

5,@

RW

2+M

OV

R

5,@

PC

+d1

6M

OV

R

6,@

RW

2+M

OV

R

6,@

PC

+d1

6M

OV

R

7,@

RW

2+M

OV

R

7,@

PC

+d1

6

+F

MO

V

R0,

@R

W3+

MO

V

R0,

addr

16M

OV

R

1,@

RW

3+M

OV

R

1,ad

dr16

MO

V

R2,

@R

W3+

MO

V

R2,

addr

16M

OV

R

3,@

RW

3+M

OV

R

3,ad

dr16

MO

V

R4,

@R

W3+

MO

V

R4,

addr

16M

OV

R

5,@

RW

3+M

OV

R

5,ad

dr16

MO

V

R6,

@R

W3+

MO

V

R6,

addr

16M

OV

R

7,@

RW

3+M

OV

R

7,ad

dr16

463


Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

VW

RW

0, R

W0

MO

VW

@R

W0+

d8M

OV

WR

W1,

RW

0M

OV

W R

W1,

@R

W0+

d8M

OV

WR

W2,

RW

0M

OV

W R

W2,

@R

W0+

d8M

OV

WR

W3,

RW

0M

OV

W R

W3,

@R

W0+

d8M

OV

WR

W4,

RW

0M

OV

W R

W4,

@R

W0+

d8M

OV

WR

W5,

RW

0M

OV

W R

W5,

@R

W0+

d8M

OV

WR

W6,

RW

0M

OV

W R

W6,

@R

W0+

d8M

OV

WR

W7,

RW

0M

OV

W R

W7,

@R

W0+

d8

+1

MO

VW

RW

0, R

W1

MO

VW

@R

W1+

d8M

OV

WR

W1,

RW

1M

OV

W R

W1,

@R

W1+

d8M

OV

WR

W2,

RW

1M

OV

W R

W2,

@R

W1+

d8M

OV

WR

W3,

RW

1M

OV

W R

W3,

@R

W1+

d8M

OV

WR

W4,

RW

1M

OV

W R

W4,

@R

W1+

d8M

OV

WR

W5,

RW

1M

OV

W R

W5,

@R

W1+

d8M

OV

WR

W6,

RW

1M

OV

W R

W6,

@R

W1+

d8M

OV

WR

W7,

RW

1M

OV

W R

W7,

@R

W1+

d8

+2

MO

VW

RW

0, R

W2

MO

VW

@R

W2+

d8M

OV

WR

W1,

RW

2M

OV

W R

W1,

@R

W2+

d8M

OV

WR

W2,

RW

2M

OV

W R

W2,

@R

W2+

d8M

OV

WR

W3,

RW

2M

OV

W R

W3,

@R

W2+

d8M

OV

WR

W4,

RW

2M

OV

W R

W4,

@R

W2+

d8M

OV

WR

W5,

RW

2M

OV

W R

W5,

@R

W2+

d8M

OV

WR

W6,

RW

2M

OV

W R

W6,

@R

W2+

d8M

OV

WR

W7,

RW

2M

OV

W R

W7,

@R

W2+

d8

+3

MO

VW

RW

0, R

W3

MO

VW

@R

W3+

d8M

OV

WR

W1,

RW

3M

OV

W R

W1,

@R

W3+

d8M

OV

WR

W2,

RW

3M

OV

W R

W2,

@R

W3+

d8M

OV

WR

W3,

RW

3M

OV

W R

W3,

@R

W3+

d8M

OV

WR

W4,

RW

3M

OV

W R

W4,

@R

W3+

d8M

OV

WR

W5,

RW

3M

OV

W R

W5,

@R

W3+

d8M

OV

WR

W6,

RW

3M

OV

W R

W6,

@R

W3+

d8M

OV

WR

W7,

RW

3M

OV

W R

W7,

@R

W3+

d8

+4

MO

VW

RW

0, R

W4

MO

VW

@R

W4+

d8M

OV

WR

W1,

RW

4M

OV

W R

W1,

@R

W4+

d8M

OV

WR

W2,

RW

4M

OV

W R

W2,

@R

W4+

d8M

OV

WR

W3,

RW

4M

OV

W R

W3,

@R

W4+

d8M

OV

WR

W4,

RW

4M

OV

W R

W4,

@R

W4+

d8M

OV

WR

W5,

RW

4M

OV

W R

W5,

@R

W4+

d8M

OV

WR

W6,

RW

4M

OV

W R

W6,

@R

W4+

d8M

OV

WR

W7,

RW

4M

OV

W R

W7,

@R

W4+

d8

+5

MO

VW

RW

0, R

W5

MO

VW

@R

W5+

d8M

OV

WR

W1,

RW

5M

OV

W R

W1,

@R

W5+

d8M

OV

WR

W2,

RW

5M

OV

W R

W2,

@R

W5+

d8M

OV

WR

W3,

RW

5M

OV

W R

W3,

@R

W5+

d8M

OV

WR

W4,

RW

5M

OV

W R

W4,

@R

W5+

d8M

OV

WR

W5,

RW

5M

OV

W R

W5,

@R

W5+

d8M

OV

WR

W6,

RW

5M

OV

W R

W6,

@R

W5+

d8M

OV

WR

W7,

RW

5M

OV

W R

W7,

@R

W5+

d8

+6

MO

VW

RW

0, R

W6

MO

VW

@R

W6+

d8M

OV

WR

W1,

RW

6M

OV

W R

W1,

@R

W6+

d8M

OV

WR

W2,

RW

6M

OV

W R

W2,

@R

W6+

d8M

OV

WR

W3,

RW

6M

OV

W R

W3,

@R

W6+

d8M

OV

WR

W4,

RW

6M

OV

W R

W4,

@R

W6+

d8M

OV

WR

W5,

RW

6M

OV

W R

W5,

@R

W6+

d8M

OV

WR

W6,

RW

6M

OV

W R

W6,

@R

W6+

d8M

OV

WR

W7,

RW

6M

OV

W R

W7,

@R

W6+

d8

+7

MO

VW

RW

0, R

W7

MO

VW

@R

W7+

d8M

OV

WR

W1,

RW

7M

OV

W R

W1,

@R

W7+

d8M

OV

WR

W2,

RW

7M

OV

W R

W2,

@R

W7+

d8M

OV

WR

W3,

RW

7M

OV

W R

W3,

@R

W7+

d8M

OV

WR

W4,

RW

7M

OV

W R

W4,

@R

W7+

d8M

OV

WR

W5,

RW

7M

OV

W R

W5,

@R

W7+

d8M

OV

WR

W6,

RW

7M

OV

W R

W6,

@R

W7+

d8M

OV

WR

W7,

RW

7M

OV

W R

W7,

@R

W7+

d8

+8

MO

VW

RW

0,@

RW

0M

OV

W@

RW

0+d1

6M

OV

WR

W1,

@R

W0

MO

VW

RW

1,@

RW

0+d1

6M

OV

WR

W2,

@R

W0

MO

VW

RW

2,@

RW

0+d1

6M

OV

WR

W3,

@R

W0

MO

VW

RW

3,@

RW

0+d1

6M

OV

WR

W4,

@R

W0

MO

VW

RW

4,@

RW

0+d1

6M

OV

WR

W5,

@R

W0

MO

VW

RW

5,@

RW

0+d1

6M

OV

WR

W6,

@R

W0

MO

VW

RW

6,@

RW

0+d1

6M

OV

WR

W7,

@R

W0

MO

VW

RW

7,@

RW

0+d1

6

+9

MO

VW

RW

0,@

RW

1M

OV

W@

RW

1+d1

6M

OV

WR

W1,

@R

W1

MO

VW

RW

1,@

RW

1+d1

6M

OV

WR

W2,

@R

W1

MO

VW

RW

2,@

RW

1+d1

6M

OV

WR

W3,

@R

W1

MO

VW

RW

3,@

RW

1+d1

6M

OV

WR

W4,

@R

W1

MO

VW

RW

4,@

RW

1+d1

6M

OV

WR

W5,

@R

W1

MO

VW

RW

5,@

RW

1+d1

6M

OV

WR

W6,

@R

W1

MO

VW

RW

6,@

RW

1+d1

6M

OV

WR

W7,

@R

W1

MO

VW

RW

7,@

RW

1+d1

6

+A

MO

VW

RW

0,@

RW

2M

OV

W@

RW

2+d1

6M

OV

WR

W1,

@R

W2

MO

VW

RW

1,@

RW

2+d1

6M

OV

WR

W2,

@R

W2

MO

VW

RW

2,@

RW

2+d1

6M

OV

WR

W3,

@R

W2

MO

VW

RW

3,@

RW

2+d1

6M

OV

WR

W4,

@R

W2

MO

VW

RW

4,@

RW

2+d1

6M

OV

WR

W5,

@R

W2

MO

VW

RW

5,@

RW

2+d1

6M

OV

WR

W6,

@R

W2

MO

VW

RW

6,@

RW

2+d1

6M

OV

WR

W7,

@R

W2

MO

VW

RW

7,@

RW

2+d1

6

+B

MO

VW

RW

0,@

RW

3M

OV

W@

RW

3+d1

6M

OV

WR

W1,

@R

W3

MO

VW

RW

1,@

RW

3+d1

6M

OV

WR

W2,

@R

W3

MO

VW

RW

2,@

RW

3+d1

6M

OV

WR

W3,

@R

W3

MO

VW

RW

3,@

RW

3+d1

6M

OV

WR

W4,

@R

W3

MO

VW

RW

4,@

RW

3+d1

6M

OV

WR

W5,

@R

W3

MO

VW

RW

5,@

RW

3+d1

6M

OV

WR

W6,

@R

W3

MO

VW

RW

6,@

RW

3+d1

6M

OV

WR

W7,

@R

W3

MO

VW

RW

7,@

RW

3+d1

6

+C

MO

VW

RW

0,@

RW

0+M

OV

W@

RW

0+R

W7

MO

VW

RW

1,@

RW

0+M

OV

W R

W1,

@R

W0+

RW

7M

OV

WR

W2,

@R

W0+

MO

VW

RW

2,@

RW

0+R

W7

MO

VW

RW

3,@

RW

0+M

OV

W R

W3,

@R

W0+

RW

7M

OV

WR

W4,

@R

W0+

MO

VW

RW

4,@

RW

0+R

W7

MO

VW

RW

5,@

RW

0+M

OV

W R

W5,

@R

W0+

RW

7M

OV

WR

W6,

@R

W0+

MO

VW

RW

6,@

RW

0+R

W7

MO

VW

RW

7,@

RW

0+M

OV

W R

W7,

@R

W0+

RW

7

+D

MO

VWR

W0,

@R

W1+

MO

VW

@R

W1+

RW

7M

OVW

RW1,

@RW

1+M

OV

W R

W1,

@R

W1+

RW

7M

OVW

RW2,

@R

W1+

MO

VW

RW

2,@

RW

1+R

W7

MO

VWR

W3,

@R

W1+

MO

VW

RW

3,@

RW

1+R

W7

MO

VWRW

4, @

RW

1+M

OV

W R

W4,

@R

W1+

RW

7M

OVW

RW5,

@R

W1+

MO

VW

@R

W1+

RW

7M

OVW

RW

6, @

RW

1+M

OV

W R

W6,

@R

W1+

RW

7M

OVW

RW7,

@R

W1+

MO

VW

RW

7,@

RW

1+R

W7

+E

MO

VWRW

0, @

RW

2+M

OV

W@

PC

+d1

6M

OVW

RW1,

@R

W2+

MO

VW

RW

1,@

PC

+d16

MO

VWR

W2,

@R

W2+

MO

VW

RW

2,@

PC

+d16

MO

VWRW

3, @

RW2+

MO

VW

RW

3,@

PC

+d16

MO

VWRW

4, @

RW

2+M

OV

W R

W4,

@P

C+d

16M

OVW

RW

5, @

RW

2+M

OV

W@

PC

+d1

6M

OVW

RW6,

@R

W2+

MO

VW

RW

6,@

PC

+d16

MO

VWR

W7,

@R

W2+

MO

VW

RW

7,@

PC

+d16

+F

MO

VWRW

0, @

RW

3+M

OV

WR

W0,

add

r16

MO

VWRW

1, @

RW

3+M

OV

WR

W1,

add

r16

MO

VWR

W2,

@R

W3+

MO

VW

RW

2, a

ddr1

6M

OVW

RW3,

@RW

3+M

OV

WR

W3,

add

r16

MO

VWRW

4, @

RW

3+M

OV

WR

W4,

add

r16

MO

VWR

W5,

@R

W3+

MO

VW

RW

5, a

ddr1

6M

OVW

RW6,

@R

W3+

MO

VW

RW

6, a

ddr1

6M

OVW

RW

7, @

RW

3+M

OV

WR

W7,

add

r16

464


Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

V R0,

R0

MO

V@

RW

0+d8

, R0

MO

V R0,

R1

MO

V@

RW

0+d8

, R1

MO

V R0,

R2

MO

V@

RW

0+d8

, R2

MO

V R0,

R3

MO

V@

RW

0+d8

, R3

MO

V R0,

R4

MO

V@

RW

0+d8

, R4

MO

V R0,

R5

MO

V@

RW

0+d8

, R5

MO

V R0,

R6

MO

V@

RW

0+d8

, R6

MO

V R0,

R7

MO

V@

RW

0+d8

, R7

+1

MO

V R1,

R0

MO

V@

RW

1+d8

, R0

MO

V R1,

R1

MO

V@

RW

1+d8

, R1

MO

V R1,

R2

MO

V@

RW

1+d8

, R2

MO

V R1,

R3

MO

V@

RW

1+d8

, R3

MO

V R1,

R4

MO

V@

RW

1+d8

, R4

MO

V R1,

R5

MO

V@

RW

1+d8

, R5

MO

V R1,

R6

MO

V@

RW

1+d8

, R6

MO

V R1,

R7

MO

V@

RW

1+d8

, R7

+2

MO

V R2,

R0

MO

V@

RW

2+d8

, R0

MO

V R2,

R1

MO

V@

RW

2+d8

, R1

MO

V R2,

R2

MO

V@

RW

2+d8

, R2

MO

V R2,

R3

MO

V@

RW

2+d8

, R3

MO

V R2,

R4

MO

V@

RW

2+d8

, R4

MO

V R2,

R5

MO

V@

RW

2+d8

, R5

MO

V R2,

R6

MO

V@

RW

2+d8

, R6

MO

V R2,

R7

MO

V@

RW

2+d8

, R7

+3

MO

V R3,

R0

MO

V@

RW

3+d8

, R0

MO

V R3,

R1

MO

V@

RW

3+d8

, R1

MO

V R3,

R2

MO

V@

RW

3+d8

, R2

MO

V R3,

R3

MO

V@

RW

3+d8

, R3

MO

V R3,

R4

MO

V@

RW

3+d8

, R4

MO

V R3,

R5

MO

V@

RW

3+d8

, R5

MO

V R3,

R6

MO

V@

RW

3+d8

, R6

MO

V R3,

R7

MO

V@

RW

3+d8

, R7

+4

MO

V R4,

R0

MO

V@

RW

4+d8

, R0

MO

V R4,

R1

MO

V@

RW

4+d8

, R1

MO

V R4,

R2

MO

V@

RW

4+d8

, R2

MO

V R4,

R3

MO

V@

RW

4+d8

, R3

MO

V R4,

R4

MO

V@

RW

4+d8

, R4

MO

V R4,

R5

MO

V@

RW

4+d8

, R5

MO

V R4,

R6

MO

V@

RW

4+d8

, R6

MO

V R4,

R7

MO

V@

RW

4+d8

, R7

+5

MO

V R5,

R0

MO

V@

RW

5+d8

, R0

MO

V R5,

R1

MO

V@

RW

5+d8

, R1

MO

V R5,

R2

MO

V@

RW

5+d8

, R2

MO

V R5,

R3

MO

V@

RW

5+d8

, R3

MO

V R5,

R4

MO

V@

RW

5+d8

, R4

MO

V R5,

R5

MO

V@

RW

5+d8

, R5

MO

V R5,

R6

MO

V@

RW

5+d8

, R6

MO

V R5,

R7

MO

V@

RW

5+d8

, R7

+6

MO

V R6,

R0

MO

V@

RW

6+d8

, R0

MO

V R6,

R1

MO

V@

RW

6+d8

, R1

MO

V R6,

R2

MO

V@

RW

6+d8

, R2

MO

V R6,

R3

MO

V@

RW

6+d8

, R3

MO

V R6,

R4

MO

V@

RW

6+d8

, R4

MO

V R6,

R5

MO

V@

RW

6+d8

, R5

MO

V R6,

R6

MO

V@

RW

6+d8

, R6

MO

V R6,

R7

MO

V@

RW

6+d8

, R7

+7

MO

V R7,

R0

MO

V@

RW

7+d8

, R0

MO

V R7,

R1

MO

V@

RW

7+d8

, R1

MO

V R7,

R2

MO

V@

RW

7+d8

, R2

MO

V R7,

R3

MO

V@

RW

7+d8

, R3

MO

V R7,

R4

MO

V@

RW

7+d8

, R4

MO

V R7,

R5

MO

V@

RW

7+d8

, R5

MO

V R7,

R6

MO

V@

RW

7+d8

, R6

MO

V R7,

R7

MO

V@

RW

7+d8

, R7

+8

MO

V@

RW

0, R

0M

OV

@R

W0+

d16,

R0

MO

V@

RW

0, R

1M

OV

@RW

0+d1

6, R

1M

OV

@R

W0,

R2

MO

V@

RW

0+d1

6, R

2M

OV

@R

W0,

R3

MO

V@

RW

0+d1

6, R

3M

OV

@R

W0,

R4

MO

V@

RW

0+d1

6, R

4M

OV

@R

W0,

R5

MO

V@

RW0+

d16,

R5

MO

V@

RW

0, R

6M

OV

@R

W0+

d16,

R

6

MO

V@

RW

0, R

7M

OV

@RW

0+d1

6, R

7

+9

MO

V@

RW

1, R

0M

OV

@R

W1+

d16,

R0

MO

V@

RW

1, R

1M

OV

@RW

1+d1

6, R

1M

OV

@R

W1,

R2

MO

V@

RW

1+d1

6, R

2M

OV

@R

W1,

R3

MO

V@

RW

1+d1

6, R

3M

OV

@R

W1,

R4

MO

V@

RW

1+d1

6, R

4M

OV

@R

W1,

R5

MO

V@

RW1+

d16,

R5

MO

V@

RW

1, R

6M

OV

@R

W1+

d16,

R6

MO

V@

RW

1, R

7M

OV

@RW

1+d1

6, R

7

+A

MO

V@

RW

2, R

0M

OV

@R

W2+

d16,

R0

MO

V@

RW

2, R

1M

OV

@RW

2+d1

6, R

1M

OV

@R

W2,

R2

MO

V@

RW

2+d1

6, R

2M

OV

@R

W2,

R3

MO

V@

RW

2+d1

6, R

3M

OV

@R

W2,

R4

MO

V@

RW

2+d1

6, R

4M

OV

@R

W2,

R5

MO

V@

RW2+

d16,

R5

MO

V@

RW

2, R

6M

OV

@R

W2+

d16,

R6

MO

V@

RW

2, R

7M

OV

@RW

2+d1

6, R

7

+B

MO

V@

RW

3, R

0M

OV

@R

W3+

d16,

R0

MO

V@

RW

3, R

1M

OV

@RW

3+d1

6, R

1M

OV

@R

W3,

R2

MO

V@

RW

3+d1

6, R

2M

OV

@R

W3,

R3

MO

V@

RW

3+d1

6, R

3M

OV

@R

W3,

R4

MO

V@

RW

3+d1

6, R

4M

OV

@R

W3,

R5

MO

V@

RW3+

d16,

R5

MO

V@

RW

3, R

6M

OV

@R

W3+

d16,

R6

MO

V@

RW

3, R

7M

OV

@RW

3+d1

6, R

7

+C

MO

V@

RW

0+, R

0M

OV

@R

W0+

RW

7, R

0M

OV

@R

W0+

, R1

MO

V@

RW0+

RW7,

R1

MO

V@

RW

0+, R

2M

OV

@R

W0+

RW

7, R

2M

OV

@R

W0+

, R3

MO

V@

RW

0+R

W7,

R3

MO

V@

RW

0+, R

4M

OV

@R

W0+

RW

7, R

4M

OV

@R

W0+

, R5

MO

V@

RW

0+R

W7,

R5

MO

V@

RW

0+, R

6M

OV

@R

W0+

RW

7, R

6M

OV

@R

W0+

, R7

MO

V@

RW

0+R

W7,

R7

+D

MO

V@

RW

1+, R

0M

OV

@R

W1+

RW

7, R

0M

OV

@R

W1+

, R1

MO

V@

RW1+

RW7,

R1

MO

V@

RW

1+, R

2M

OV

@R

W1+

RW

7, R

2M

OV

@R

W1+

, R3

MO

V@

RW

1+R

W7,

R3

MO

V@

RW

1+, R

4M

OV

@R

W1+

RW

7, R

4M

OV

@R

W1+

, R5

MO

V@

RW

1+R

W7,

R5

MO

V@

RW

1+, R

6M

OV

@R

W1+

RW

7, R

6M

OV

@R

W1+

, R7

MO

V@

RW

1+R

W7,

R7

+E

MO

V@

RW

2+, R

0M

OV

@P

C+d

16, R

0M

OV

@R

W2+

, R1

MO

V@

PC

+d16

, R1

MO

V@

RW

2+, R

2M

OV

@P

C+d

16, R

2M

OV

@R

W2+

, R3

MO

V@

PC

+d16

, R3

MO

V@

RW

2+, R

4M

OV

@P

C+d

16, R

4M

OV

@R

W2+

, R5

MO

V@

PC

+d16

, R5

MO

V@

RW

2+, R

6M

OV

@P

C+d

16, R

6M

OV

@R

W2+

, R7

MO

V@

PC

+d16

, R7

+F

MO

V@

RW

3+, R

0M

OV

addr

16, R

0M

OV

@R

W3+

, R1

MO

Vad

dr16

, R1

MO

V@

RW

3+, R

2M

OV

addr

16, R

2M

OV

@R

W3+

, R3

MO

Vad

dr16

, R3

MO

V@

RW

3+, R

4M

OV

addr

16, R

4M

OV

@R

W3+

, R5

MO

Vad

dr16

, R5

MO

V@

RW

3+, R

6M

OV

addr

16, R

6M

OV

@R

W3+

, R7

MO

Vad

dr16

, R7

465


Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

VW

RW

0, R

W0

MO

VW@

RW

0+d8

, RW

0M

OV

WR

W0,

RW

1M

OVW

@R

W0+

d8, R

W1

MO

VW

RW

0, R

W2

MO

VW@

RW0+

d8, R

W2

MO

VW

RW

0, R

W3

MO

VW@

RW0+

d8, R

W3

MO

VW

RW

0, R

W4

MO

VW@

RW0+

d8, R

W4

MO

VW

RW

0, R

W5

MO

VW@

RW0+

d8, R

W5

MO

VW

RW

0, R

W6

MO

VW@

RW

0+d8

, RW

6M

OV

WR

W0,

RW

7M

OVW

@R

W0+

d8, R

W7

+1

MO

VW

RW

1, R

W0

MO

VW@

RW

1+d8

, RW

0M

OV

WR

W1,

RW

1M

OVW

@R

W1+

d8, R

W1

MO

VW

RW

1, R

W2

MO

VW@

RW1+

d8, R

W2

MO

VW

RW

1, R

W3

MO

VW@

RW1+

d8, R

W3

MO

VW

RW

1, R

W4

MO

VW@

RW1+

d8, R

W4

MO

VW

RW

1, R

W5

MO

VW@

RW1+

d8, R

W5

MO

VW

RW

1, R

W6

MO

VW@

RW

1+d8

, RW

6M

OV

WR

W1,

RW

7M

OVW

@R

W1+

d8, R

W7

+2

MO

VW

RW

2, R

W0

MO

VW@

RW

2+d8

, RW

0M

OV

WR

W2,

RW

1M

OVW

@R

W2+

d8, R

W1

MO

VW

RW

2, R

W2

MO

VW@

RW2+

d8, R

W2

MO

VW

RW

2, R

W3

MO

VW@

RW2+

d8, R

W3

MO

VW

RW

2, R

W4

MO

VW@

RW2+

d8, R

W4

MO

VW

RW

2, R

W5

MO

VW@

RW2+

d8, R

W5

MO

VW

RW

2, R

W6

MO

VW@

RW

2+d8

, RW

6M

OV

WR

W2,

RW

7M

OVW

@R

W2+

d8, R

W7

+3

MO

VW

RW

3, R

W0

MO

VW@

RW

3+d8

, RW

0M

OV

WR

W3,

RW

1M

OVW

@R

W3+

d8, R

W1

MO

VW

RW

3, R

W2

MO

VW@

RW3+

d8, R

W2

MO

VW

RW

3, R

W3

MO

VW@

RW3+

d8, R

W3

MO

VW

RW

3, R

W4

MO

VW@

RW3+

d8, R

W4

MO

VW

RW

3, R

W5

MO

VW@

RW3+

d8, R

W5

MO

VW

RW

3, R

W6

MO

VW@

RW

3+d8

, RW

6M

OV

WR

W3,

RW

7M

OVW

@R

W3+

d8, R

W7

+4

MO

VW

RW

4, R

W0

MO

VW@

RW

4+d8

, RW

0M

OV

WR

W4,

RW

1M

OVW

@R

W4+

d8, R

W1

MO

VW

RW

4, R

W2

MO

VW@

RW4+

d8, R

W2

MO

VW

RW

4, R

W3

MO

VW@

RW4+

d8, R

W3

MO

VW

RW

4, R

W4

MO

VW@

RW4+

d8, R

W4

MO

VW

RW

4, R

W5

MO

VW@

RW4+

d8, R

W5

MO

VW

RW

4, R

W6

MO

VW@

RW

4+d8

, RW

6M

OV

WR

W4,

RW

7M

OVW

@R

W4+

d8, R

W7

+5

MO

VW

RW

5, R

W0

MO

VW@

RW

5+d8

, RW

0M

OV

WR

W5,

RW

1M

OVW

@R

W5+

d8, R

W1

MO

VW

RW

5, R

W2

MO

VW@

RW5+

d8, R

W2

MO

VW

RW

5, R

W3

MO

VW@

RW5+

d8, R

W3

MO

VW

RW

5, R

W4

MO

VW@

RW5+

d8, R

W4

MO

VW

RW

5, R

W5

MO

VW@

RW5+

d8, R

W5

MO

VW

RW

5, R

W6

MO

VW@

RW

5+d8

, RW

6M

OV

WR

W5,

RW

7M

OVW

@R

W5+

d8, R

W7

+6

MO

VW

RW

6, R

W0

MO

VW@

RW

6+d8

, RW

0M

OV

WR

W6,

RW

1M

OVW

@R

W6+

d8, R

W1

MO

VW

RW

6, R

W2

MO

VW@

RW6+

d8, R

W2

MO

VW

RW

6, R

W3

MO

VW@

RW6+

d8, R

W3

MO

VW

RW

6, R

W4

MO

VW@

RW6+

d8, R

W4

MO

VW

RW

6, R

W5

MO

VW@

RW6+

d8, R

W5

MO

VW

RW

6, R

W6

MO

VW@

RW

6+d8

, RW

6M

OV

WR

W6,

RW

7M

OVW

@R

W6+

d8, R

W7

+7

MO

VW

RW

7, R

W0

MO

VW@

RW

7+d8

, RW

0M

OV

WR

W7,

RW

1M

OVW

@R

W7+

d8, R

W1

MO

VW

RW

7, R

W2

MO

VW@

RW7+

d8, R

W2

MO

VW

RW

7, R

W3

MO

VW@

RW7+

d8, R

W3

MO

VW

RW

7, R

W4

MO

VW@

RW7+

d8, R

W4

MO

VW

RW

7, R

W5

MO

VW@

RW7+

d8, R

W5

MO

VW

RW

7, R

W6

MO

VW@

RW

7+d8

, RW

6M

OV

WR

W7,

RW

7M

OVW

@R

W7+

d8, R

W7

+8

MO

VW

@R

W0,

RW

0M

OV

W@

RW

0+d

16, R

W0

MO

VW

@R

W0,

RW

1M

OV

W@

RW

0+d

16, R

W1

MO

VW

@R

W0,

RW

2M

OV

W@

RW

0+d

16, R

W2

MO

VW

@R

W0,

RW

3M

OV

W@

RW

0+d

16, R

W3

MO

VW

@R

W0,

RW

4M

OV

W@

RW

0+d

16, R

W4

MO

VW

@R

W0,

RW

5M

OV

W@

RW

0+d

16, R

W5

MO

VW

@R

W0,

RW

6M

OV

W@

RW

0+d

16, R

W6

MO

VW

@R

W0,

RW

7M

OV

W@

RW

0+d

16, R

W7

+9

MO

VW

@R

W1,

RW

0M

OV

W@

RW

1+d

16, R

W0

MO

VW

@R

W1,

RW

1M

OV

W@

RW

1+d

16, R

W1

MO

VW

@R

W1,

RW

2M

OV

W@

RW

1+d

16, R

W2

MO

VW

@R

W1,

RW

3M

OV

W@

RW

1+d

16, R

W3

MO

VW

@R

W1,

RW

4M

OV

W@

RW

1+d

16, R

W4

MO

VW

@R

W1,

RW

5M

OV

W@

RW

1+d

16, R

W5

MO

VW

@R

W1,

RW

6M

OV

W@

RW

1+d

16, R

W6

MO

VW

@R

W1,

RW

7M

OV

W@

RW

1+d

16, R

W7

+A

MO

VW

@R

W2,

RW

0M

OV

W@

RW

2+d

16, R

W0

MO

VW

@R

W2,

RW

1M

OV

W@

RW

2+d

16, R

W1

MO

VW

@R

W2,

RW

2M

OV

W@

RW

2+d

16, R

W2

MO

VW

@R

W2,

RW

3M

OV

W@

RW

2+d

16, R

W3

MO

VW

@R

W2,

RW

4M

OV

W@

RW

2+d

16, R

W4

MO

VW

@R

W2,

RW

5M

OV

W@

RW

2+d

16, R

W5

MO

VW

@R

W2,

RW

6M

OV

W@

RW

2+d

16, R

W6

MO

VW

@R

W2,

RW

7M

OV

W@

RW

2+d

16, R

W7

+B

MO

VW

@R

W3,

RW

0M

OV

W@

RW

3+d

16, R

W0

MO

VW

@R

W3,

RW

1M

OV

W@

RW

3+d

16, R

W1

MO

VW

@R

W3,

RW

2M

OV

W@

RW

3+d

16, R

W2

MO

VW

@R

W3,

RW

3M

OV

W@

RW

3+d

16, R

W3

MO

VW

@R

W3,

RW

4M

OV

W@

RW

3+d

16, R

W4

MO

VW

@R

W3,

RW

5M

OV

W@

RW

3+d

16, R

W5

MO

VW

@R

W3,

RW

6M

OV

W@

RW

3+d

16, R

W6

MO

VW

@R

W3,

RW

7M

OV

W@

RW

3+d

16, R

W7

+C

MO

VW@

RW

0+,R

W0

MO

VW

@R

W0

+RW

7,R

W0

MO

VW@

RW0+

, RW

1M

OV

W@

RW

0+R

W7,

RW

1M

OVW

@RW

0+,R

W2

MO

VW

@R

W0

+RW

7,R

W2

MO

VW@

RW

0+,R

W3

MO

VW

@R

W0

+RW

7,R

W3

MO

VW@

RW

0+,R

W4

MO

VW

@R

W0

+RW

7,R

W4

MO

VW@

RW

0+,R

W5

MO

VW

@R

W0

+RW

7,R

W5

MO

VW@

RW

0+,R

W6

MO

VW

@R

W0

+RW

7,R

W6

MO

VW@

RW

0+,R

W7

MO

VW

@R

W0

+RW

7,R

W7

+D

MO

VW@

RW

1+,R

W0

MO

VW

@R

W1

+RW

7,R

W0

MO

VW

@R

W1+

,RW

1M

OV

W@

RW

1+R

W7,

RW

1M

OVW

@RW

1+,R

W2

MO

VW

@R

W1

+RW

7,R

W2

MO

VW@

RW

1+,R

W3

MO

VW

@R

W1

-+R

W7,

RW

3M

OVW

@R

W1+

,RW

4M

OV

W@

RW

1+R

W7,

RW

4M

OVW

@R

W1+

,RW

5M

OV

W@

RW

1+R

W7,

RW

5M

OVW

@R

W1+

,RW

6M

OV

W@

RW

1+R

W7,

RW

6M

OVW

@R

W1+

,RW

7M

OV

W@

RW

1+R

W7,

RW

7

+E

MO

VW@

RW

2+,R

W0

MO

VW

@P

C+

d16,

RW

0M

OV

W@

RW

2+,R

W1

MO

VW

@P

C+

d16,

RW

1M

OVW

@RW

2+,R

W2

MO

VW

@P

C+

d16,

RW

2M

OVW

@R

W2+

,RW

3M

OV

W@

PC

+d1

6, R

W3

MO

VW@

RW

2+,R

W4

MO

VW

@P

C+

d16,

RW

4M

OVW

@R

W2+

,RW

5M

OV

W@

PC

+d1

6, R

W5

MO

VW@

RW

2+,R

W6

MO

VW

@P

C+

d16,

RW

6M

OVW

@R

W2+

,RW

7M

OV

W@

PC

+d1

6, R

W7

+F

MO

VW@

RW

3+,R

W0

MO

VW

addr

16, R

W0

MO

VW

@R

W3+

,RW

1M

OV

Wad

dr16

, RW

1M

OVW

@RW

3+,R

W2

MO

VW

addr

16, R

W2

MO

VW@

RW

3+,R

W3

MO

VW

addr

16, R

W3

MO

VW@

RW

3+,R

W4

MO

VW

addr

16, R

W4

MO

VW@

RW

3+,R

W5

MO

VW

addr

16, R

W5

MO

VW@

RW

3+,R

W6

MO

VW

addr

16, R

W6

MO

VW@

RW

3+,R

W7

MO

VW

addr

16, R

W7

466


Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH)

0010

2030

4050

6070

8090

AB

0C

0D

0E

0F

0

+0

XC

H R0,

R0

XC

H

R0,

@R

W0+

d8X

CH R

1, R

0X

CH

R

1,@

RW

0+d8

XC

H R2,

R0

XC

H

R2,

@R

W0+

d8X

CH R

3, R

0X

CH

R

3,@

RW

0+d8

XC

H R4,

R0

XC

H

R4,

@R

W0+

d8X

CH R

5, R

0X

CH

R

5,@

RW

0+d8

XC

H R6,

R0

XC

H

R6,

@R

W0+

d8X

CH R

7, R

0X

CH

R

7,@

RW

0+d8

+1

XC

H R0,

R1

XC

H

R0,

@R

W1+

d8X

CH R

1, R

1X

CH

R

1,@

RW

1+d8

XC

H R2,

R1

XC

H

R2,

@R

W1+

d8X

CH R

3, R

1X

CH

R

3,@

RW

1+d8

XC

H R4,

R1

XC

H

R4,

@R

W1+

d8X

CH R

5, R

1X

CH

R

5,@

RW

1+d8

XC

H R6,

R1

XC

H

R6,

@R

W1+

d8X

CH R

7, R

1X

CH

R

7,@

RW

1+d8

+2

XC

H R0,

R2

XC

H

R0,

@R

W2+

d8X

CH R

1, R

2X

CH

R

1,@

RW

2+d8

XC

H R2,

R2

XC

H

R2,

@R

W2+

d8X

CH R

3, R

2X

CH

R

3,@

RW

2+d8

XC

H R4,

R2

XC

H

R4,

@R

W2+

d8X

CH R

5, R

2X

CH

R

5,@

RW

2+d8

XC

H R6,

R2

XC

H

R6,

@R

W2+

d8X

CH R

7, R

2X

CH

R

7,@

RW

2+d8

+3

XC

H R0,

R3

XC

H

R0,

@R

W3+

d8X

CH R

1, R

3X

CH

R

1,@

RW

3+d8

XC

H R2,

R3

XC

H

R2,

@R

W3+

d8X

CH R

3, R

3X

CH

R

3,@

RW

3+d8

XC

H R4,

R3

XC

H

R4,

@R

W3+

d8X

CH R

5, R

3X

CH

R

5,@

RW

3+d8

XC

H R6,

R3

XC

H

R6,

@R

W3+

d8X

CH R

7, R

3X

CH

R

7,@

RW

3+d8

+4

XC

H R0,

R4

XC

H

R0,

@R

W4+

d8X

CH R

1, R

4X

CH

R

1,@

RW

4+d8

XC

H R2,

R4

XC

H

R2,

@R

W4+

d8X

CH R

3, R

4X

CH

R

3,@

RW

4+d8

XC

H R4,

R4

XC

H

R4,

@R

W4+

d8X

CH R

5, R

4X

CH

R

5,@

RW

4+d8

XC

H R6,

R4

XC

H

R6,

@R

W4+

d8X

CH R

7, R

4X

CH

R

7,@

RW

4+d8

+5

XC

H R0,

R5

XC

H

R0,

@R

W5+

d8X

CH R

1, R

5X

CH

R

1,@

RW

5+d8

XC

H R2,

R5

XC

H

R2,

@R

W5+

d8X

CH R

3, R

5X

CH

R

3,@

RW

5+d8

XC

H R4,

R5

XC

H

R4,

@R

W5+

d8X

CH R

5, R

5X

CH

R

5,@

RW

5+d8

XC

H R6,

R5

XC

H

R6,

@R

W5+

d8X

CH R

7, R

5X

CH

R

7,@

RW

5+d8

+6

XC

H R0,

R6

XC

H

R0,

@R

W6+

d8X

CH R

1, R

6X

CH

R

1,@

RW

6+d8

XC

H R2,

R6

XC

H

R2,

@R

W6+

d8X

CH R

3, R

6X

CH

R

3,@

RW

6+d8

XC

H R4,

R6

XC

H

R4,

@R

W6+

d8X

CH R

5, R

6X

CH

R

5,@

RW

6+d8

XC

H R6,

R6

XC

H

R6,

@R

W6+

d8X

CH R

7, R

6X

CH

R

7,@

RW

6+d8

+7

XC

H R0,

R7

XC

H

R0,

@R

W7+

d8X

CH R

1, R

7X

CH

R

1,@

RW

7+d8

XC

H R2,

R7

XC

H

R2,

@R

W7+

d8X

CH R

3, R

7X

CH

R

3,@

RW

7+d8

XC

H R4,

R7

XC

H

R4,

@R

W7+

d8X

CH R

5, R

7X

CH

R

5,@

RW

7+d8

XC

H R6,

R7

XC

H

R6,

@R

W7+

d8X

CH R

7, R

7X

CH

R

7,@

RW

7+d8

+8

XC

HR

0,@

RW

0X

CH

R

0,@

RW

0+d1

6X

CH

R1,

@R

W0

XC

H

R1,

@R

W0+

d16

XC

HR

2,@

RW

0X

CH

R

2,@

RW

0+d1

6X

CH

R3,

@R

W0

XC

H

R3,

@R

W0+

d16

XC

HR

4,@

RW

0X

CH

R

4,@

RW

0+d1

6X

CH

R5,

@R

W0

XC

H

R5,

@R

W0+

d16

XC

HR

6,@

RW

0X

CH

R

6,@

RW

0+d1

6X

CH

R7,

@R

W0

XC

H

R7,

@R

W0+

d16

+9

XC

HR

0,@

RW

1X

CH

R

0,@

RW

1+d1

6X

CH

R1,

@R

W1

XC

H

R1,

@R

W1+

d16

XC

HR

2,@

RW

1X

CH

R

2,@

RW

1+d1

6X

CH

R3,

@R

W1

XC

H

R3,

@R

W1+

d16

XC

HR

4,@

RW

1X

CH

R

4,@

RW

1+d1

6X

CH

R5,

@R

W1

XC

H

R5,

@R

W1+

d16

XC

HR

6,@

RW

1X

CH

R

6,@

RW

1+d1

6X

CH

R7,

@R

W1

XC

H

R7,

@R

W1+

d16

+A

XC

HR

0,@

RW

2X

CH

R

0,W

2+d1

6, A

XC

HR

1,@

RW

2X

CH

R

1,W

2+d1

6, A

XC

HR

2,@

RW

2X

CH

R

2,W

2+d1

6, A

XC

HR

3,@

RW

2X

CH

R

3,W

2+d1

6, A

XC

HR

4,@

RW

2X

CH

R

4,W

2+d1

6, A

XC

HR

5,@

RW

2X

CH

R

5,W

2+d1

6, A

XC

HR

6,@

RW

2X

CH

R

6,W

2+d1

6, A

XC

HR

7,@

RW

2X

CH

R

7,W

2+d1

6, A

+B

XC

HR

0,@

RW

3X

CH

R

0,@

RW

3+d1

6X

CH

R1,

@R

W3

XC

H

R1,

@R

W3+

d16

XC

HR

2,@

RW

3X

CH

R

2,@

RW

3+d1

6X

CH

R3,

@R

W3

XC

H

R3,

@R

W3+

d16

XC

HR

4,@

RW

3X

CH

R

4,@

RW

3+d1

6X

CH

R5,

@R

W3

XC

H

R5,

@R

W3+

d16

XC

HR

6,@

RW

3X

CH

R

6,@

RW

3+d1

6X

CH

R7,

@R

W3

XC

H

R7,

@R

W3+

d16

+C

XC

HR

0,@

RW

0+XC

H

R0,

@R

W0+

RW7

XC

HR

1,@

RW

0+XC

H

R1,

@R

W0+

RW7

XC

HR

2,@

RW

0+XC

H

R2,

@RW

0+R

W7

XC

HR

3,@

RW

0+XC

H

R3,

@RW

0+R

W7

XC

HR

4,@

RW

0+XC

H

R4,

@R

W0+

RW7

XC

HR

5,@

RW

0+XC

H

R5,

@R

W0+

RW

7X

CH

R6,

@R

W0+

XCH

R

6,@

RW0+

RW

7X

CH

R7,

@R

W0+

XCH

R

7,@

RW

0+RW

7

+D

XC

HR

0,@

RW

1+XC

H

R0,

@R

W1+

RW7

XC

HR

1,@

RW

1+XC

H

R1,

@R

W1+

RW7

XC

HR

2,@

RW

1+XC

H

R2,

@RW

1+R

W7

XC

HR

3,@

RW

1+XC

H

R3,

@RW

1+R

W7

XC

HR

4,@

RW

1+XC

H

R4,

@R

W1+

RW7

XC

HR

5,@

RW

1+XC

H

R5,

@R

W1+

RW

7X

CH

R6,

@R

W1+

XCH

R

6,@

RW1+

RW

7X

CH

R7,

@R

W1+

XCH

R

7,@

RW

1+RW

7

+E

XC

HR

0,@

RW

2+X

CH

R

0,@

PC

+d1

6X

CH

R1,

@R

W2+

XC

H

R1,

@P

C+

d16

XC

HR

2,@

RW

2+X

CH

R

2,@

PC

+d1

6X

CH

R3,

@R

W2+

XC

H

R3,

@P

C+

d16

XC

HR

4,@

RW

2+X

CH

R

4,@

PC

+d1

6X

CH

R5,

@R

W2+

XC

H

R5,

@P

C+

d16

XC

HR

6,@

RW

2+X

CH

R

6,@

PC

+d1

6X

CH

R7,

@R

W2+

XC

H

R7,

@P

C+

d16

+F

XC

HR

0,@

RW

3+X

CH

R0,

add

r16

XC

HR

1,@

RW

3+X

CH

R1,

add

r16

XC

HR

2,@

RW

3+X

CH

R2,

add

r16

XC

HR

3,@

RW

3+X

CH

R3,

add

r16

XC

HR

4,@

RW

3+X

CH

R4,

add

r16

XC

HR

5,@

RW

3+X

CH

R5,

add

r16

XC

HR

6,@

RW

3+X

CH

R6,

add

r16

XC

HR

7,@

RW

3+X

CH

R7,

add

r16

467


Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

XC

HW

RW

0, R

W0

XC

HW

RW

0,@

RW

0+d8

XC

HW

RW

1, R

W0

XC

HW

RW

1,@

RW

0+d8

XC

HW

RW

2, R

W0

XC

HW

RW

2,@

RW

0+d8

XC

HW

RW

3, R

W0

XC

HW

RW

3,@

RW

0+d8

XC

HW

RW

4, R

W0

XC

HW

RW

4,@

RW

0+d8

XC

HW

RW

5, R

W0

XC

HW

RW

5,@

RW

0+d8

XC

HW

RW

6, R

W0

XC

HW

RW

6,@

RW

0+d8

XC

HW

RW

7, R

W0

XC

HW

RW

7,@

RW

0+d8

+1

XC

HW

RW

0, R

W1

XC

HW

RW

0,@

RW

1+d8

XC

HW

RW

1, R

W1

XC

HW

RW

1,@

RW

1+d8

XC

HW

RW

2, R

W1

XC

HW

RW

2,@

RW

1+d8

XC

HW

RW

3, R

W1

XC

HW

RW

3,@

RW

1+d8

XC

HW

RW

4, R

W1

XC

HW

RW

4,@

RW

1+d8

XC

HW

RW

5, R

W1

XC

HW

RW

5,@

RW

1+d8

XC

HW

RW

6, R

W1

XC

HW

RW

6,@

RW

1+d8

XC

HW

RW

7, R

W1

XC

HW

RW

7,@

RW

1+d8

+2

XC

HW

RW

0, R

W2

XC

HW

RW

0,@

RW

2+d8

XC

HW

RW

1, R

W2

XC

HW

RW

1,@

RW

2+d8

XC

HW

RW

2, R

W2

XC

HW

RW

2,@

RW

2+d8

XC

HW

RW

3, R

W2

XC

HW

RW

3,@

RW

2+d8

XC

HW

RW

4, R

W2

XC

HW

RW

4,@

RW

2+d8

XC

HW

RW

5, R

W2

XC

HW

RW

5,@

RW

2+d8

XC

HW

RW

6, R

W2

XC

HW

RW

6,@

RW

2+d8

XC

HW

RW

7, R

W2

XC

HW

RW

7,@

RW

2+d8

+3

XC

HW

RW

0, R

W3

XC

HW

RW

0,@

RW

3+d8

XC

HW

RW

1, R

W3

XC

HW

RW

1,@

RW

3+d8

XC

HW

RW

2, R

W3

XC

HW

RW

2,@

RW

3+d8

XC

HW

RW

3, R

W3

XC

HW

RW

3,@

RW

3+d8

XC

HW

RW

4, R

W3

XC

HW

RW

4,@

RW

3+d8

XC

HW

RW

5, R

W3

XC

HW

RW

5,@

RW

3+d8

XC

HW

RW

6, R

W3

XC

HW

RW

6,@

RW

3+d8

XC

HW

RW

7, R

W3

XC

HW

RW

7,@

RW

3+d8

+4

XC

HW

RW

0, R

W4

XC

HW

RW

0,@

RW

4+d8

XC

HW

RW

1, R

W4

XC

HW

RW

1,@

RW

4+d8

XC

HW

RW

2, R

W4

XC

HW

RW

2,@

RW

4+d8

XC

HW

RW

3, R

W4

XC

HW

RW

3,@

RW

4+d8

XC

HW

RW

4, R

W4

XC

HW

RW

4,@

RW

4+d8

XC

HW

RW

5, R

W4

XC

HW

RW

5,@

RW

4+d8

XC

HW

RW

6, R

W4

XC

HW

RW

6,@

RW

4+d8

XC

HW

RW

7, R

W4

XC

HW

RW

7,@

RW

4+d8

+5

XC

HW

RW

0, R

W5

XC

HW

RW

0,@

RW

5+d8

XC

HW

RW

1, R

W5

XC

HW

RW

1,@

RW

5+d8

XC

HW

RW

2, R

W5

XC

HW

RW

2,@

RW

5+d8

XC

HW

RW

3, R

W5

XC

HW

RW

3,@

RW

5+d8

XC

HW

RW

4, R

W5

XC

HW

RW

4,@

RW

5+d8

XC

HW

RW

5, R

W5

XC

HW

RW

5,@

RW

5+d8

XC

HW

RW

6, R

W5

XC

HW

RW

6,@

RW

5+d8

XC

HW

RW

7, R

W5

XC

HW

RW

7,@

RW

5+d8

+6

XC

HW

RW

0, R

W6

XC

HW

RW

0,@

RW

6+d8

XC

HW

RW

1, R

W6

XC

HW

RW

1,@

RW

6+d8

XC

HW

RW

2, R

W6

XC

HW

RW

2,@

RW

6+d8

XC

HW

RW

3, R

W6

XC

HW

RW

3,@

RW

6+d8

XC

HW

RW

4, R

W6

XC

HW

RW

4,@

RW

6+d8

XC

HW

RW

5, R

W6

XC

HW

RW

5,@

RW

6+d8

XC

HW

RW

6, R

W6

XC

HW

RW

6,@

RW

6+d8

XC

HW

RW

7, R

W6

XC

HW

RW

7,@

RW

6+d8

+7

XC

HW

RW

0, R

W7

XC

HW

RW

0,@

RW

7+d8

XC

HW

RW

1, R

W7

XC

HW

RW

1,@

RW

7+d8

XC

HW

RW

2, R

W7

XC

HW

RW

2,@

RW

7+d8

XC

HW

RW

3, R

W7

XC

HW

RW

3,@

RW

7+d8

XC

HW

RW

4, R

W7

XC

HW

RW

4,@

RW

7+d8

XC

HW

RW

5, R

W7

XC

HW

RW

5,@

RW

7+d8

XC

HW

RW

6, R

W7

XC

HW

RW

6,@

RW

7+d8

XC

HW

RW

7, R

W7

XC

HW

RW

7,@

RW

7+d8

+8

XC

HW

RW

0,@

RW

0X

CH

W R

W0,

@R

W0+

d16

XC

HW

RW

1,@

RW

0X

CH

W R

W1,

@R

W0+

d16

XC

HW

RW

2,@

RW

0X

CH

W R

W2,

@R

W0+

d16

XC

HW

RW

3,@

RW

0X

CH

W R

W3,

@R

W0+

d16

XC

HW

RW

4,@

RW

0X

CH

W R

W4,

@R

W0+

d16

XC

HW

RW

5,@

RW

0X

CH

W R

W5,

@R

W0+

d16

XC

HW

RW

6,@

RW

0X

CH

W R

W6,

@R

W0+

d16

XC

HW

RW

7,@

RW

0X

CH

W R

W7,

@R

W0+

d16

+9

XC

HW

RW

0,@

RW

1X

CH

W R

W0,

@R

W1+

d16

XC

HW

RW

1,@

RW

1X

CH

W R

W1,

@R

W1+

d16

XC

HW

RW

2,@

RW

1X

CH

W R

W2,

@R

W1+

d16

XC

HW

RW

3,@

RW

1X

CH

W R

W3,

@R

W1+

d16

XC

HW

RW

4,@

RW

1X

CH

W R

W4,

@R

W1+

d16

XC

HW

RW

5,@

RW

1X

CH

W R

W5,

@R

W1+

d16

XC

HW

RW

6,@

RW

1X

CH

W R

W6,

@R

W1+

d16

XC

HW

RW

7,@

RW

1X

CH

W R

W7,

@R

W1+

d16

+A

XC

HW

RW

0,@

RW

2X

CH

W R

W0,

@R

W2+

d16

XC

HW

RW

1,@

RW

2X

CH

W R

W1,

@R

W2+

d16

XC

HW

RW

2,@

RW

2X

CH

W R

W2,

@R

W2+

d16

XC

HW

RW

3,@

RW

2X

CH

W R

W3,

@R

W2+

d16

XC

HW

RW

4,@

RW

2X

CH

W R

W4,

@R

W2+

d16

XC

HW

RW

5,@

RW

2X

CH

W R

W5,

@R

W2+

d16

XC

HW

RW

6,@

RW

2X

CH

W R

W6,

@R

W2+

d16

XC

HW

RW

7,@

RW

2X

CH

W R

W7,

@R

W2+

d16

+B

XC

HW

RW

0,@

RW

3X

CH

W R

W0,

@R

W3+

d16

XC

HW

RW

1,@

RW

3X

CH

W R

W1,

@R

W3+

d16

XC

HW

RW

2,@

RW

3X

CH

W R

W2,

@R

W3+

d16

XC

HW

RW

3,@

RW

3X

CH

W R

W3,

@R

W3+

d16

XC

HW

RW

4,@

RW

3X

CH

W R

W4,

@R

W3+

d16

XC

HW

RW

5,@

RW

3X

CH

W R

W5,

@R

W3+

d16

XC

HW

RW

6,@

RW

3X

CH

W R

W6,

@R

W3+

d16

XC

HW

RW

7,@

RW

3X

CH

W R

W7,

@R

W3+

d16

+C

XC

HW

RW

0,@

RW

0+X

CH

W R

W0,

@R

W0+

RW

7X

CH

WR

W1,

@R

W0+

XC

HW

RW

1,@

RW

0+R

W7

XC

HW

RW

2,@

RW

0+X

CH

W R

W2,

@R

W0+

RW

7X

CH

WR

W3,

@R

W0+

XC

HW

RW

3,@

RW

0+R

W7

XC

HW

RW

4,@

RW

0+X

CH

W R

W4,

@R

W0+

RW

7X

CH

WR

W5,

@R

W0+

XC

HW

RW

5,@

RW

0+R

W7

XC

HW

RW

6,@

RW

0+X

CH

W R

W6,

@R

W0+

RW

7X

CH

WR

W7,

@R

W0+

XC

HW

RW

7,@

RW

0+R

W7

+D

XC

HW

RW

0,@

RW

1+X

CH

W R

W0,

@R

W1+

RW

7X

CH

WR

W1,

@R

W1+

XC

HW

RW

1,@

RW

1+R

W7

XC

HW

RW

2,@

RW

1+X

CH

W R

W2,

@R

W1+

RW

7X

CH

WR

W3,

@R

W1+

XC

HW

RW

3,@

RW

1+R

W7

XC

HW

RW

4,@

RW

1+X

CH

W R

W4,

@R

W1+

RW

7X

CH

WR

W5,

@R

W1+

XC

HW

RW

5,@

RW

1+R

W7

XC

HW

RW

6,@

RW

1+X

CH

W R

W6,

@R

W1+

RW

7X

CH

WR

W7,

@R

W1+

XC

HW

RW

7,@

RW

1+R

W7

+E

XC

HW

RW

0,@

RW

2+X

CH

W R

W0,

@P

C+d

16X

CH

WR

W1,

@R

W2+

XC

HW

RW

1,@

PC

+d16

XC

HW

RW

2,@

RW

2+X

CH

W R

W2,

@P

C+d

16X

CH

WR

W3,

@R

W2+

XC

HW

RW

3,@

PC

+d16

XC

HW

RW

4,@

RW

2+X

CH

W R

W4,

@P

C+d

16X

CH

WR

W5,

@R

W2+

XC

HW

RW

5,@

PC

+d16

XC

HW

RW

6,@

RW

2+X

CH

W R

W6,

@P

C+d

16X

CH

WR

W7,

@R

W2+

XC

HW

RW

7,@

PC

+d16

+F

XC

HW

RW

0,@

RW

3+X

CH

WR

W0,

add

r16

XC

HW

RW

1,@

RW

3+X

CH

WR

W1,

add

r16

XC

HW

RW

2,@

RW

3+X

CH

WR

W2,

add

r16

XC

HW

RW

3,@

RW

3+X

CH

WR

W3,

add

r16

XC

HW

RW

4,@

RW

3+X

CH

WR

W4,

add

r16

XC

HW

RW

5,@

RW

3+X

CH

WR

W5,

add

r16

XC

HW

RW

6,@

RW

3+X

CH

WR

W6,

add

r16

XC

HW

RW

7,@

RW

3+X

CH

WR

W7,

add

r16

468

INDEX

INDEX

The index follows on the next page.This is listed in alphabetic order.

469

INDEX

Index

Numerics

16-bit free-running timer.......................................17016-bit free-running timer block diagram................17316-bit free-running timer operation.......................17716-bit free-running timer timing ............................17816-bit I/O timer register ........................................17216-bit I/O timer, block diagram of .........................17116-bit reload timer (in internal clock mode), input pin

function of ..................................................20216-bit reload timer (with event count function), outline

of ................................................................19416-bit reload timer register ...................................19616-bit reload timer, block diagram of....................19516-bit reload timer, internal clock operation of .....20116-bit reload timer, output pin function of.............20416-bit reload timer, underflow operation of...........20316-bit timer register (TMR)/16-bit reload register

(TMRLR) ....................................................2001M/2M-bit flash memory feature...........................3501M/2M-bit flash memory, sector configuration of .35124-bit operand specification ...................................2532-bit register indirect specification........................258/16-bit PPG hardware, initial value of .................2258/16-bit PPG output operation..............................2218/16-bit PPG Pulses, controlling pin output of......2238/16-bit PPG register............................................2118/16-bit PPG, function of ......................................2088/16-bit PPG, operation modes of ........................2208/16-bit PPG, operation of....................................2208/16-bit PPG, selecting count clock for ................222

A

A/D Control Status Register (ADCS1)..................249A/D converter register ..........................................245A/D converter, block diagram of...........................244A/D converter, features of ....................................242accumulator (A)......................................................31address generation type.........................................23address match detection function, block diagram of

...................................................................338address match detection function, operation of ...341address match detection function, system

configuration example of ............................342Addressing ..........................................................410alternative mode...................................................352

analog input enable register................................. 243analog input enable register (ADER) ................... 150application example of UART0 ............................ 288asynchronous (start-stop synchronized) mode data

transfer format ........................................... 307asynchronous (start-stop synchronized) mode

receive operation ....................................... 307asynchronous (start-stop synchronized) mode

transmit operation ...................................... 307automatic ready function selection register (ARSR)

................................................................... 131

B

bank addressing type............................................. 26bank select prefix ................................................... 40block diagram........................................................... 5block diagram of 8/16-bit PPG............................. 209buffer address pointer (BAP) ................................. 66bus control signal selection register (ECSR) ....... 134

C

Calculating the Execution Cycle Count ............... 427CLK asynchronous baud rate .............................. 277CLK synchronous baud rate ................................ 277CLK synchronous mod, control register setting for

................................................................... 308CLK synchronous mode data transfer format ...... 308CLK synchronous mode, end of communication in

................................................................... 309CLK synchronous mode, start of communication in

................................................................... 309clock generator, note on ........................................ 74clock selection register (CKSCR)........................... 91command sequence table.................................... 356common register bank prefix (CMR)...................... 41compare registers 0 and 1 being used, output

waveform sample when ............................. 184compare registers, output waveform sample with two

................................................................... 185condition code register (CCR)................................ 34continuous mode.................................................. 254continuous mode, starting EI2OS in .................... 259control status register........................................... 188control status register (ADCS0) ........................... 246conversion data protection................................... 263

470

INDEX

counter operation state ........................................ 205CPU memory space, outline of .............................. 23CPU, outline of....................................................... 22

D

data counter (DCT) ................................................ 64data polling flag (DQ7) ......................................... 360data registers (ADCR1 and ADCR0) ................... 252delayed interrupt cause issuance/cancellation

register (DIRR)........................................... 229delayed interrupt occurrence ............................... 230delayed interrupt, block diagram of...................... 228Description of Instruction Presentation Items and

Symbols .................................................... 430Direct Addressing ................................................ 412DIV A, Ri and DIVW A, RWi instruction, note on using

..................................................................... 43DTP operation...................................................... 237DTP request, switching between external interrupt

and............................................................. 238DTP/External interrup, block diagram of .............. 232DTP/External interrup, outline of.......................... 232DTP/External interrupt register ............................ 233DTP/external interrupt, note on using .................. 239

E

Effective Address Field ............................... 411, 429EI2OS (extended intelligent I/O service).............. 287EI2OS, conversion using ..................................... 256erasing chip.......................................................... 372erasing flash memory........................................... 350erasing sector ...................................................... 373erasing sector in flash memory ............................ 373exception due to execution of an undefined

instruction .................................................... 71Execution Cycle Count ........................................ 426extended intelligent I/O service (EI2OS)........ 59, 316extended intelligent I/O service (EI2OS), execution

time of the .................................................... 69extended intelligent I/O service (EI2OS), operation

flow of .......................................................... 67extended intelligent I/O service descriptor (ISD).... 64extended serial I/O interface, interrupt function of

................................................................... 334external address output control register (HACR) . 133external clock ....................................................... 280external event counter ......................................... 202external interrupt operation .................................. 236external interrupt request ..................................... 238external interrupt request register ........................ 234

external level register ...........................................235external memory access (bus pin control circuit) .129external memory access control signal ................137external memory access register..........................130external memory access, block diagram of ..........129external shift clock mode ......................................328

F

F2MC-16LX Instruction List .................................433feature ......................................................................3flag change disable prefix (NCC)............................41flag set timing .......................................................311flag set timing for a transmit operation .................286flag set timings for a receive operation (in Mode 0, 1,

or 3) ............................................................284flag set timings for a receive operation (in Mode 2)

...................................................................285flash memory control signal..................................352flash memory control status register (FMCS) .......354flash memory mode ..............................................352flash memory register ...........................................350flash memory write/erase, detailed explanation of

...................................................................368flash memory, writing data to................................370flash memory, writing to........................................370flash microcomputer programmer (power supplied

from programmer), example of minimum connection to ..............................................396

flash microcomputer programmer (user power supplyused), example of minimum connection to...................................................................394

flash security feature ............................................379flow of data protection function (when EI2OS is use)

...................................................................264FPT-100P-M05 package dimension .........................7FPT-100P-M06 package dimension .........................6

G

general-purpose register ........................................30

H

handling the device.................................................18hardware interrupt ..................................................51hardware interrupt operation ..................................53hardware interrupt operation, flow of ......................56hardware interrupt request during writing to the input-

output area ...................................................51hardware interrupt, structure of ..............................51hardware sequence flag .......................................358hardware standby mode, releasing ......................107

471

INDEX

hardware standby mode, transition to ..................107hold function.........................................................141

I

i/o circuit .................................................................15I/O map ................................................................400I/O port register ....................................................145I/O ports, outline of...............................................144I/O register address pointer (IOA) ..........................64Indirect Addressing .............................................418input capture ........................................................187input capture (2 channel per one module) ...........171input capture block diagram .................................187input capture data register ...................................188input capture fetch timing, sample of ...................190input capture input timing .....................................191input data register 0 (UIDR0) ...............................273input impedance...................................................243Instruction Types .................................................409intelligent I/O service (EI2OS) function and interrupt

...................................................................194intermittent CPU operation...................................108intermittent CPU operation function .......................84internal and external clock ...................................280internal shift clock mode.......................................328interrupt control register (ICR)................................61interrupt disable instruction ....................................42interrupt level mask register (ILM)..........................35interrupt request enable register ..........................234interrupt source ......................................................47interrupt vector .......................................................49interrupt, 8/16-bit PPG .........................................224interrupt, intelligent I/O service (EI2OS) function and

...................................................................194interrupt, outline of .................................................46interrupt/DTP cause register ................................234interrupt/DTP enable register ...............................234

L

low-power consumption mode................................98

low-power consumption mode, operation status of...................................................................100

low-power control circuit, block diagram of ............86low-power control circuit, operation modes of ........84low-power mode control register ............................87low-power mode control register (LPMCR) ............88low-power mode control register, access to...........90

M

main clock oscillation stabilization wait time .......... 84MB90435 series product, overview of...................... 2MB90F438L(S)/F439(S) serial programming

connection, basic configuration of ............. 386memory access mode.......................................... 124memory space in each bus mode........................ 127memory space map ............................................... 24mode data............................................................ 126mode pin .............................................................. 125multi-byte data allocation in memory space........... 28multi-byte data, accessing ..................................... 28multiple interrupt .................................................... 52

N

negative clock operation ...................................... 335notes on using the conversion data protection

function ...................................................... 264notes, evasion of.................................................... 44

O

operation after reset release.................................. 76operation, note on................................................ 228oscillation clock frequency and serial clock input

frequency................................................... 389Outline of Interrupts ............................................... 46output compare.................................................... 179output compare (2 channel per one module) ....... 170output compare block diagram............................. 179output compare register ....................................... 180output compare timing ......................................... 185output compare, control status register of............ 181output data register 0 (UODR0)........................... 273

P

parity bit ............................................................... 282pin assignment......................................................... 8pin function............................................................. 10PLL clock multiplication function............................ 85port data register (PDR)....................................... 146port direction register (DDR)................................ 147PPG0 operation mode control register (PPGC0). 212PPG0, 1 clock selection register (PPG0/1) .......... 217PPG1 operation mode control register (PPGC1). 214precautions for UART1 use.................................. 316prefix code ............................................................. 42prefix code, consecutive ........................................ 42processor status (PS) ............................................ 34

472

INDEX

program address detection control status register (PACSR) .................................................... 339

program address detection register (PADR0 and PADR1)...................................................... 339

program counter (PC) ............................................ 37program patch processing, example of................ 343programming example of 1M/2M-bit flash memory

................................................................... 380pseudo watch mode, releasing ............................ 103pseudo watch mode, transition to ........................ 103PT-100P-M06 Package Dimensions.................... 6, 7pull-up control register (PUCR)............................ 148pull-up control register (PUCR), block diagram of

................................................................... 149

R

rate and data register 0 (URD0)........................... 274read state, setting flash memory to...................... 369ready function ...................................................... 139receive operation ................................................. 287recommended set ................................................ 128register bank .......................................................... 38register bank pointer (RP)...................................... 35register saving onto stack ...................................... 52releasing sleep mode........................................... 102reload register (PRLL/PRLH) ............................... 219reload value and pulse width, relationship between

8/16-bit PPG .............................................. 221request level setting register ................................ 235reset cause ............................................................ 80reset cause occurrence.......................................... 75reset input, register not initialized by...................... 77reset state, setting flash memory to ..................... 369restrictions on interrupt disable instruction and prefix

instruction .................................................... 42ROM mirroring ÇÜunction selection module, block

diagram of.................................................. 346ROM mirroring function selection register (ROMM)

................................................................... 347

S

sector erase timer flag (DQ3)............................... 364sector, restarting erasing of flash memory........... 376sector, suspending erasing of flash memory ....... 375serial control register 1 (SCR1)............................ 297serial I/O block diagram ....................................... 318serial I/O operation....................................... 327, 329serial I/O prescaler (SCDCR)............................... 326serial I/O resister.................................................. 319

serial input data register 1 (SIDR1)/serial output data register 1 (SODR1).....................................299

serial mode control register 0 (UMC)....................269serial mode control status register (SMCS)..........320serial mode register 1 (SMR1)..............................295serial output data register 1 (SODR1) ..................299serial programming connection (power supplied from

programmer), example of ...........................392serial programming connection (user power supply

used), example of.......................................390serial shift data register (SDR) .............................325serial statu register 1 (SSR1) ...............................300set timing of six flags ............................................283shift operation Start/Stop timing ...........................331single mode ..........................................................254single mode, starting EI2OS in .............................257sleep mode, transition to ......................................102software interrupt....................................................57software interrupt operation....................................57software interrupt, note on......................................58software interrupt, structure of................................57special register .......................................................29start-stop synchronized mode data transfer format

...................................................................307start-stop synchronized mode receive operation..307start-stop synchronized mode transmit operation.307status flag during transmit and receive operation.287status register0 (USR0) ........................................271status transition diagram for low-power consumption

mode (one clock system parts) ..................119status transition diagram for low-power consumption

mode (two clocks system parts) .................114status transition for clock selection.........................94stop mode.............................................................255stop mode, releasing ............................................105stop mode, starting EI2OS in................................261stop mode, transition to ........................................105structure..................................................................60Structure of Instruction Map ................................447switching between machine clock ..........................85system configuration in mode 1............................315

T

timebase timer ......................................................156timebase timer control register (TBTC) ................154timebase timer register .........................................152timebase timer, Block Diagram of.........................153timer control register (TMSCR).............................197timer counter control status register .....................175

473

INDEX

timer counter data register (TCDT) ......................174timing limit exceeded flag (DQ5) ..........................363toggle bit 2 flag (DQ2) ..........................................366toggle bit flag (DQ6) .............................................362transfer data format..............................................281transition conditions in low-power consumption mode

...................................................................109

U

UART block diagram ............................................267UART0 operation mode .......................................276UART0 register ....................................................268UART0, feature of ................................................266UART1 block diagram ..........................................293UART1 clock selection .........................................304UART1 communication flow chart ........................315UART1 flag...........................................................310UART1 interrupt and flag set timing .....................311UART1 interrupt source .......................................310UART1 operating mode .......................................303

UART1 prescaler control register (U1CDCR) ...... 302UART1 register .................................................... 294UART1 sample application (system configuration in

mode 1)...................................................... 315UART1, features of .............................................. 292user power supply........................................ 390, 394user stack pointer (USP) and system stack pointer

(SSP) ........................................................... 33

W

watch mode, releasing ......................................... 104watch mode, transition to..................................... 104watch timer........................................................... 168watch timer register.............................................. 164watch timer, interval interrupt function of ............. 168watch-dog timer control register (WDTC) ............ 160watch-dog timer control register (WTC) ............... 166watch-dog timer register ...................................... 158watch-dog timer, activating .................................. 162watch-dog timer, resetting.................................... 162writing to flash memory........................................ 350

474

CM44-10123-2E

FUJITSU MICROELECTRONICS • CONTROLLER MANUAL

F2MC-16LX

16-BIT MICROCONTROLLER

MB90435 Series

HARDWARE MANUAL

July 2008 the second edition

Published FUJITSU MICROELECTRONICS LIMITEDEdited Strategic Business Development Dept.

f2mc-16lx - fujitsu€¦ · i preface objectives and intended reader thank you for your continued...

Documents