extra cache examples

8/7/2019 Extra Cache Examples

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Extra Cache Coherence Examples

In the following examples there are a couple

questions. You can answer these for practice by

emailing Colin at [email protected].


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MSI Protocol

There are three processors. Each is

reading/writing the same value from

memory where r1 means a read by

processor 1 and w3 means a write by

processor 3. For simplicity sake, the

memory location will be referred to asvalue. The memory access stream is:

r1, r2, w3, r2, w1, w2, r3, r2, r1


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P1 wants to read the value. The cache does nothave itand generates a BusRd for the data. Main

memory controller provides the data. The data goes

into the cache in the shared state.

P1 P3P2

Snooper Snooper Snooper

PrRd

BusRd

r1

value S

Main Memory


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P1 P3P2


value S

PrRd

BusRd

r2

value S

P2 wants to read the value. Its cache does not have the

data, so it places a BusRd to notify other processors

and ask for the data. The memory controller provides

the data.

Main Memory


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P1 P3P2


value S

w3

value S

P3 wants to write the value. It places a BusRdX to getexclusive access and the most recent copy of the data.

The caches of P1 and P2 see the BusRdX and

invalidate their copies. Because the value is still up-to-

date in memory, memory provides the data.

PrWr

BusRdX

I I value M

Main Memory


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Main Memory

P1 P3P2


value Mvalue I

r2

value I

P2 wants to read the value. P3s cache has the mostup-to-date copy and will provide it. P2s cache puts a

BusRd on the bus. P3s cache snoops this and cancels

the memory access because it will provide the data.

P3s cache flushes the data to the bus.

PrRd

BusRd

S S

Flush


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P1 P3P2


value Svalue I

w1

value S

P1 wants to write to its cache. The cache places aBusRdX on the bus to gain exclusive access and the

most up-to-date value. Main memory is not stale so it

provides the data. The snoopers for P2 and P3 see the

BusRdX and invalidate their copies in cache.

PrWr

BusRdX

I IM

Main Memory


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P1 P3P2


value Ivalue M

w2

value I

P2 wants to write the value. Its cache places a BusRdXto get exclusive access and the most recent copy of the

data. P1s snooper sees the BusRdX and flushes the

data to the bus. Also, it invalides the data in its cache

and cancels the memory access.

PrWr

BusRdX

I M

Flush

Main Memory


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Main Memory

P1 P3P2


value Ivalue I

r3

value M

P3 wants to read the value. Its cache does not have avalid copy, so it places a BusRd on the bus. P2 has a

modified copy, so it flushes the data on the bus and

changes the status of the cache data to shared. The

flush cancels the memory accecss and updates the

data in memory as well.

PrRd

BusRdFlush

S S


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P1 P3P2


value Svalue I

r2

value S

P2 wants to read the value. Its cache has an up-to-datecopy. No bus transactions need to take place as there

is no cache miss.

PrRd

Main Memory


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P1 P3P2


value Svalue I

r1

value S

P1 wants to read the value. The cache does not haveit, so it places a BusRd onto the bus for the data. The

memory controller provides the data as it has an up-to-

date copy. The data goes into the cache in the shared

state.

PrRd

BusRd

S

Main Memory


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MES

I ProtocolThere are three processors. Each is

loading or storing different words from

memory given as w0, w1, and w2.These all map to the same location in

cache.


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The memory accesses are as follows:

P1: ld w0, P3: ld w2

P1: st w0, P2: st w2

P2 st w2, P3 ld w0

P3: st w0

P1: ld w2

P2: ld w1

P3: ld w1


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In both loads, a cache miss happens so each cacheputs a BusRd onto the bus for the information. Main

memory is the owner and will provide the up-to-date

data. P1s cache loads w0 in the E state. P3s cache

loads w2 in the E state as well.

P1 P3


PrRd

BusRd(S)

P1 ld w0

P3 ld w2PrRd

BusRd (S)

P2

w0 E w2 E

Main Memory


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P1 has w0 in the exclusive state, so on the cache hit, it doesnot need to have a bus transaction. w2 is not in P2s cache,

so the cache places a BusRdX to gain exclusive access.

Main memory provides the data because it is not stale even

though P3s cache has the data. w2 is loaded in M state and

P3s cache invalidates its copy of w2.

P1 P3


w2 Ew0 E

PrWr

P1 st w0

P2 st w2

Flush

P2

PrWr

BusRdX

IM w2 M

Main Memory


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Main Memory

P2 executes another store to w2. It already has exclusiveaccess to w2 and the store results in a cache hit. No bus

transaction is issued by P2s cache. P3 wants to load w0. This

results in a cache miss and the cache issues a BusRd

transaction. P1s cache asserts the S signal because it has a

dirty w0 and provides the up-to-date data through a flush. P1

changes its state to S. P3s cache loads w0 in the S state.

P1 P3


w2 Iw0 M

P2 st w0

P3 ld w0 P2

w2 M

PrWr PrRd

BusRd(S)Flush

S w0 S


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P3 executes a store to w0. Both P1 and P3 have an up-to-date,unmodified w0. What bus transactions are needed?

P1 P3


w0 Sw0 S

P3 st w0

P2

w2 MI

PrWr

M

Main Memory


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Main Memory

P1 wants to load w2. P1s cache does not have w2, so it issuesa BusRd transaction. P2s cache turns on the S signal, so P1s

cache knows to load w2 in the S state. P2s cache provides w2

for P1 and cancels the access to main memory through a

Flush.

P1 P3


w0 Mw0 S

P1 ld w2

P2

w2 M

PrRd

BusRd(S)

S

Flush

Sw2


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P2 wants to load w1. This generates a cache miss. P2s cacheissues a BusRd transaction. The S signal is not asserted, so it

knows that it has exclusive access to w1. Main memory

provides the data for w1. Should the state of w2 be changed in

P1 because it is the only cache that has a copy of w2?

P1 P3


w0 Mw2 S

P2 ld w1

P2

w2 S

PrRd

BusRd(S)

Ew1

Main Memory


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Dragon Protocol

In this system there are 3 processors.

Each is loading or storing from memory

locations w0, w1, w2, and w3. w0 andw1 are on the same cache line and are

loaded at the same time. Likewise for

w2 and w3. The two cache lines map tothe same location in cache.


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P1 wants to load w2. This generates a cache missand P1s cache issues a BusRd bus transaction. The

S signal is not asserted, so the cache knows to load

w2 and w3 in the E state.

P1 P3


PrRd

BusRd(S)

P1 ld w2

P2

Ew2,w3

Main Memory


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P2 wants to load w0. This generates a cache missand P1s cache issues a BusRd bus transaction. The

S signal is not asserted, so the cache knows to load

w0 and w1 in the E state.

P1 P3


w2, w3 E

PrRd

BusRd(S)

P2 ld w0

P2

w0, w1 E

Main Memory


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P3 wants to store w1. This generates a cache miss.Memory will provide the data as no other cache has

this line in a modified state. After storing the new value

of w1, P3s cache issues a BusUpd. P2 snoops this

and updates its cache with the updated w1.

P1 P3


w2, w3 E

PrWr

BusRd(S)

P3 st w1

P2

E

BusUpd

w0, w1 Sm

Main Memory

Sc

Update

w0, w1


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P1 issues store w3. It has exclusive access to thiscache line. What bus transactions does P1s cache

issue?

P1 P3


w0, w1 Smw2, w3 E

P1 st w3

P2

w0, w1 Sc

PrRd

M

Main Memory


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P2 wants to load w3. This generates a cache miss. P2s cache issues aBusRd transaction. P1 asserts the S signal, so P2 will load the cache line

in Sc state. P1s cache has a modified version of the cache line, so it will

provide the data for P2 with a flush transaction. P1s cache will update the

lines state to Sm. Should P3 change w0/w1s state to M?

P1 P3


w0, w1 Smw2, w3 M

P2 ld w3

P2

w0, w1 Sc

PrRd

BusRd(S)

???

Main Memory

Sm

Flush

w2, w3


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P2 wants to load w2. P3 wants to store w0. What are thenecessary bus transactions and cache updates that need to

take place?

P1 P3


w0, w1 ?w2, w3 Sm

P2 ld w2

P3 st w0 P2

w2, w3 Sc

PrRd PrWr

Main Memory

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