Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA

Technology Mapping

Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA

Technology Mapping

Yu Hu1, Victor Shih2, Rupak Majumdar2 and Lei He1

1Electrical Engineering Dept., UCLA

2Computer Science Dept., UCLAPresented by Yu HuPresented by Yu Hu

Address comments to lhe@ee.ucla.eduAddress comments to lhe@ee.ucla.edu

OutlineOutline

Background and Motivations

Review of Standard SAT-based Boolean Matching

Proposed Improvements

Experimental Results

Conclusion and Future Work

BackgroundBackground

FPGA technology mapping Map a design into a network of Programmable

Logic Blocks (PLBs) Optimize for area, speed and/or power

PLB containing heterogeneous devices requires Boolean matching (BM) to determine whether function fcan be implemented by hardware component H

LUT4

AND2

PLB_aLUT4

PLB_b

LUT4

MUX2

LUT4

PLB_d

LUT4

LUT3

Example: Boolean Matching (BM) for PLBExample: Boolean Matching (BM) for PLB

Answer a Yes-No question Can a Boolean function f be implemented in PLB p? If yes, give the configuration bits of LUTs.

f1 = e*a + c*a + d*a + b*a

f2 = a + b + c + d + e

LUT4

AND2

x1

x2

x3

x4

x5f

PLB p

f1 = (e + c + d + b)*a

i.e.,

f1 = z*a

z = e + c + d + b

z

ec

db

a f1

L0 (0000) 0

L1 (0001) 1

L2 (0010) 1

…… …

L15(1111) 1

Motivation for SAT Based PLB BMMotivation for SAT Based PLB BM

Application of FPGA PLB Boolean matching Technology mapping Re-synthesis

Existing BM algorithms Decomposition based BM is lack of flexibility, i.e., algorithm is

only applicable to selected BLE structure [Cong, TCAD’01] BDD based BM is not scalable (memory explosion) [Ciric, TCAD’03] Fast BM is hard to deal with programmable devices [Wei, ISQED’06]

SAT based BM [Ling, DAC’05][Safarpour, DAC’06][Cong, FPGA’07]

Introduces extreme flexibility Provide a tradeoff between memory and runtime to deal with

complicated BLE structures Still slow, hard to be applied to complex PLBs

Review: SAT Based Encoding for BMReview: SAT Based Encoding for BM

Encoding non-programmable devices Requires common/interconnect variables Is a linear time procedure

Example:

x1x2 g

x3

z1

f AND= (x2+¬z1) (x1+¬z1) (¬x2+¬x1+ z1)

f OR= (¬x3+g) (¬z1+g) (x3+z1+ ¬g)

f total= fAND fOR

= (x2+¬z1) (x1+¬z1) (¬x2+¬x1+ z1) (¬x3+g) (¬z1+g) (x3+z1+ ¬g)

Review: SAT Based Encoding for BMReview: SAT Based Encoding for BM

Encoding programmable devices Configuration bits are encoded

f LUT= ( x1 + x2+ ¬L0 + z1) ( x1 + x2+ L0 + ¬ z1)

( x1 + ¬ x2+ ¬L1 + z1) ( x1 + ¬ x2+ L1 + ¬ z1)

(¬ x1 + x2+ ¬L2 + z1) (¬ x1 + x2+ L2 + ¬ z1)

(¬ x1 + ¬ x2+ ¬L3 + z1) (¬ x1 + ¬ x2+ L3 + ¬ z1)

L0

L3

L1 4-1 MUX

x1

z

LUT-2

00

11

01

L2 10

x2

LUT2 z

x1

x2

Review: SAT Based Encoding for BMReview: SAT Based Encoding for BM

G LUT2 =( x1 + x2+ ¬L0 + z) ( x1 + x2+ L0 + ¬ z)

( x1 + ¬ x2+ ¬L1 + z) ( x1 + ¬ x2+ L1 + ¬ z)

(¬ x1 + x2+ ¬L2 + z) (¬ x1 + x2+ L2 + ¬ z)

(¬ x1 + ¬ x2+ ¬L3 + z) (¬ x1 + ¬ x2+ L3 + ¬ z)

G AND2 = ( x3 + ¬f ) (¬ x3 + ¬f ) ( ¬x3 + ¬z + f )

G = G AND2 · G LUT2

x1x2x3 f

000 0

001 0

010 1

011 0

100 1

101 1

110 1

111 1

SAT:

G expand = G[X/000, f/0 , z/z0] · G[X/001, f/0, z/z1]

G[X/010, f/1 , z/z2] · G[X/011, f/0 , z/z3]

G[X/100, f/1 , z/z4] · G[X/101, f/1 , z/z5]

G[X/110, f/1 , z/z6] · G[X/111, f/1 , z/z7]

LUT2

AND2

x1

x2

x3f

z

Boolean function

The solution of this SAT problem

corresponds to the Boolean matching

results

Configuration bits are encoded as

SAT literals

Handle Input Permutation and BridgeHandle Input Permutation and Bridge

Virtual MUXes increase runtime

exponentially!

Impact of Virtual MUXesImpact of Virtual MUXes

0

2000

4000

6000

8000

10000

12000

5 6 7 8 9

input#

SA

T V

aria

ble

#

V-MUX w /o V-MUX

0

20000

40000

60000

80000

100000

120000

5 6 7 8 9

input#

Cla

use

#

V-MUX w /o V-MUX

0.001

0.01

0.1

1

10

100

1000

5 6 7 8 9

input#

Ru

nti

me

(s

)

V-MUX w/o V-MUX

LUT4

PLB_d

LUT4

LUT3

Symmetries in Circuits and PLBSymmetries in Circuits and PLB

Functional Symmetries Variable a and variable b are symmetric if swapping a and b

does not change the truth table of function F(…,a,…,b,…) General symmetries which consider the permutation of more

than two variables can also be explored Eg: F(a,b,c) = a(b+c), where b and c are symmetric

Architectural Symmetries Structures of certain inputs of a PLB are equivalent Eg: Inputs of the primary input LUTs of each PLB are symmetric

F(a, b, c, d)F(b, a, c, d)

Impact of Considering SymmetriesImpact of Considering Symmetries

The number of distinct permutations under symmetries decreases substantially Functional symmetries and architecture symmetries

independently reduce 100x permutations

Number of distinct permutations (for 9-input Boolean functions, 9!=362880)

1

10

100

1000

10000

100000

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

Test case

Nu

mb

er o

f d

isti

nct

per

mu

tati

on

s

Per#F_symm Per#Arch_symm

Overall AlgorithmOverall Algorithm

Target architecture

Pre-calculate architecture symmetries patterns

Architecture symmetry

information

Characteristic function template

Generate characteristic function template

Boolean function

Functional symmetry detection

Pruning by architecture symmetries

Non-redundant permutation set (NPS)

Is NPs empty?

Pre-process for the target PLB, one-time cost ExitPop a permutation p

YN

Overall Algorithm (cont.)Overall Algorithm (cont.)

Replicate CNFs of p

Solve the SAT problem

SAT?

Return implementable

Target architecture

Pre-calculate architecture symmetries patterns

Architecture symmetry

information

Characteristic function template

Generate characteristic function template

Pre-process for the target PLB, one-time cost Exit

Y

Is NPs empty?

Pop a permutation p

YN

N

Experimental ResultsExperimental Results

Experimental settings Tested by Boolean functions in MCNC circuits Target PLB is “PLB_d” Use “minSAT1.14” to solve SAT instances

Obtain over 100x speedup compared to the standard approach [Ling’05]

LUT4

PLB_d

LUT4

LUT3

0.001

0.01

0.1

1

10

100

1000

5 6 7 8 9

Number of inputs of Boolean function

Ru

nti

me

(s)

Ling'05 Ours Ours+Cong'07

Effectiveness of considering symmetries and implicant table

0.1

1

10

100

1000

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

Test case

Ru

nti

me

(s

)

SAT-BM F_symm_SAT-IP Arch_symm_SAT-IP SAT-IP

Breakdown of speedup techniques

Conclusions and Future WorkConclusions and Future Work

An improvement for SAT-based Boolean matching is presented by considering functional and architectural symmetries

Over 100x speedup is obtained compared to the standard SAT-based Boolean matching approach

Future Work Integrate the improved SAT-based Boolean matcher into

heterogeneous FPGA technology mapping phase Perform architecture exploration by our improved technology

mapper

Thank You!Thank You!

Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous

FPGA Technology MappingYu Hu, Victor Shih, Rupak Majumdar and Lei He