Experimental results obtained from a 1.6 GHz CMOS Quadrature Output PLL with on-chip DC-DC Converter

Owen CashaDepartment of Micro & Nanoelectronics

University of Malta

Co-authors: Ivan Grech, Edward Gatt, Joseph Micallef

17th IEEE International Conferenceon Electronics, Circuits, and Systems

ICECS 2010

2

Overview

Introduction

Quadrature PLL Architecture

Linear Regulated DC-DC Converter

Chip Layout Design Considerations

Chip Measurements / Characterisation

Conclusions

Acknowledgements

3

Introduction The compliance of RF circuits with the emerging communication

standards depends a lot on how the local oscillator performs in terms of phase noise, power consumption, tuning range and adaptivity to the transmission environment.

An on-chip DC-DC converter is not commonly used in a RFIC due to the possibility of interference with the RF function.

Nonetheless in this work, an on-chip DC-DC converter is employed to permit the use of low sensitivity varactors in conjunction with a switched capacitor bank to achieve the required tuning range.

Measured results – confirm that a proper regulatory scheme for the DC-DC converter limits the output voltage ripple.

Automatic Amplitude Control – VCO Adaptivity (Phase Noise versus Power Consumption)

4

Quadrature PLL Architecture

Level Shifters PFD CP

Prescalar÷ 16

LFVtune

Quadrature Outputs

DC-DC Converter

Reference Oscillator100 MHz

Vddhigh

B2-B0Tuning

Band Selection

Buffered QO-VCO

AmplitudeReference Signal

Linear Regulator

~ Level Shifters PFD CP

Prescalar÷ 16

LFVtune

Quadrature Outputs

DC-DC Converter

Reference Oscillator100 MHz

Vddhigh

B2-B0Tuning

Band Selection

Buffered QO-VCO

AmplitudeReference Signal

Linear Regulator

~

1.6 GHz QPLL Chip2 mm x 2 mmST 130 nm HCMOS9-RF

Prototype testing board designed for

the QPLL chip

5

Linear Regulated DC-DC Converter

Ensures stability

Derivative Feedback Level shifting

Proportional Controller

Switched Capacitor Converter

100 MHz 200 MHz ripple frequency

6

Chip Layout Design Considerations

The design of the QO-VCO, PFD, charge pump and prescalar was carried out with a high degree of symmetry, where the interconnections were kept as short as possible and utilised mostly top metal layers which have a low associated sheet resistance and capacitance.

The DC-to-DC converter was placed as far as possible from the QO-VCO to limit the interference between the two circuits through the substrate. The DC-to-DC converter was surrounded with a wide guard ring to limit the radiation generated by this switching circuit.

Differential inductors were used to maintain the symmetry of the QO-VCO. The inductors were placed at a distance of about 100 μm apart from each other to reduce magnetic coupling between them which affects the quadrature lock of the oscillator.

Layout of the 1.6 GHz QPLL Chip2 mm x 2 mm

ST 130 nm HCMOS9-RF

7

QO-VCO Measurements (I)

QO-VCO Tuning Characteristics

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

0 0.5 1 1.5 2 2.5

Varactor Tuning Voltage (Volts)

Osc

illa

tion

Fre

quen

cy (G

Hz)

BS 0 BS 1 BS 2 BS 3

BS 4 BS 5 BS 6 BS 7

The QO-VCO can be continuously tuned from 1.18 GHz to 1.75 GHz, thus a tuning range of 570 MHz (38%) is available. The different curves refer to the different tuning band settings obtained by switchable capacitors.

8

QO-VCO Measurements (II)

IMR Measurement for QO-VCO at 1.6 GHz

Measured QO-VCO buffered outputsignals at 1.58 GHz

Quadrature Phase Error3.56°

Amplitude Mismatch5.28%

9

Phase Noise Response (I)

-120

-119

-118

-117

-116

-115

-114

0 0.5 1 1.5 2 2.5

Varactor Tuning Voltage (Volts)

Phas

e N

oise

@ 1

MH

z O

ffse

t (dB

c/H

z)

BS 0 BS 1

BS 2 BS 3

BS 4 BS 5

BS 6 BS 7

Variation of the QO-VCO phase noise across tuning range

10

Phase Noise Response (II)

-125-120-115-110-105-100-95-90-85-80-75-70-65

10 100 1000 10000

Offset Frequency (kHz)

Phas

e N

oise

(dBc/

Hz)

1/f2 region

1/f3 region acceptable phase noise limitfor GPS applications [7]

Phase noise response of the (○) open loop QO-VCO and the (●) quadrature PLL at operated at 1.6 GHz.

11

QO-VCO Automatic Amplitude Control

-120-115-110-105-100-95-90-85-80

0.2 0.4 0.6 0.8 1

AAC Reference Voltage (Volts)

Phas

e N

oise

@ 1

MH

z off

set (

dBc/

Hz)

FB 3 Vtune = 1.2VFB 0 Vtune = 0.6VFB 7 Vtune = 1.6V

1.55

1.555

1.56

1.565

1.57

1.575

1.58

1.585

0.2 0.4 0.6 0.8 1

AAC Reference Voltage (Volts)

Fre

quen

cy (G

Hz)

0

0.2

0.4

0.6

0.8

1

1.2

Kvf x

109 (r

ad/s

/V)

Variation of the phase noise response at an offset of 1 MHz with AAC reference voltage

Variation of the oscillation frequency (●) and Kvf (○) with AAC reference voltage

refvf dV

dK

12

QO-VCO Performance Summary

Measurement

QO-VCO Tuning Range

570 MHz38%

Phase Noise @ an offset of 1 MHz from carrier across whole

tuning range

< ‒115 dBc/Hz

QO-VCO Power Consumption

(including AAC circuitry and buffers)

20.4 mW @ 1.6 GHzVtune = 0.75 VB2B1B0 = “001”

IMR ‒ 28 dB @ 1.58 GHz

Quadrature Phase Imbalance

3.56º

Amplitude Imbalance 5.28%

14

16

18

20

22

24

26

28

0.2 0.4 0.6 0.8 1AAC Reference Voltage (Volts)

Curr

ent D

eman

d (m

A) FB3 Vtune = 1.2V

FB0 Vtune = 0.6VFB7 Vtune = 1.6V

Variation of the QO-VCO current demand (including buffers and AAC circuitry) with the AAC reference voltage.

The higher the AAC reference voltage the lower the VCO oscillation amplitude.

13

DC-DC Converter

The on-chip DC-DC converter provides a constant 2.5 V output voltage:

Full Load Efficiency of 53%. 2 mV output ripple voltage up to a load current

of 200 μA. Consumes only 4.6% of the total PLL power

demand at the optimum phase noise response. The regulatory scheme aids in reducing the

degradation of the PLL spurious tone level due to the DC-DC converter.

14

Effect of DC-DC Converter on Spur Tone Level

Frequency synthesizer output spectrum with on-chip DC-DC converter, PFD and CP switched off, QO-VCO in open loop mode and reference clock oscillator disabled.

15

Effect of DC-DC Converter on Spur Tone Level

Frequency synthesizer output spectra with:

(a) off chip 2.5 V linear voltage regulator and (b) on chip DC-DC converter

supplying the CP and PFD

(a)

(b)

Results confirm the negligibleeffect of the DC-DC converter onthe spur tone level of the QPLL

16

Effect of DC-DC Converter on Spur Tone Level

Frequency synthesizer output spectrum with on-chip DC-DC converter, PFD and CP switched off, QO-VCO in open loop mode and reference clock oscillator switched on

This test indicates that the spur at 100 MHz is possibly arising due to the chip substrate and testing board electromagnetic coupling and not due to CP injection.

17

Conclusions

This paper presented the measured results and characterisation of a 1.6 GHz low voltage CMOS quadrature output PLL chip designed for a GPS tuner application.

Measurement results show that it exhibits a phase noise of less than 115 dBc/Hz at an offset of 1 MHz from carrier and has a tuning range of 570 MHz.

Negligible effect of the on-chip linear regulated DC-DC converter on the spurious tone level of the PLL, included in order to provide a high tuning voltage swing whilst using low sensitivity MOS varactors.

18

Acknowledgements

The work presented in this paper has been supported by the Telecommunication Peripherals and Automotive Groups at STMicroelectronics, Catania, Italy.

Special thanks go to

Mr. Mario Paparo Mr. Salvatore Cantella

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Thank you for your attention

Any Questions?

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Switched Capacitor Voltage Tripler

Two identical switchedcapacitor converters combined in parallel and operated with complementary reference clock signals via a dead band generator.

Effective output frequency is 200 MHz – low voltage ripple and facilitated filtering.