exercise 2: transfer characteristics of gates - lab- · pdf file118 facet by lab-volt open...

Student Manual

118 FACET by Lab-Volt

Open Collector and Other TTL Gates Digital Logic Fundamentals

Exercise 2: Transfer Characteristics of Gates

EXERCISE OBJECTIVE

When you have completed this exercise, you will be able to demonstrate the effects of an input signal

voltage level on the output logic state of a Schmitt-trigger LS inverter and a standard LS inverter by using

the OPEN COLLECTOR circuit block. You will verify your results by comparing the output waveforms of

each type of inverter.

DISCUSSION

A standard gate is designed with an input circuit that responds best to input signals with fast rise and fall

times.

Slow rate of change input voltages or noise may cause a standard gate to generate false output logic

levels (levels between a high state and a low state).

output to change state.

Slow rate of change and noisy input signals are typically buffered with Schmitt-trigger input gates.

What type of gates have internal positive feedback that enables the outputs to change state only at

a. standard gates

b. Schmitt-trigger gates

A typical transfer characteristic curve (output versus input) for a standard LS transistor-transistor inverter

is shown here.

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FACET by Lab-Volt 119

Digital Logic Fundamentals Open Collector and Other TTL Gates

The input voltage low (VIL) is 0.8 Vdc and the input voltage high (VIH) is 2.0 Vdc.

However, the output for this typical inverter changes state at an input voltage between 0.8 Vdc and 1.1

Vdc.

There is not a very sharp change in the output state.

Each inverter in this class might change state in a narrow voltage range between the VIL of 0.8 Vdc and

VIH of 2.0 Vdc.

As a result, slow rate of change or noisy input signals can cause a false output state.

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If noise causes the input signal to increase from 0 Vdc to 1.4 Vdc and then decrease to 0 Vdc for a

standard inverter with a transfer characteristic curve as shown, the output logic state would go from

a. low to high to low.

b. low to high and stay high.

c. high to low to high.

The transfer characteristic curve for a typical Schmitt-trigger inverter is shown.

The Schmitt-trigger output changes state only at the threshold points, VT+ and VT-.

VT+ is the positive-going (input increasing) threshold voltage. VT- is the negative-going (input decreasing)

threshold voltage.

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For the Schmitt-trigger inverter, the output does not change from high to low until the input increases to a

VT+ of about 1.6 Vdc.

When the input voltage decreases, the output will stay low until the input decreases to a VT- of about 0.8

Vdc.

Because the gate changes state only at VT+ and VT- and the output transition between low and high is

sharp, the Schmitt-trigger gate is used when the input signal is noisy and/or has slow rise and fall times.

As shown, the Schmitt-trigger inverter outputs a sharp digital pulse when the input is an analog signal with

a slow rise and fall time or contains noise.

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The output of the inverter goes low at VT+.

Only when the input decreases to VT- does the output go high again.

When the input falls slightly below VT+ or goes slightly above VT-, there is no change in the output state.

If the input signal increased from 0 Vdc to 2.0 Vdc and then decreased to 1.2 Vdc for a Schmitt-trigger

inverter with a transfer characteristic curve as shown, the output logic state would go from

a. low to high to low.

b. high to low and stay low.

c. high to low to high.

Student Manual



PROCEDURE

Locate the OPEN COLLECTOR circuit block and the TTL/CMOS COMPARISON circuit

block.

Connect the voltmeter to the output of the positive variable supply on the TTL/CMOS

COMPARISON circuit block. Set the positive variable supply to 0 Vdc.

Connect the positive variable supply to input A at the SCHMITT inverter, as shown.

Connect the voltmeter to input A.

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Connect the oscilloscope channel 1 probe to the output of the SCHMITT inverter, and connect

the probe ground clip to ground as shown in the image below.

Slowly increase the positive variable supply until the SCHMITT inverter output changes state

from high to low. At what voltage (VT+) did the SCHMITT inverter change state?

VT+ = Vdc (Recall Value 1)

Increase the positive variable supply to about 3 Vdc at input A.

Slowly decrease the positive variable supply until the SCHMITT inverter output changes state

from low to high. At what voltage (VT-) did the SCHMITT inverter change state?

VT- = Vdc (Recall Value 2)

By changing the positive supply, vary the input voltage at A between the measured values of

VT- ( Vdc [Step 6, Recall Value 2]) and VT+ ( Vdc [Step 5, Recall Value 1]).

Does the output of the SCHMITT inverter change states between VT- and VT+?

a. yes

b. no

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Based on your measurements, does the SCHMITT inverter lock out input voltages between

VT- and VT+?

a. yes

b. no

Connect the positive variable supply to input B at the STANDARD inverter as shown.

Connect the voltmeter to input B.

Set the input voltage at B to 0 Vdc.

Connect the oscilloscope channel 1 probe to the STANDARD inverter output (as shown in the

image below).

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Slowly increase the positive variable supply until the output of the STANDARD inverter,

which is shown on oscilloscope channel 1, stops decreasing (reaches logic 0).

At what input voltage did the output reach logic 0?

V = Vdc (Recall Value 3)

Increase the input voltage at B to about 3 Vdc. Then slowly decrease the positive variable

supply until the output of the STANDARD inverter, which is shown on oscilloscope channel

1, just starts to increase beyond 2.0 Vdc (2.4 VMAX).

At what input voltage did the output start to increase beyond 2.0 Vdc?

V = Vdc (Recall Value 4)

Slowly vary the input voltage above and below the measured input voltages of ( Vdc

[Step 10, Recall Value 3]) and ( Vdc [Step 11, Recall Value 4]).

Does the output of the STANDARD inverter change states between these voltages?

a. no

b. yes

Does the output of a STANDARD inverter change state in a voltage range between the

IL (0.8 Vdc) and VIH (2.0 Vdc)?

a. yes

b. no

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Connect the output of the CLOCK circuit block to inputs A and B at the OPEN COLLECTOR

circuit block, as shown.

During this part of the procedure, passive RC networks in the OPEN COLLECTOR circuit

block convert the clock signal waveform at A and B into a slow rise and fall waveform at A

and B, as shown.

Connect the oscilloscope channel 2 probe to the SCHMITT inverter output, and connect the

channel 1 probe to the STANDARD inverter output (as shown in the image below).

Compare the outputs of the SCHMITT and STANDARD inverters.

Student Manual



Which gate generates the cleaner output transitions?

a. the SCHMITT inverter

b. the STANDARD inverter

CONCLUSION

• IL

and VIH.

• T+ and VT-; input signals

between VT+ and VT- are locked out.

• A Schmitt-trigger gate transforms analog input waveforms into square digital output waveforms.

REVIEW QUESTIONS

1. A standard TTL inverter output changes state at an input voltage

a. equal to VIL.

b. equal to VT+.

c. equal to VIH.

d. greater than VIL and less than VIH.

2. When the input voltage increases from 0 Vdc, a Schmitt-trigger TTL inverter output changes state at

an input voltage

a. equal to VT–.

b. equal to VT+.

c. between VT– and VT+.

d. less than VT+.

3. A standard TTL inverter is used when the input signal

a. contains noise.

b.

c. has fast transitions between states.

d. has slow transitions between states.

4. A Schmitt-trigger TTL inverter is used when the input signal

a. contains noise.

b. has slow transitions between states.

c. waveform is analog that has to be converted to a digital pulse signal.

d. All of the above.

5. A Schmitt-trigger TTL inverter has a VT– of 0.8 Vdc and a VT+ of 1.6 Vdc. The input signal increases

from 0 Vdc to 1.2 Vdc and then decreases to 0 Vdc. The output will

a. change from high to low to high.

b. stay low.

c. stay high.

d. change from high to low.

exercise 2: transfer characteristics of gates - lab- · pdf file118 facet by lab-volt open...

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