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1 E E valuation valuation Test Test R R esult esult s s of of A A ntifuse ntifuse T T ype FPGA ype FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

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Page 1: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

1

EEvaluation valuation TestTest RResultesultss of of AAntifuse ntifuse TType FPGAype FPGA

2005.10.28Noriko YAMADA

Electronic, Mechanical Components and MaterialsEngineering Group

Page 2: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

2

BackgroundBackgroundIn the U.S., the failures of antifuse type FPGA (RTSX-S and SX-A) produced with MEC die (MEC device) have been reported from the beginning of 2003.An Industry Tiger Team (ITT) and NASA have made investigations and evaluation tests to find out the cause of the failures (ongoing).From the evaluation test results, the failure phenomenon is considered to be the increase in the delay time by the increase in resistance of an antifuse.The antifuse degradation is attributed to the problem of the structure of the MEC devices , and the manufacture recommends change to the UMC devices which are compatible with the MEC devices.In order to evaluate the risk of the MEC devices already mounted in the PWB and to determine the management plan for every project, the evaluation test was carried out by JAXA.

Page 3: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

3

APPENDIX(1): APPENDIX(1): AntifuseAntifuse (MEC)(MEC)

W-Plug

a:Si

Al

Ti

Ti

Before programming

unprogrammedunprogrammed AntifuseAntifuse

After programming

Programmed Programmed AntifuseAntifuse

“Reliability of Antifuse-Based Field Programmable Gate Arrays for Military and Aerospace Applications,” MAPLD 2001

Page 4: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

4

IntroductionIntroduction

Risk assessment of MEC die DevicesTo determine the acceleration factors and the failure rates about antifuse failures.Long-term life tests and thermal shock tests are carried out .

Reliability evaluation of UMC die DevicesThe UMC device has just received QML authorization in October, 2004, and UMC does not have experience used in the space. To evaluate the reliability for space applications by performing long-term life tests and radiation tests.

Page 5: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

5

Test SamplesTest Samples

Original(ver. 4.48)UMC die110Actel Corp.RTSX32SU-

CQ256E

Old(ver. 4.42)MEC die320Actel Corp.A54SX72A-

CQ256M

Old(ver. 4.42)MEC die190Actel Corp.A54SX32A-

CQ256M

ProgramAlgorithmRemarkSample

SizeManufacturerPartNumber

Page 6: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

6

Test Vehicle (1)Test Vehicle (1)

4-input AND-OR chains : Maximum utilization of antifusesStable operation using an external clock circuit:Easier failure detectionR-cells driven by skewed clock: Delays detectable to less than 10nsecContinuous monitoring of XORed outputs from the same circuit block: Real-time detection of failures

x4:32A32SU

x8:72A

Block UnitBlock Unit

Page 7: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

7

RTSX32SU

RT54SX32S

RT54SX32S

A54SX72A

A54SX32ARTSX32SU

Part No.

12102

13012

13015

3654536545

1790617906

Dynamic fuse Count (Total)

-

-

-

8

4

Circuit BlockCount

15102151022144321443

46967406NASA

51787834General Test

51977818Colonel Test

7931793199759975JAXAJAXA

High CurrentFuse Count

(F,X,G,V,H,W)

Low Current Fuse Count

(I,S,K,B)

Designtype

Test Vehicle (2)Test Vehicle (2)The number of antifuses in test vehicles

Page 8: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

8

5--Total Ionizing Dose (TID)5--Single Event Effect (SEL/SEU)

Radiation Test

907745-65 to +150deg.C,1000 cyclesThermal Shock Test-774525 deg.C, 33MHz, 1000H

1007745125 deg.C, 1MHz, 1000H-774570 deg.C, 1MHz, 1000H-774525 deg.C, 1MHz, 1000H

Long-term Life Test

RTRTSX32SUSX32SU

A54A54SX72ASX72A

A54A54SX32ASX32A

Sample SizeSample SizeConditionConditionTest ItemTest Item

Test Items and ConditionsTest Items and Conditions

Page 9: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

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Test EnvironmentTest Environment

Handling EnvironmentHandling EnvironmentESD protected / designated areaESD protected / designated area

-- Vacuum wandsVacuum wands-- Globes requiredGlobes required-- Wrist strapWrist strap-- ESD shoesESD shoes

-- ESD safe table matsESD safe table mats-- Ionizer (ATE area)Ionizer (ATE area)-- Antistatic floor Antistatic floor etc. etc.

Test SystemsTest SystemsPrevention of EOSPrevention of EOS

-- Signals and power supplies within Signals and power supplies within recommended operating conditions recommended operating conditions described in datasheetdescribed in datasheet

(ex. Power strip with noise filter)(ex. Power strip with noise filter)

Page 10: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

10

Test Results (Test Results (11): ): Weibull PlotsWeibull Plots72A Weibull Plot

y(125C) = 0.0954Ln(x) - 2.6000y(70C) = 0.1002Ln(x) - 2.7259y(25C) = 0.1118Ln(x) - 2.8132

-5

-4

-3

-2

-1

1 10 100 1000 10000Time [Hour]

ln(-l

n(1-

F))

125C70C25C

Comparison of Weibull Plot

y(72A, 25C) = 0.1118Ln(x) - 2.8132

y(32A, 25C) = 0.0518Ln(x) - 3.2763

-5

-4

-3

-2

-1

1 10 100 1000 10000Time [Hour]

ln(-l

n(1-

F))

25C(72A)25C(32A)

Weibull ParametersWeibull Parameters

6.528E+110.1002

70℃

6.857E+118.473E+10η

0.09540.1118β

125℃25℃

2.942E+27η

0.0518β

32AWeibull parameter (beta< 1) Infant mortality as the result in the U.S.

Page 11: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

11

Comparison of Failure Rate

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+8

1 10 100 1000 10000 100000Time [Hour]

Failu

re R

ate

[Fit(

32A

Equ

ival

ent)] 25C(72A)

25C(32A)

Failure Rate for 72A

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+8

1 10 100 1000 10000 100000Time [Hour]

Failu

re R

ate

[Fit(

32A

Equ

ival

ent)] 25C

70C125C

Test Results (Test Results (22): Failure Rate): Failure Rate

The temperature dependence of the failure rates is very small.

Since the structure of 32A and 72A is the same, the difference in the failure rates between 32A and 72A is considered to be lot dependence.

90% Confidence Interval (Upper-Lower)

90% Confidence Interval (Upper-Lower)

Page 12: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

12

Acceleration Factor (Ea=0.002eV)

y = 0.9567e-0.0218x

1E-1

1E+0

2 2.5 3 3.51000/T [1000/K]

Slop

e of

λ(t)

Test Results Test Results (3)(3): : Activation EnergyActivation Energy

Ea=0.002eV

The activation energy (Ea) was calculated based on the Weibull plot of 72A sample.

Ea=0.002eV → PPBI (125 deg.C, 240 hours) is almost ineffective in screening for the antifuse delay failures.

Page 13: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

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Test Results Test Results (4):(4): UMCUMC

Long-term Life Test (1MHz・125℃・ 1000H)

→ No Failure

The failure by antifuse delay which was detected by the MEC device did not take place.

The failure by ESD was not observed.*

* In the evaluation in the U.S, the failure by ESD had occurred and it became clear that the electrostatic tolerance of 32SU is extremely low.

Page 14: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

14

Antifuse Delay Time DistributionAntifuse Delay Time DistributionSX72A, 25 deg. C, 1000H

0

1

2

3

4

5

6

7

8

1.0 10.0 100.0 1000.0 10000.log10(Delta tPD) [ns]

Occ

uren

ce

experimentnormal

SX72A, 125 deg. C, 1000H

0

1

2

3

4

5

1 10 100 1000 10000log10(Delta tPD [ns])

Occ

uren

ce

experimentnormal

SX72A, 125 deg. C, 1000H

0

1

2

3

4

5

1 10 100 1000 10000log10(Delta tPD [ns])

Occ

uren

ce

experimentnormal

SX72A, 70 deg. C, 1000H

0

1

2

3

4

5

6

7

1 10 100 1000 10000log10(Delta TPD [ns])

Occ

uren

ce

measuredexperiment

SX72A, 70 deg. C, 1000H

0

1

2

3

4

5

6

7

1 10 100 1000 10000log10(Delta TPD [ns])

Occ

uren

ce

measuredexperiment

SX72A, 70 deg. C, 1000H

0

1

2

3

4

5

6

7

1 10 100 1000 10000log10(Delta TPD [ns])

Occ

uren

ce

measuredexperiment

SX72A, 70 deg. C, 1000H

0

1

2

3

4

5

6

7

1 10 100 1000 10000log10(Delta TPD [ns])

Occ

uren

ce

experimentnormal

SX72A, 70 deg. C, 1000H

0

1

2

3

4

5

6

7

1 10 100 1000 10000log10(Delta TPD [ns])

Occ

uren

ce

measuredexperiment

SX72A, 70 deg. C, 1000H

0

1

2

3

4

5

6

7

1 10 100 1000 10000log10(Delta TPD [ns])

Occ

uren

ce

experimentnormal

The delta is well fitted to the log-normal distribution.

Page 15: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

15

Voltage Voltage AAccelerationcceleration FactorFactor72A Weibull Plot (Accelerated)

y(2.5V) = 0.1118Ln(x) - 2.8132

y (3.0V,a.f.=50)= 0.1079Ln(x) - 2.7912 R2 = 0.9867

-5

-4

-3

-2

-1

1 10 100 1000 10000 100000Time [Hour]

ln(-l

n(1-

F))

2.5V3.0V(a.f.=50)

Long-term life test was carried out on 72A at 3.0V following 1000H life test at 2.5V (@1MHz・25℃).

2.5V => 3.0V An acceleration factor is about 50 times.

Page 16: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

16

Frequency Frequency DDependabilityependability ((11)): : 32A32A

Comparison of Fairure Rate for 32A

1E+0

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+8

1 10 100 1000 10000 100000Time [Hour]

Failu

re R

ate

[Fit(

32A

Equ

ival

ent)] 1MHz

33MHz

33MHz ⇔ 1MHzA failure rate is mostly the same and the frequency dependenceis not observed.

The thermal migration model which a manufacturer advocates cannot explain the results.

Page 17: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

17

Frequency Frequency DDependabilityependability ((22):): 72A72A

In order to avoid the influence of noise when testing at 33MHz, power supply voltage was set up 0.1V lower than when testing at 1MHz. the failure rate at 33MHz is low.

The voltage accelerationfactor calculated from page14 was about 3(0.1V). This is almost the same as that of estimated from this graph. No frequency dependability

Comparison of Fairure Rate for 72A

1E+0

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+8

1 10 100 1000 10000 100000Time [Hour]

Failu

re R

ate

[Fit(

32A

Equ

ival

ent)] 1MHz

33MHz

Page 18: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

18

0.50

0.60

0.70

0.80

0.90

1.00

1.10

0 20,000 40,000 60,000 80,000 100,000Mission Duration (hours)

Pro

babi

lity

of N

o Fa

ilure

3years1year 5years 10years

85300FIT

25500FIT14500FIT

6700FIT

Survival ProbabilitySurvival Probability :: 72A72A

The survival probability over the mission time was calculated using the Weibull parameters and activation energy at the operating temperature of 40 degrees C after PPBI

FIT of 72A is large compared with general LSI for the space.

Page 19: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

19

1.0E-10

1.0E-09

1.0E-08

1.0E-07

0.1 1 10 100Frequency [MHz]

Cro

ss S

ectio

n [c

m2 /b

it]

Dyanmic(CKB pattern)Dyanmic(All 1)

Radiation Test Results (1)Radiation Test Results (1):: SEESEE

FrequencyFrequencydependencedependence

SEU(Single Event Upset) / SEL(Single Event Latch-up)- Japan Atomic Energy Agency(JAEA)TIARA* AVF CYCLOTRON- Xe (LET=64[MeV/mg/cm2])

SEL was not observed

SEU was not observed in the static state .

SEU were observed in the dynamic state, andshowed frequency dependence ( right figure).

•TIARA* (Takasaki Ion Accelerators for Advanced Radiation Application)

Page 20: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

20

Radiation Test Results Radiation Test Results (2)(2):: TIDTID

S/N 58607

0.000

0.050

0.100

0.150

0.200

0.250

0.300

0.350

0.400

0 100 200 300 400 500 600 700 800 900 1000Total Dos e [G y (Si)]

Icc

[A]

Ic c aIc c i

Manufacturer’s result JAXA result

The increase in power supply current was observed.Sharp increase of Icca at 600Gy(Si) Recovered to the initial value and the equivalent level after

annealing (100 degrees C with 168H)

Page 21: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

21

Thermal Shock Test ResultsThermal Shock Test Results

Thermal Shock Test

Conditions: -65℃~150℃

Test period: 1000 cycles

Test samples: MEC: 32A・72A, UMC: 32SU

No Failure was observed

Page 22: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

22

Summary Summary (1)(1)MEC:

Delays caused by anti-fuse degradation were observed and considered to be similar phenomena observed in evaluation conducted by ITT and NASA. The failure rates of MEC are large, compared with general LSI for the space.The temperature acceleration of the failure rates was too small to screen out the defective antifuses throughout PPBI (125deg.C 240hours)The frequency dependence of the failure rates was not observed. It is new findings that the degradation mechanism is not explained by thermal migration which manufacturer advocates.The degradation of antifuse is accelerated by supply voltage: accelerated about 50 times for 2.5V to 3.0V of Vcc.The delta tPD showed a stable behavior after failure.The failure rates have varied from lot to lot.

Page 23: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

23

Summary Summary (2)(2)UMC:

The failure by antifuse delay which was detected in the MEC device did not take place.The failure by ESD was not observed.SEL was not observed.SEU was not observed in static state but also in dynamic state, and showed frequency dependence:Xe (LET=64[MeV/mg/cm2]).The increase in power supply current was observed during TID testing. The trend is similar to the manufacturer’s data.

Thermal Shock TestingNo failure was observed.

Based on the test results, JAXA has decided to replace the Based on the test results, JAXA has decided to replace the MEC with UMC.MEC with UMC.

Page 24: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

24

APPENDIX(2)APPENDIX(2)--1: Test Data1: Test Data

631 631 631 631 631

Units

76 69 63 52 40

Failures

-2.26 0.1000 100

0.1206 0.1095

0.0826 0.0635

cumulative failure rateF(t) lnln(1/(1-F(t)))Test point

(hours)

-2.16 338-2.06 1011

-2.46 29-2.73 2

72A 25℃ 1MHz72A 25℃ 1MHz

-2.67 0.0673 652 44 2

652 652 652 652 652

Units

76 67 62 55 46

Failures

-2.31 0.0950 36

0.1206 0.1026

0.0842 0.0704

cumulative failure rateF(t) lnln(1/(1-F(t)))Test point

(hours)

-2.23 110-2.06 303

-2.44 16-2.63 4

72A 70℃ 1MHz72A 70℃ 1MHz

Page 25: Evaluation Test Results of Antifuse Type FPGAEvaluation Test Results of Antifuse Type FPGA 2005.10.28 Noriko YAMADA Electronic, Mechanical Components and Materials Engineering Group

25

-2.30 0.0963 655 63 15-2.17 0.1085 655 71 40

655 655 655

655 655

Units

82 80 75

50 49

Failures

-2.11 0.1146 110

0.1253 0.1222

0.0764 0.0749

cumulative failure rateF(t) lnln(1/(1-F(t)))Test point

(hours)

-2.04 303-2.02 1067

-2.54 4-2.56 2

-2.88 0.0564 182 10 804 -2.88 0.0564 182101002

-3.11 0.0454 182 8 96 182

182

Units

9

7

Failures

0.0509

0.0399

cumulative failure rateF(t) lnln(1/(1-F(t)))Test point

(hours)

-2.99 522

-3.25 1

72A 125℃ 1MHz72A 125℃ 1MHz

32A 25℃ 1MHz32A 25℃ 1MHz

APPENDIX(2)APPENDIX(2)--2: Test Data2: Test Data