evaluation of the multi-core technology for demanding space … · memory management mmu for each...

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ESA Workshop on Avionics Data, Control and Software Systems

(ADCSS)

Multi-Core Processors for Space Applications

(MCPSA)

25-27 October 2011, ESTEC

Evaluation of the Multi-Core Technology for

Demanding Space Applications

P. Behr, I. Haulsen, S. Pletner, R. van Kampenhout

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target technology evaluation

requirement definition

specification of system architecture (incl. FDIR)

software architecture and algorithms

hardware implementation and system integration

setup of demonstration and evaluation scenario

system evaluation

target technology evaluation

requirement definition

specification of system architecture (incl. FDIR)

software architecture and algorithms

hardware implementation and system integration

setup of demonstration and evaluation scenario

system evaluation

ADCSS 2011 MUSE Project

MUSE – Evaluation of the MULti-Core Architecture

for tracking SEnsor in Space

Objectives of the project:

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ADCSS 2011 Target Technology

Criteria for Processor Selection:

PowerPC Multi-Core Processor QorIQ P4080

embedded design (SoC)

performance (on-chip interconnect, FPU)

memory interface

I/O interfaces (standard, high speed)

SOI technology

power dissipation (mW/MIPS)

power save functions

availability (long term, ITAR free)

multi-core (8-16 cores)

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Frame Manager

Parse, Classify,Distribute

Buffer

RapidIOMessageUnit (RMU)

2x DMA

PCIe

18-Lane 5 GHz SerDes

PCIe sRIOPCIe

CoreNet™

1024 KBFrontsideL3 Cache

64-bitDDR-2 / 3

Memory Controller> 30W max @ 1.5GHz

SRIO

WatchpointCross

Trigger

PerfMonitor

CoreNetTrace

Aurora

Security4.0

PatternMatchEngine

Queue Mgr.

BufferMgr.

eLBC

TestPort/SAP

1GE 1GE

1GE 1GE10GE

1024 KBFrontsideL3 Cache

64-bitDDR-2 / 3

Memory Controller

PAMUCoherency Fabric

PAMUPAMUPAMU PAMUPeripheral Access Mgmt Unit

eOpenPIC

Power Mgmt

2x USB 2.0/ULPI

SD/MMC

Clocks/Reset

2x DUART4x I 2C

SPI

GPIO

PreBoot LoaderSecurity Monitor

Internal BootROM

CCSR

Power Architecture™e500-mc 1.5GHz Core

D-Cache I-Cache

128 KBBacksideL2 Cache 32 KB 32 KB

Frame Manager

Parse, Classify,Distribute

Buffer

1GE 1GE

1GE 1GE10GE

Block diagram of P4080

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Technology 8 core multi-core processor, 45nm SOI processclock frequency 1,5 GHz, 1295-pin FBGA

Cache1st Level: 32 Kbyte code, 32 Kbyte data2nd Level: 2 x 128 Kbyte back side 3rd Level: 2 x 1 Mbyte with ECC front side

CoreNet Switch Fabric cache-coherent crossbar interconnect

Memory Management MMU for each corePAMU for the I/O channels

Main Memory 2 separate memory controllers for DDR2/3 SDRAM 32/64 bit data bus with ECC, up to 1.6 GHz clock

High Speed Interconnect 3 PCI express® 2.0 controller2 serial RapidIO controller

Ethernet

8 x 10/100/1000 Ethernet controller2 x 10GE controller classification/policing H/W queuing, policing, buffer management,checksum offload, QoS, losslessflow control, IEEE® 1588, SGMII/XAUI

Data Path Acceleration10Gb/s IP forwarding, 64B packets SEC 4.0: 10Gb/s IPSec, 1456B packetsPME 2.0: 10Gb/s IDS, 1456B packets


Main features of the P4080 Processor

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Redundancy and I/O Structure of the MUSE

High Performance Processing Node (HPPN)

ADCSS 2011 System Architecture

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ADCSS 2011 Hardware Structure

MUSE Processor Board+ 12 V+ 5 V

CPU Monitor

FPGA Monitor

power connector (for testing)

DDR2 MEMORY

NAND Flash

PC

DebugJTAG

2 GB DDR3 MEMORY

RS‐232

17 x SERDES for:4 x 1Gb Ethernet2 x Rapid IO2 x PCIen x spare

control/ state

Power ConversionHousekeeping

Clock

NOR Flash

N x LVTTL for:1 x SpaceWire1 x RS‐4851 x CAN n x spare

Test

RS‐232 CON

RS‐232 CON

RS‐232

MagneticsRJ45Ethernet

1Gb‐Ethernet

FREESCALEP4080

Radiation tolerantFPGA

ELB

+ 12 V+ 12 V+ 5 V+ 5 V

CPU Monitor

FPGA Monitor

power connector (for testing)

DDR2 MEMORY DDR2

MEMORY

NAND FlashNAND Flash

PCPC

DebugJTAGDebugJTAG

2 GB DDR3 MEMORY 2 GB DDR3 MEMORY

RS‐232RS‐232

17 x SERDES for:4 x 1Gb Ethernet2 x Rapid IO2 x PCIen x spare

control/ state

Power ConversionHousekeeping

Clock

NOR FlashNOR Flash

N x LVTTL for:1 x SpaceWire1 x RS‐4851 x CAN n x spare

Test

RS‐232 CONRS‐232 CON

RS‐232 CONRS‐232 CON

RS‐232RS‐232

MagneticsMagneticsRJ45RJ45Ethernet

1Gb‐Ethernet

FREESCALEP4080

FREESCALEP4080



ELB

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ADCSS 2011 Hardware Structure

MUSE I/O Board

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Error Detection and Error Handling• System level 1oo2d system• Multi-Core P4080 redundant computations• Caches EDC (L3) and parity (L1, L2)• Node memory redundant memory banks with EDC• Flash memory RAD Hard, redundant copies with CRC• FPGA radiation tolerant (TMR)• Control output synchronizing voter (FPGA)• Hardware watch-dog for unspecific errors in HW or SW• Monitoring of all supply voltages, currents and temperatures• Default error handling by node RESET and node-switch

ADCSS 2011 FDIR Concept (Hardware)

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Process- and task level redundancy:• Compute intensive: no redundancy (plausibility check)

• Mission critical: dual mode redundancy (compare and restart)

• Mission critical + real time: triple mode redundancy (synchronized voting)

ADCSS 2011 FDIR Concept (Software)

Diagnoses tasks for self checking of the nodes

Hardware watchdog for heartbeat control:• Diagnoses- and application tasks supervisor process (replicated)

• Supervisor process re-triggers hardware watchdog (TMR FPGA logic)

Dual node concept (Worker/Monitor)• Software RESET and node-switch for all detected errors not handled locally

• Outage time can be optimized by continuously sending actual state

information to the monitor node (task-specific)

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ADCSS 2011 Assembly

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ADCSS 2011 Assembly

Node 2

Node 1

I/O Board

Heat Pipes

Stack-Down Configuration

I/O I/O

I/O I/O

I/O

I/OI/O

MCU

I/O

MCU

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Thank you for your attention!Contact and further information:

Thomas [email protected] [email protected] van [email protected] [email protected]

Fraunhofer FIRSTDepartment Embedded Systemshttp://www.first.fraunhofer.de/EST

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ADCSS 2011 System Architecture

Scalability and Integration into the Communication Infrastructure of a Satellite

Rapid IO3,125 GBit/s

MUSE HPPN 1 MUSE HPPN 2

To HPPN ior Subsystem

To HPPN jor Subsystem

SpacecraftComputer

Mass Storage

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ADCSS 2011 FPGA Technology

Microsemi (Actel) A3PE3000L3 Mio. System gates in 75.264 VersaTiles341 single-ended I/Os / 168 differential I/OsFlash-based configuration memoryLow power consumption

Pin and design compatible space version available (RT3PE3000L)SEU immune Flash memoryRadiation hard by design (TMR syntheses by design software)

evaluation of the multi-core technology for demanding space … · memory management mmu for each...

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