evaluation of different wireless communication systems for ...evaluation of different wireless...

Evaluation of Different Wireless Communication Systems

For Intracortical Prosthesis

Cortivis Report

Deliverable D4

By INESC-ID

Evaluation of Different Wireless Communication Systems for Intracortical Prosthesis

2

Contributions to this report

This report includes written contributions and results of research work of: Prof. Gonçalo Tavares,

Prof. José Gerald, Prof. Moisés Piedade and Engº Ricardo Ribeiro (PhD student). The report also

includes work developed by the undergraduate students Ricardo, Elísio and Manuel.

The reported work benefit with the helpful discussions in the periodical meetings, realized within the

SIPS research group, aiming the architecture definition of the intracortical prosthesis and the design of

VLSI circuits. It includes suggestions of Prof. Leonel de Sousa, Profª Beatriz Borges, Prof. Jorge

Fernandes, Prof. Marcelino Santos, Prof. Pedro Santos and Prof. Carlos Martins.

The work also benefits with the information given by all CORTIVIS partners.

CORTIVIS

3

Architecture of the intracortical prosthesis system

This document reports some of the work developed by INESC in the first year of the CORTIVIS

project, namely in the design of the intracortical prosthesis. The block diagram of the intracortical

prosthesis system under development is shown in Fig.1 below. The system is divided in two parts: the

primary and the secondary system. The former is located outside the human body and the later is

designed to be placed inside the human body (not necessarily inside the head). Two radio frequency

(RF) data links connect these systems: a forward link which transmits data from the primary to the

secondary system and a backward link which operates in the reverse direction. Both links may operate

simultaneously (full-duplex mode) or in half-duplex mode. It is yet to decide whether need for full-

duplex operation is required. The forward link transmits a power/data signal modulated carrier in the 4

-16 MHz frequency range at a data bit rate up to 1 Mbps using ASK (Amplitude Shift Keying) or FSK

(Frequency Shift Keying) modulation. After demodulation and frame disassembly, useful data is

forward to the electrode stimulator. This bit rate is enough to drive about 1000 implanted electrodes.

The secondary power and main system clock are derived from the forward link signal. In the opposite

direction BPSK (Binary Phase Shift Keying) will be used to modulate a carrier at a bit rate up to 16

kbps which suffices for maintenance purposes. The coupling between the primary and the secondary

system is done using a RF low coupling transformer.

Fig.1- Architecture of the intracortical prosthesis system.

This report is organized in four sections, each addressing the following material:

• Section 1 deals with the design of the coupling transformer. Several problems regarding the

magnetic coupling between primary and secondary coils were identified. Among these, the

most important is the high variability of the coupling, which depends on misalignment,

distance and load. To overcome these problems, a number of transformer design solutions were

FILTER

DATACONTROLLER

AMPLIFIERPOWERMODULATOR

CLOCK

DEMODULATOR AGC

Dat

a

Di

PC

POWERAMPLIFIER

DEMODULATOR

RF

RF

DATAPROCESSING

RF LINK

CONTROLCIRCUIT

POWER SUPPLY

GENERATOR

CLOCKRECOVERY

DATAPROCESSING

Adress

Command

ELECTRODESSTIMULATOR

Data

Data

Electrodes

Command

MODULATOR

Enable

PRIMARY SYSTEMSECONDARY SYSTEM


4

built and tested. The necessary transformer models were also developed and their accuracy

evaluated.

• Section 2 presents the forward link design and is divided in several subsections each devoted to

one particular functional block. Section 2.1 treats the problem of carrier recovery. The RF

transceiver, using both ASK and FSK modulation schemes, has been simulated at the

functional level, first and at circuit level afterwards. The previously developed RF transformer

models were included in the simulation model. Several simulations using a carrier frequency of

8 MHz and a data rate of 1 Mbps were performed in order to evaluate the transmitter

performance under different conditions, such as different transmission channels, modulation

level, filters type and filter bandwidths, and transmitter/receiver architectures. This work is

presented in Sections 2.2 and 2.3. In Section 2.4 a comparison between ASK ad FSK is

presented; it justifies the final decision to use FSK instead of ASK. Section 2.5 presents the

design of the bit synchronizer used in the receiver. Finally, some problems and solutions

regarding the power delivery are presented in Section 2.6.

• Section 3 presents the backward link design which is still in an initial developing phase.

• The final conclusions and future work perspectives are presented in Section 4.

1 Transformer design

1.1 Introduction

The electronic circuits in the cortical prosthesis developed in the CORTIVIS project need to be

wireless power supplied by an external system, see Fig. 1.1.

The cortical prosthesis is provided with a bidirectional data link to the outside system. Both power and

data will be transferred by a radio frequency (RF) transformer composed by an external coil and an

internal one placed inside the prosthesis. The coils may be separated about 1 to 3 cm, see Fig.1.2. This

transformer has a very low coupling coefficient between the two coils, so, at the first analysis, it is

expected to have low power transfer efficiency. This will be contested in this document, by adoption

of some circuit techniques and RF coil design rules.

CORTIVIS

5

The expected bit rate of the communication between the external system and the prosthesis is about

1Mbps. To support this bit rate a carrier frequency in the range 4 MHz to 20 MHz is required. In the

following design examples, we will use 8 MHz for the carrier frequency.

DATA ANDPOWER

TRANSMITTERRECEIVER

RECEIVER INTERNALTRANSMITTER

DATACONTROLLER

Dat

a

Cortivis

High LevellCONTROLLER

POWER SUPPLYGENERATOR

DATAPROCESSING

STATE MONITOR

Dat

a

RF

RF

VARIABLES

ELECTRODESSTIMULATOR

STATESENSORS

RF LINK Fig. 1.2- Detail of RF link to intracortical electrodes.

1.2 RF transformer model

Without any prior estimate of the prosthesis minimum size, we made the hypothesis of using a

maximum coil diameter of 3 cm (coil will be placed in the border of the prosthesis). Smaller coils will

be very sensitive to geometric distance variance between position of internal and external coils. Coils

must be placed in a parallel-resonant circuit with an integrated small capacitor (smaller than 20 pF)

which defines the carrier frequency of a band-pass filter. The required self inductance is 160 µH; this

can be obtained by 50 turns of copper wire (0.2 mm diameter) wound in 8 layers over a 3 cm diameter

air form (Rayner formula for multilayer cylindrical coils, see Annex 1.), which results in the values of

L1 given in Table1.1.

Fig. 1.1- RF link to intracortical electrodes


6

Experimental measurement of the coil reveal the model represented in Fig.1.3a), with a very high self

capacitance, Cp = C and high AC resistance R, compared to the DC resistance RDC (R ≅ 32 × RDC).

This is due to the skin effect, see Table 1.1. This inductor can not be used because the self-resonance

frequency, fp, is lower than the required carrier frequency (at 8 MHz the inductor is capacitive); this is

due to the high self-capacitance value.

Table 1.1- Experimental results for RF coils.

Reducing the inductance lowers the number of turns and layers of the coil, but the self-capacitance

does not lower significantly. To reduce self-capacitance and AC resistance, planar coils realized in an

appropriate substrate will be the next step to follow in the project.

LR

Cp

a)

b)

λ11R11

LΜ

n:1λ22 R22

c)

λ11R11 nLΜ

λ'22= n2λ22

R'22=n2R22

n:1

v2vMv1

Cp1

Cp1 C'p2=Cp2 / n2

Cp2

Fig. 1.3- RF transformer model.

However, inductors L5 and L6, realized with a single wire layer, having a self resonance frequency

above the desired carrier frequency, are appropriate to build a prototype of an RF transformer, and in

the following will be named L1 (primary coil with n1 wire turns) and L2 (secondary coil with n2 wire

turns), respectively. Inductors L1 and L2 placed side by side at a distance d, realize an RF transformer.

CORTIVIS

7

The electrical current I in L1 generates a total magnetic field flux L1× I, but due to the coil physical

separation only a fraction of this flux is coupled with L2, representing the mutual induction LM, and

consequently induces a voltage on L2. The other portion of magnetic flux, which is λ11 × I (dispersion

flux), does not contribute to induce voltage on L2. Anyway L1 = λ11 + LM and L2 = λ22 + LM.

The RF transformer model, represented in Fig.1.3b), takes into account the flux dispersion, skin effect

resistances and self capacitances of both inductors, L1 and L2. The ideal transformer takes into account

the ratio n of number of turns of L1 e L2 (n = n1 /n2). In our case n = 1. The circuit in Fig.1.3c)

represents the RF transformer model referred to the primary side

1.3 Study of transformer coupling

The coupling coefficient between primary and secondary coils is defined by k = LM(L1L2)-1/2 . By

inspection of Fig.1.3c) it can be concluded that the low value of LM (high λ11) originates a great

Fig.1.4 – Jig for RF transformer testing.


8

reduction of voltage vM and v2 and, as a consequence, very low voltage transfer efficiency between

primary and secondary coil is expected. Using the empirical formula included in the annex 1, the

coupling coefficient for different separation distances between primary and secondary coils was

calculated. In order to measure the coupling coefficient, an experimental test jig was constructed. It´s

photo is shown in Fig.1.4.

Both theoretical and experimental results obtained for the transformer made with inductors L5 and L6

(Table 1.1), are represented in Fig.1.5, where a good value agreement for k was achieved, specially in

the distance region of 1 cm to 3 cm, covering the distances that will be used in CORTIVIS

intracortical prosthesis.

The open circuit voltage transfer function of the RF transformer, using the model of Fig.1.3c), built

with parameters L5 and L6 given in Table 1.1, and values of coupling coefficient variable between 0.1

and 0.4, was simulated in the SPICE program. The results obtained are shown in Fig.1.6.

0 0.5 1 1.5 2 2.5 3 3.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

K

distancia (centimetros)

Fig.1.5 – Theoretical and experimental (dot points) RF transformer coupling coefficient.

CORTIVIS

9

The experimental results obtained by measuring the transformer, see Fig. 1.7, agree very well with the

simulated ones, validating the model used.

104 105 106 107 108-60

-50

-40

-30

-20

-10

0

10

20

frequencia (Hz)

Gan

ho (d

B)

Fig. 1.7 – Experimental voltage transfer ratios for distances of 0 cm, 1 cm, 2 cm and 3 cm

between primary and secondary coils with RL = ∞.

1.4 Frequency response of the loaded RF transformer

The low value of k means L1 ≅ λ11>> LM and L2 ≅ λ22 > LM. There are big reactive voltage drops in λ11

and λ22, which reduces the voltage ratio v2/v1 (see Fig.1.3c) between primary and secondary coil.

However, these voltage drops can be compensated by opposite voltages developed in resonant series

Frequency

10KHz 30KHz 100KHz 300KHz 1.0MHz 3.0MHz 10MHz 30MHz 100MHzvdb(rl:2)-vdb(r4:2)

-60

-40

-20

-0

20

40

Fig. 1.6 – SPICE simulation of voltage transfer ratio of RF transformer with RL

= ∞, for different values of k. (k = 0.1, 0.2, 0.3 and 0.4).


10

capacitors CA and CB, placed between the transformer and the source generator (RS and vS) and also

with load RL, respectively, see Fig.1.8.

λ11R11nLΜ

λ'22=n2λ22

R'22= n2R22

n:1

v2vMv1

Cp1 C'p2= Cp2 /n2

CBCA

vP vS RLvS

RS

Fig. 1.8 – Complete model of the RF coupling link between external system and

intracortical prosthesis.

This is a complete model of the RF coupling link usable both for power transfer and bidirectional data

transmission between the external system and intracortical prosthesis. To obtain the frequency

response of the communication channel and the power transmission efficiency from the generator vS to

the load RL, the circuit shown in Fig.1.8 was simulated on SPICE, for different values of RL around

the expected value correspondent to the prosthesis power consumption of 125 mW ( 5 V @ 25 mA)..

The results in Fig.1.9 show the expected frequency response and its variability with load conditions.

These are fundamental results showing that an expected power of 200 mW, increasing vS, can be

obtained for supplying the intracortical prosthesis circuitry and also showing the expected data

channel frequency response to be taken in account in the design of the data communication system.

Frequency

2MHz 4MHz 6MHz 8MHz 10MHz 12MHzvdb(r1:2)-vdb(r3:1)

-40.0

-20.0

-0.0

-59.9

15.0

Fig. 1. 9 – Frequency response of the data communication channel for different transformer

coupling factor k and RL = 200 Ω. (k = 0.1, 0.2, 0.3 and 0.4).

CORTIVIS

11

Frequency

2MHz 3MHz 4MHz 5MHz 6MHz 7MHz 8MHz 9MHz 10MHz 11MHz 12MHzVdb(R1:2)-Vdb(R3:1)

-60

-40

-20

0

20

Fig. 1. 9 – Frequency response of the data communication channel for different load resistances

RL and a transformer coupling factor of 0.2. (RL = 100 Ω, 300 Ω, 500 Ω, 700 Ω and 900 Ω).

2 Forward link design

2.1 Carrier recovery

2.1.1 Introduction

The purpose of this receiver block is to recover a clock signal from the incoming RF signal, to serve as

a master system clock. In order not to compromise system performance, it is of fundamental

importance that this recovered clock be of the highest quality possible. The simulation results for the

ASK modulation scheme indicated the need of PLLs (Phase Lock Loops) in both the received data and

the master clock circuitry, in order to achieve precise frequency (no significant jitter) signals. Also, the

ASK modulation scheme presents a significant problem, which is to be highly dependent on the

channel amplitude response (which is unknown and may vary in time). Results also show that the FSK

scheme is more robust to the main problem which is the high variability of the RF channel.


12

2.1.2 SPICE simulations

The carrier recovery circuit has been simulated at the circuit level using SPICE. The actual circuit

simply a charge-pump Phase Locked Loop (PLL) which is represented in Fig.2.1.1.

g2vb

g1va

500p

1k

vc

500p

'1'

va

vb

1Meg

1Meg

5v

g4vc

g3vc

1MegD Q

CLK R

D Q

CLK R

D Q

CLK R

'1''1'

g1=g2=1m g3=26u g4=37,2uVout (160)

Vin (8)

Fig.2.1.1- Electrical diagram of the Charge-pump Phase Locked Loop (PLL).

In Fig.2.1.2 we present simulation results regarding the carrier recovery circuit operating with an ASK

modulated signal.

Fig.2.1.2– Carrier recovery circuit operation: input ASK signal, error signal and

output PLL signal.

After a transient period of about 1.5µs, which is roughly one and a half bit, the PLL error signal

stabilizes providing a clock signal to be used as the master system clock. Since, at the transmitter, the

carrier frequency is synchronized with the data, the recovered master clock is also synchronized with

the received data (the actual phase difference is unknown but will be properly adjusted by the bit

synchronizer described in Section 2.5).

Time

0s 0.5us 1.0us 1.5us 2.0us 2.5us 3.0us 3.5us 4.0us 4.5us v(160) v(132) v(8)

-2.0V

0V

2.0V

4.0V

5.0V

ASK signal (PLL in)

VCO out (recoverd clock)

error signal vc(132)

CORTIVIS

13

The carrier recovery results for operation from a FSK information signal are given in Fig.2.1.3.

Fig.2.1.3– Carrier recovery circuit operation with FSK signal.

The PLL used is the same although with different parameters. It can be seen that a clean recovered

clock is present at the PLL VCO output. The most important conclusion from these results is that the

carrier recovery signal processing requirement is the same regardless of the modulation employed

(ASK or FSK).

2.2 ASK modulation

2.2.1 Introduction

To evaluate the modulation scheme used in the RF link, it was tested, by its simplicity, robustness and

reliability, a binary ASK (Amplitude Shift Keying) transmitter, also called OOK (On-Off Keying)

when one of the amplitudes is chosen to be zero. However, the need of obtaining the receiver power

supply from the received signal, makes it undesirable to have zero energy received signal periods.

Thus, the OOK modulation was abandoned and an amplitude modulation with data enveloping was

adopted. Non coherent detection was used in order to avoid the need for a local carrier at the receiver,

resulting in a much simpler demodulator. A low value (17.6%) of percentage modulation was assumed

(carrier amplitude with values 0.7 or 1). The percentage modulation was chosen taking in

consideration 2 factors: (i) the need of the most energetic signal always present at the receiver (the

receiver is inside the patient head) and (ii) the distortion caused by the coupling transformer included

in the transmission path.

Time

2.0us 3.0us 4.0us 5.0us 6.0us 1.2us V(8) V(84)

-5.0V

0V

5.0V

FSK signal

Recovered clockV(83) V(19)

2.15V

2.20V

2.25V

SEL>> Transmitted data

PLL error signal


14

2.2.2 SIMULINK evaluation

The RF transmitter using an ASK modulation scheme was simulated at the functional level first and at

circuit level afterwards using respectively Matlab and Spice simulators. In the simulations the

transformer models previously developed were included. The simulations have shown that the ASK

modulation index should be lower than 30% in order to avoid signal degradation and the subsequent

need for equalization.

A transmission system was simulated by means of simulation program Matlab with Simulink, from

MathWorks. The carrier frequency used was 8 MHz for a data rate of 1 Mbps. Several simulations

were performed in order to evaluate the transmitter performance under different conditions, such as

transmission channels, percentages of modulation, filters bandwidth, and emitter/receiver

architectures. The main goal was to minimize received data errors and data clock jitter.

The ASK simulated transmission system is represented in Fig. 2.2.1.

Fig. 1 – ASK transmission system

Fig. 2.2.1 – ASK transmission system.

Emitter

1 R

Channel

CORTIVIS

15

The transmission system is composed of a transmitter, a channel and a receiver. The transmitter

generates the 17.6 % percentage of modulation amplitude modulated signal. This signal is passed

through a passband channel before it gets to the receiver. In the receiver, two main tasks are performed

and tested: (i) to generate the receiver master clock, a high frequency clock with 8 MHz, which is

obtained from the carrier, and (ii) to recover the data information by means of a noncoherent adaptive

demodulator. An optimal data signal is also generated at the receiver, in order to compare with the

adaptive demodulator result. This optimal demodulator uses the knowledge of the channel attenuation,

which, in a real system, is not usually possible.

The system allows observing several signals, as for instance, the received data signal. An eye diagram

of the received data signal can be seen in Fig.2.2.2. This information is relevant, for instance, to decide

which is the best timing to sample the signal in order to decide about the received bit value.

a) b)

c)

Fig. 2.2.2 – Received data eye diagram. a) low-selective and flat passband channel; b) high-selective and flat passband channel; c) high-selective and non-flat passband channel.


16

From Fig.2.2.2 one can see how the received data signal optimal sampling time change with the

increase of channel selectivity. Also the data signal is very dependent from the amplitude response

shape, which makes the data discriminator very critical.

Fig.2.2.3 shows the received carrier zero crossing eye diagram. In this figure, one can see the

associated jitter caused by the transmission channel. With non-flat passband the amplitude response of

the received carrier zero crossing present a slightly bigger maximum jitter than with a flat passband.

Also, the jitter is mainly influenced by the percentage modulation, as can be seen in Fig.2.2.3c) where

the percentage modulation is now 53.8%.

a) b)

c)

Fig. 2.2.3 – Received carrier zero crossing eye diagram. a) 2 MHz flat passband channel and 17.6% modulation; b) 2 MHz non-flat passband channel and 17.6% modulation; c) 2 MHz flat passband channel and 53.8% modulation.

CORTIVIS

17

The adaptive discriminator implemented in the receiver is a good solution to track the data signal

amplitude fluctuations, as can be seen in Fig. 2.2.4. This figure shows the data signal and its estimated

mean value. One can see the initial transient and the posterior stationary functioning of the adaptive

Fig. 2.2.4 – Received data adaptive discriminator.

discriminator in its task to track the data mean value. As the RF channel may vary in time and from

patient to patient, an adaptive solution is required.

The simulation results for the ASK modulation scheme indicated the need of PLLs (Phase Lock

Loops) in both the received data and the master clock circuitry, in order to achieve precise frequency

(no significant jitter) signals. Also, the ASK modulation scheme presented a relevant problem, which

is to be highly dependent from the channel amplitude response (which is unknown and may vary in

time), because of its great dependence from the received signal amplitude, specially the amplitude

distortion.


18

2.2.3 SPICE evaluation

In this section we present a simulation study of the CORTIVIS forward link using ASK modulation.

The simulation is performed at circuit level using the program SPICE. The schematic circuit of the

ASK transmitter, including the RF transformer model, is shown in Fig.2.2.5.

Fig.2.2.5- SPICE circuit model used for the CORTIVIS ASK transmitter.

n Fig.2.2.6 we represent the random Non-Return-to-Zero (NRZ) data signal at 1Mbps and the ASK-

modulated signal with a carrier frequency of 8MHz and a modulation index of 30%, measured at the

receiver input (v(8) in the schematic of Fig.2.2.5).

Fig.2.2.6-Waveforms for ASK modulation.

Vcc10V

L1

16uH

RL 200

C22

16.5p

R15 820

Cp4.1pF

Cs 4.1p

Rs

50

L2

16uH

R14 1k

R2

357 Q1 .

C11

412uF

Q5 .

Q4 .

CM

16.5p

R16 100

LM4uH

R13 500

R8

50

Rp

50

LRF 1797.7nH

Q6 .

R1 180

V1

RANDOM DATA GENERATOR

T=2us

F=8MHZ

V(8) RF TRANSFORMER MODEL

Time

0s 5us 10us 15us 20us 25us 30us 35us 40us v(8) v(214)

-2.0V

0V

2.0V

4.0V NRZ

CORTIVIS

19

Note the time delay of approximately one bit between the data and the envelope of the modulated

waveform.

To recover the data from the ASK signal a noncoherent demodulator is employed. It is implemented

by an envelope detector and a threshold estimator followed by a comparator.

Vcc

1Meg

1K35k

100pF

10k

10k

50nF

Va

Vb

Ω

Ω

Ω

Ω

ΩASK signalData out

Fig.2.2.7- ASK noncoherent demodulator.

The ASK demodulator is depicted in Fig.2.2.7. It consists on two half-wave passive rectifiers followed

by two lowpass integrating filters with different time constants. The filter producing Vb has a small

time constant allowing data to pass and cutting harmonic components generated by the rectifier. On

the other hand, the filter producing Va is designed to have a much lower cutoff frequency as is

required to estimated the DC component of the signal. Both filter outputs are used by a schmitt-trigger

comparator to detect the received data. The signal Va acts as a dynamic threshold accounting for

possible amplitude variations of the received ASK information signal. The simulation results for these

signals are given in Fig.2.2.8. It should be pointed out that the use of a Schmitt-trigger comparator is

absolutely necessary. This is due to the fact that still a significant amount of harmonics pass through

the lowpass filter and appear in Vb as can be clearly seen in this figure.


20

Fig.2.2.8- ASK demodulator waveforms: Va is the threshold signal used by the comparator.

The signal at the comparator output is plotted in Fig.2.2.9 together with the received ASK waveform.

Again, it is noticeable the delay between the two signals which is due to the signal processing. As can

be seen by comparing the recovered data with the NRZ data (transmitted data) in Fig.2.2.6, there are

no data errors (note that the recovered data is complemented).

Fig.2.2.9- Recovered data from the ASK information signal.

2.3 FSK modulation

2.3.1 Introduction

One of the modulations considered to be used in the RF forward link of the CORTIVIS system is

binary FSK (Frequency Shift Keying). With this modulation, each bit is assigned a different frequency

Time

0s 5us 10us 15us 20us 25us 30us 35us 40us v(8) v(64)

-2.0V

0V

2.0V

4.0V

Received ASK waveform

Recovered data

Time

0s 1us 2us 3us 4us 5us 6us 7us 8us 9us 10us v(58) v(54)

-200mV

0V

200mV

400mV

600mV

Vb

Va

CORTIVIS

21

deviation from the central carrier frequency which as been set at 8 MHz. The simulation results

presented here, as well as the theoretical considerations in Section 2.4 lead to the conclusion that this

modulation will be the best choice for the CORTIVIS RF forward link.

2.3.2 SIMULINK evaluation

The system was simulated in Simulink, a component of the MATLAB simulation software, as is

depicted in Fig.2.3.1.

In1

In2

errorsnum

error

error counter

PLL (XOR)

datadem odulation

VCO

Voltage-Control ledOsci l lator

T ransportDelay

Sum Scope

Relay2

Relay1

Out1

Pseudo Randomdata generator

Periodogram

Periodogram

MuxMux1

.9

FrequencyVector Scope1

FrequencyVector Scope

0

Display

data

c lock

sy nc_data

data_clock

Data sincronization

(3 2 2 1 0)

Constant

butter

Channel

PLL (XOR)

master clockrecovery

Data Clock

TransmiterReceiver

Fig. 2.3.1 – FSK transmission system simulation.

The transmitter contains a data generator and a FSK modulator. The modulator was done with a VCO.

The VCO switches between two carrier signals according to the value of the incoming data bit. The

carrier frequencies chosen where 8.25MHz for the high bit level and 7.75MHz for the low bit level,

which is equivalent to a central carrier of 8MHz with an 250KHz frequency deviation. The bit rate is

1Mbps.

The FSK modulated signal spectrum, shown in Fig.2.3.2, has the first two local minimums at 7.25

MHz and 8.75MHz, meaning that most of the signal’s energy is located between those two


22

frequencies. The transmission channel was simulated by a second order Butterworth passband filter

centered at 8 MHz with a 2 MHz bandwidth. The receiver input signal spectrum is depicted in

Fig.2.3.3.

Fig.2.3.2 - Spectrum of the FSK modulated signal.

Fig.2.3.3 - Spectrum of the signal at the input of the receiver.

In order to demodulate the FSK signal a broadband phase-locked-loop (PLL, Fig.2.3.4) was used. The

PLL will follow the frequency of the signal at the input of the receiver and at the lowpass filter output

CORTIVIS

23

will have the demodulated signal which is then passed trough a discriminator. The discriminator will

recover the original bit stream. The signals before and after the discriminator can be seen in the second

plot from the top of Fig.2.3.5. Another PLL, now a narrow-band one, was used to recover a master

clock with a frequency equal to the central carrier frequency (see Section 2.1). This time we use the

signal at the output of the PLL’s voltage controlled oscillator (VCO). The master clock and the

demodulated bit stream were feed to the data synchronization block. This block recovers a clock

synchronized to the data bit stream. The data bit stream can be observed in the third plot from the top

of Fig.2.3.5 and the data clock in the fourth plot. As can be observed, the original bit stream is

successfully recovered. In fact no transmission errors where detected during the simulations performed

Fig.2.3.5 - Time plot. The top signal is the generated bit stream. Below that is the demodulated signal before and after the discriminator (both overlapped). The last two are the bit stream and the data clock recovered by the data synchronization block.

3

2

1

VCO

Fn(s)

Fd(s)T ransfer Fcn

Relay1

Relay

XOR

LogicalOperator

G

1

Fig.2.3.4 – Phase-locked-loop (PLL).


24

2.3.3 SPICE evaluation of system using FSK

In this section we present a simulation study of the CORTIVIS forward link using FSK modulation.

The simulation is performed at circuit level using the program SPICE. The schematic circuit of the

FSK transmitter, including the RF transformer model, is shown in Fig.2.3.6.

Fig.2.3.6- SPICE circuit model used for the CORTIVIS FSK transmitter.

In Fig.2.3.7 we represent the random Non-Return-to-Zero (NRZ) data signal at 1Mbps and the binary

FSK-modulated signal with a carrier frequency of 8 MHz and a total frequency deviation of 500 kHz

(the transmitted frequencies corresponding to the possible bit values are 7.75 MHz and 8.25 MHz),

measured at the receiver input (v(8) in the schematic of Fig.2.3.6).

Fig.2.3.7- Waveforms for FSK modulation.

Note that because the two frequencies are very close, their difference is hardly noticeable in this

figure.

LRF 1797.7nH

RL 200

R33 3K5

Rp

50

Q1 .

R32 6k5

R8

50

Vcc10V

R15 820

Cp

4.1pF

R1 180

VCO LM4uH

Q4 .

L2

16uH

R13 500

C22

16.5p

Q5 . R14 1k

Cs 4.1p

L1

16uH

R16 100

Rs

50CM

16.5p

R2 357

V(8)

Q6 .

C11

412uF

RF TRANSFORMER MODEL

Time

2.00us 3.00us 4.00us 5.00us 6.00us 1.27us 6.61us V(19)*10-21.8 V(8)

-1.00V

0V

1.00V

-1.61V

1.61V NRZ

FSK modulated waveform

CORTIVIS

25

To recover the data from the FSK signal a coherent demodulator is employed. It is implemented by a

phase locked loop (PLL) similar to the one used to recover the carrier clock (see Section 2.1) and

represented in Fig.2.1.1. The PLL error signal is then fed to a regenerative comparator similar to the

one used for ASK detection and represented in Fig.2.2.7. The output of this comparator is the detected

data.

The simulation results for these signals are given in Fig.2.3.8.

Fig.2.3.8- FSK demodulator waveforms.

As with the ASK receiver, the use of a Schmitt-trigger comparator is necessary. This is due to the fact

that still a significant amount of harmonics pass through the lowpass PLL filter. The most important

aspect revealed by these results is that the threshold signal required for detecting the data is fixed, i.e.,

does not need to be estimated from the incoming RF signal (as was the case with ASK). Therefore, it

is guaranteed that even with very small signal amplitude the system will operate reliably.

2.4 ASK vs FSK

This section presents some theoretical guidelines which were relevant in the decision about the most

appropriate modulation format for the forward RF link (primary-to-secondary system). The

modulations which have been considered are binary ASK (Amplitude Shift Keying), binary FSK

(Frequency Shift Keying) and BPSK (Binary Phase Shift Keying). Together with the results in Sections

2.2 and 2.3, the following considerations justify the final choice of modulation which is to be FSK in

the case of the forward link and BPSK for the backward link:

Time

1.400us 1.600us 1.800us 2.000us 2.200us 2.400us 2.600us 2.800us 1.239us V(124) V(8)

-5.0V

0V

5.0V

SEL>>

Recovered data

FSK signal

V(43) v(123)

1.5V

2.0V

2.5V

PLL error signal Decision threshold level


26

• ASK is better than FSK in terms of carrier (i.e., clock) recovery easiness: with ASK, a fraction

of the carrier is sent together with the information signal. With FSK, the transmitted spectrum

does not contain specific energy at the carrier frequency; consequentially, carrier recovery is

more difficult and requires a separate, narrow-band PLL (Phase Locked Loop). However, since

the ASK carrier recovery subsystem must also contain some pass-band filtering, it seems that

the required resources for this task will be the same for both modulations.

• Both ASK and FSK require the same bandwidth.

• With a time-invariant, constant gain channel, ASK may be demodulated with a simple non-

coherent receiver, which is a simply an envelope detector followed by a decision device

(comparator). Non-coherent detection of binary FSK requires two separate precise-tuned

bandpass filters and is thus much more complicated. However, coherent demodulation of FSK

is simple and can be done using a simple PLL. Also, a time-invariant, constant gain channel

does not seem a reasonable assumption for the intracortical CORTIVIS system.

• In the case of both RF links in the CORTIVIS system, the channel gain has a high degree of

uncertainty which translates in high amplitude variations; this is due to the randomness

associated with the coil relative positions. In order to achieve reliable data detection with ASK,

it is therefore necessary to have high-efficient gain-monitoring and level-controlling devices.

This is not the case with FSK for which the receiver front end is insensitive to the amplitude of

the received signal (within reasonable limits). This is a very strong argument for choosing FSK

over ASK.

2.5 Bit Synchronizer

2.5.1 Introduction

A digital feedforward symbol synchronizer was developed and implemented in a low power FPGA

which simplifies the demodulator and can be used in both ASK or FSK demodulation schemes.

In this section, the development of the CORTIVIS secondary system bit synchronizer is presented

(from now on, the secondary system will be referred simply as the receiver). The task performed by

this device is of fundamental importance to establish a proper time reference in the receiver. The

CORTIVIS

27

positive-going transitions in this reference clock should accurately signal the optimum instants to

sample and detect the received data bits. The part of the receiver interacting with the bit synchronizer

is depicted in Fig.2.5.1.

ASK or FSKDEMODULADOR

MASTERCLOCK

RECOVERY

BIT SYNCHRONIZER

masterclock

DATASAMPLER

data Retimed data

Data clock

RF link

CLK bf N R= ´

/bR bit s

bf R=

time

Retimed data

Data clock

1 0 0 1

Fig.2.5.1 – Data clock recovery and bit synchronizer.

The signal received from the primary system (which is referred in this section as the transmitter) is

used to produce the system master clock, with frequency fT

N RCLKCLK

b= = ×1 where R

Tb b=

1 is the

raw bit-rate; this is accomplished by the MASTER CLOCK RECOVERY block using a narrow-band phase-

locked-loop (PLL). At the present stage of the project, target values being considered are Rb = 1

Mbit/s and N = 8 samples per bit, corresponding to a RF carrier frequency of 8MHz. The received

signal is also fed to the data demodulator (binary ASK or FSK modulation), which produces a stream

of raw data bits, but does not provide any time reference signal, required later for proper data

detection. The following point is worth noting: since the master clock is derived from the transmitted

signal and is used to demodulate the data, it follows that the data stream must be synchronized (i.e.,

frequency-locked) with the master clock; a data clock could therefore be obtained by suitable division

(by a factor N ) of fCLK . This is because there is no frequency offset between transmitter and

receiver. Although this is true, the (lead or lag) phase difference between the positive-going clock

transitions and the optimum time epoch for sampling the data which is the middle time of each bit

is unknown. The purpose of the bit synchronizer is thus to provide a stable reference clock with

positive-going transitions signaling the middle of each bit (see the time diagram in Fig.2.5.1).

Nevertheless, the bit synchronizer which has been developed for this project is also able to track small

frequency offsets, with acceptable performance.


28

As it is seen in Fig.2.5.1, the bit synchronizer has a novel feedforward structure; this avoids the

annoying loop behavior known as hang-up, typical with feedback synchronizers, which manifests

itself has an unacceptably long synchronizer acquisition period, compromising receiver operation. In

summary, the bit synchronizer developed has the following desirable properties:

1) In the absence of frequency offset between transmitter and receiver (as is the case in this

application) the recovered clock is jitter-free (neither static nor dynamic phase error).

2) Has a feedforward structure that avoids the hang-up disabling phenomenon.

3) Is easily implemented with simple digital logic.

2.5.2 Synchronizer description

The working principle of the bit synchronizer is best understood with the aid of the waveforms

depicted in Fig.2.5.2.

1/b bT R=

time

Masterclock

0 2bTt +0t

Raw data

Fig.2.5.2 – Bit synchronizer waveforms.

Suppose we have a binary counter being driven with the master clock frequency fCLK ; then, it will

advance N states within each bit period. If, at time t0 , the counter is in state i then, at time

t Tb0 2+ , it will have advanced T

Tf

RNb

CLK

CLK

b2 2 2= = and be in state i N+

2 (on average); this is when

the recovered clock should have a positive transition, marking the middle of the data bit. This

reasoning justifies the block diagram represented in Fig.2.5.3: the positive-going transition on the

data signal (Non-Return to Zero, NRZ random data signal) latches the counter state i , at reference

time t0 , and marks the start of a bit. When the counter reaches the state S iN

= +2

, then

S N N i N N i+ = + =2

mod ( ) mod and the comparator will signal this event to the final processing

CORTIVIS

29

block, which in turn samples the raw data and produces a clock pulse synchronized with the master

clock.

COUNTER

clock

LATCH

ADDER

COMPARATOR

SAMPLER &CLOCK SYNC.

Q

Clock

Retimeddata

Data

2N

mod N

Masterclock

Raw data

2Log N

bits

DQ

A

B

A = B

A

B

Dataclock

Fig.2.5.3 – Conceptual block diagram of the developed bit synchronizer.

2.5.3 Implementation and results

The realization of the synchronizer using N = 8 samples per bit is shown in Fig.2.5.4. The J-K

flip-flops U1-U3, together with the AND gate U4 implement the Log N2 3= bit binary counter; D-

J

Q

Q

K

SET

CLR

U2

J

Q

Q

K

SET

CLR

U1

J

Q

Q

K

SET

CLR

U3

Q

QSET

CLR

D

U5

Q

QSET

CLR

D

U6

Q

QSET

CLR

D

U7

Q

QSET

CLR

D

U13

Raw Data

Master Clock

Retimed data

Data clock

Note: all SET and CLR inputs are connected to ground (disabled)

/bR bit s

CLK bf N R= ´

Realization with samples/bit8N =

U9

U8

U10

U11

U4

U12

VCC

Fig.2.5.4 – Bit synchronizer realization using 8 samples per bit.


30

type flip-flops U5-U7 form the data register, latched by the positive transitions on the raw data

signal.

Gates U8-U11 form the comparator and U12 synchronizes the comparator output with the master

clock transition, producing the recovered data clock. Finally, U13 samples the raw data signal with

this clock signal. Note that the mod N adder in Fig.2.5.3 is implemented by recognizing that the

result of adding N N2

mod to any count C may be found by taking C and complementing its

most significant bit; this is why the second input to U9 in Fig2.5.4 (comparator) is the

complemented output of U3 (i.e., Q instead of Q ). The implementation has been carried out using

simple logic circuits.

The synchronizer has been tested using a random NRZ binary data signal as the raw data input

and an unsynchronised master clock with no frequency offset and also with a frequency offset

equal to 5% the raw bit-rate (which was set at Rb = 1 Mbit/s); this situation reflects a worst-case

operation condition since, as stated early, no frequency offset is expected in the CORTIVIS

receiver. The resulting eye-pattern diagrams for both the data signal and the recovered data clock

are presented in Fig.2.5.5 and Fig.2.5.6.

-0.5 -0.25 0 0.25 0.5-1.5

-1

-0.5

0

0.5

1

1.5

Am

plitu

de

Raw data (eye pattern)

-0.5 -0.25 0 0.25 0.5-2

0

2

4

6Recovered data clock (eye pattern)

Am

plitu

de

Relative time, t/Tb Fig.2.5.5 – Bit synchronizer performance using 8 samples per bit and a master

clock frequency with no frequency offset: Rb = 1 Mbit/s and fclk = 8 MHz.

CORTIVIS

31

In the absence of frequency offset (Fig.2.5.5), the recovered data clock exhibits no jitter and

the positive-going transitions, occurring at t Tb= ±0 25. , accurately mark the optimum sampling

instants, at half the bit duration.

When the master clock has a small frequency offset, the recovered clock will still be

synchronized to the incoming NRZ data stream but will exhibit some amount of phase noise or jitter

(Fig.2.5.6). Because only N = 8 clock periods are available in each bit duration (8 samples/bit), the

synchronizer has an inherent phase error of ± = ±TN

Tb b2 16

, so the positive-going transitions will occur

in a Tb8

-duration interval around the desired epochs t Tb= ±0 25. . This is quite clear in the bottom eye

diagram in Figure 6. Nevertheless, it must be pointed that because high amounts of noise are not

expected in this system (i.e., operation is with a wide open raw data eye diagram), the synchronizer

performance is acceptable even in this worst-case situation (frequency offset equal to 5% the bit-rate).

-0.5 -0.25 0 0.25 0.5-1.5

-1

-0.5

0

0.5

1

1.5

Am

plitu

de

Raw data (eye pattern)

-0.5 -0.25 0 0.25 0.5-2

0

2

4

6Recovered data clock (eye pattern)

Am

plitu

de

Relative time, t/Tb Fig.2.5.6 – Bit synchronizer performance using 8 samples/bit and a master clock

with frequency offset equal to 5% the bit-rate: Rb = 1 Mbit/s, fclk = 8.05 MHz.


32

2.5.4 Conclusions and further work

The development of a new bit synchronizer for the CORTIVIS secondary system RF link has

been described. The circuit is very simple and is ready to be incorporated in the final receiver.

Performance tests have been conducted and the results show that all requirements are largely fulfilled

and that no further adjustments are necessary.

2.6 Power Delivery

Some real experiments were conducted to determine the amount of power which could be

magnetically induced from the primary to the secondary system and the corresponding power

efficiency. Using the resonant transformer design and the transmitter described in Section 1, it was

determined that it is possible to obtain about 200m W of power in the secondary system with an

efficiency of about 50%. These results are presented in Section 1.4. Even considering some additional

power loss in the DC source converters, this seems to be enough for an integrated low-power system

design.

3 Backward link design

The feasibility of a backward (secondary-to-primary) data channel has been investigated. This channel

is required for electrode and system maintenance. The solution offering the best

performance/complexity ratio seems to be the use of a FDM (Frequency Division Multiplexing)

scheme with a constant envelope modulation. It is worth pointing out that even if operation in the

forward channel is in half-duplex mode (in terms of transmission of useful information), a FDM

scheme is necessary because the primary system must continuously transmit a carrier signal to provide

for the secondary system power and clock. Furthermore, the simpler transmitter will result if BPSK

modulation is selected. At this point, the design of this backward link is being evaluated at the

simulation macro level and no final results are yet available. Preliminary results however show that it

is feasible although requiring a relatively complex receiver. This in turn does not pose an

CORTIVIS

33

unsurpassable obstacle since the receiver is located in the primary system where enough signal

processing resources and power are available.

4 Conclusions

The work so far realized has been of significant importance in terms of deciding the modulation type

to use in both links. We are now strongly inclined to use FSK in the forward link and BPSK in the

backward link.

The following points summarize the work that needs to be done in the next phase of this project:

• Develop the required DC-DC converters for the secondary system power supply.

• Specify and Develop the data processing digital block of Fig.1 which is responsible for frame

disassembling and subsequent forwarding of the data bits to the electrode stimulator.

• Determine a suitable carrier frequency to be employed in the backward link and develop the

BPSK transmitter.

• Develop the backward channel BPSK receiver. This receiver is expected to be a lot more

complex than for example the FSK receiver in the secondary system.

• Continue the study leading to the fabrication of the whole system in VLSI integrated circuits.


34

Bibliography

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K. Moxon, J. Morizio, J. Chapin, M. Nicolelis and P. Wolf, ‘Designing a Brain Interface for

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CORTIVIS

35

D. Marín, M. Troosters, I. Martinez, E. Valderrama, J. Aguillo, ‘ New Developments for High

Performance Implantable Stimulators’- Esprit Project ‘Microsystems for Visual Prosthesis MIVIP

LTR-22527.- Proc. Of MicroNeuro’99, Granada 1999, pp. 120-126.

C. Fernandez, O. Garcia, R. Prieto, J. Jacobs, J. Uceda, ‘Overview of different alternatives for

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http://www.pime.iit.edu/

http://neural.iit.edu/intro.html

http://www.bioen.utah.edu/cni/projects/blindness.htm#overview

http://www.dobelle.com/index.html

http://webvision.med.utah.edu/


36

Annex 1

dcd

bddnL 25.2.

10075.43

22 −+

=

Rayner formula for the inductance (µH) of a n turns multilayer cylindrical coil

(dimensions in cm).

( )

+−=

−−

−−=

−=

−=

×=

−=

+=+=+=−=

++=

4

4

2

24

5

2

22

92

22

21

91

125

2

22

352

25

1

13

11

1

2

221

2222

221121

553311

2221

4105.20103.0

;43435.30

43064.0 ;5.19

24.0 ;5.12

; ; ; ;2.2

004.0

al

allak

Ax

rx

ax

rxAK

allak

rx

rxK

lkrx

rx

AK

AxrAxrxDxxDx

KkKkKklxAannLM

Mutual inductance (µH) between 2 single-layer coils (dimensions in cm).

evaluation of different wireless communication systems for ...evaluation of different wireless...

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