eval-ad7293sdz user guide · position b: selects the external avcc (j13) located at the bottom of...

EVAL-AD7293SDZ User GuideUG-817

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the AD7293 12-Bit Power Amplifier Current Controller with ADC, DACs,

Temperature and Current Sensors

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FEATURES Full featured evaluation board for AD7293 Graphical user interface (GUI) software with USB control Various link options

EVALUATION KIT CONTENTS AD7293 evaluation board AD7293 evaluation board software CD

EQUIPMENT NEEDED EVAL-SDP-CB1Z Bench top power supply and connector cables

APPLICATIONS GaN and GaAs power amplifier (PA) monitoring and controls Base station power amplifiers General-purpose system monitoring and controls

ONLINE RESOURCES Documents Needed

AD7293 data sheet AD7293 evaluation board software

Design and Integration Files Schematics, layout files, bill of materials

GENERAL DESCRIPTION This user guide describes the evaluation board for the AD7293, which is a 12-bit monitoring device with a multichannel ADC, DACs, and temperature and current sensors.

For full details on the AD7293, see the AD7293 data sheet and consult it when using the EVAL-AD7293SDZ. The configuration of the various link options is explained in the Evaluation Board Hardware section.

The EVAL-AD7293SDZ requires the EVAL-SDP-CB1Z board. The EVAL-AD7293SDZ interfaces to the USB port of the PC via the EVAL-SDP-CB1Z. Software that allows the user to easily program the AD7293 is available with the EVAL-AD7293SDZ.

EVAL-AD7293SDZ AND EVAL-SDP-CB1Z CONNECTION PHOTOGRAPH

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Figure 1.

http://www.analog.com/AD7293?doc=EVAL-AD7293SDZ-UG-817.pdf




http://analog.com/SDP-B?doc=EVAL-AD7293SDZ-UG-817.pdf






http://www.analog.com/EVAL-AD7293?doc=EVAL-AD7293SDZ-UG-817.pdf









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UG-817 EVAL-AD7293SDZ User Guide

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TABLE OF CONTENTS Features .............................................................................................. 1

Evaluation Kit Contents ................................................................... 1

Equipment Needed ............................................................................ 1

Applications ....................................................................................... 1

Online Resources .............................................................................. 1

General Description ......................................................................... 1

EVAL-AD7293SDZ and EVAL-SDP-CB1Z Connection Diagram ............................................................................................. 1

Revision History ............................................................................... 2

Evaluation Board Hardware ............................................................ 3

AD7293 Power Supply ................................................................. 3

Serial Communication, GPIO, and System Demonstration Platform (SDP) ............................................................................. 6

Closed-Loop Current Control .................................................... 7

ADC Input Links ........................................................................ 12

External Reference Links ........................................................... 12

Temperature Sensor Links ......................................................... 12

Sockets ......................................................................................... 14

Getting Started ................................................................................ 15

Installing the Software ............................................................... 15

Operating the Software .............................................................. 15

Verifying the Links and Powering Up the Evaluation Board ............................................................................................ 16

Evaluating the Board .................................................................. 16

Using the Software .......................................................................... 17

AD7293 Evaluation Board Software Window ........................... 17

Hardware Pins ............................................................................. 18

ADC Monitoring Tab................................................................. 19

Temperature Sensing Tab .......................................................... 20

Current Sensing Tab................................................................... 21

DAC Control Tab ....................................................................... 22

Closed Loop Tab ......................................................................... 23

AD7293 Register Interface Window ........................................ 24

Communications Log ................................................................ 25

GPIOs/Alerts Tab ....................................................................... 26

Evaluation Board Schematics and Artwork ................................ 27

Ordering Information .................................................................... 38

Bill of Materials ........................................................................... 38

REVISION HISTORY 7/2016—Revision 0: Initial Version

EVAL-AD7293SDZ User Guide UG-817

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EVALUATION BOARD HARDWARE AD7293 POWER SUPPLY There are several options available for powering the EVAL-AD7293SDZ, all of which use external power supplies.

The default option for powering the EVAL-AD7293SDZ is to supply J11 or J12 with 9 V.

Supply approximately 8 V to J2, LK_PAVDD (see the Closed-Loop Current Control section and Table 5) with a current limit to avoid a current path to ground via the BSS159 depletion mode transistor.

The supply planes are decoupled to the relevant ground plane using 10 µF and 0.1 µF ceramic capacitors connected to the EVAL-AD7293SDZ. The EVAL-AD7293SDZ requires a number of power supply inputs: AVDD, VDD, VDRIVE, AVSS, DACVDD-UNI, and DACVDD-BI.

LK_AVDDA B

AD7293

AVDDDACVDD_BI

VDRIVEVDD

J1(VDD)

J10(DVDD)

J9(VDRIVE)

J12(PWR)

5VREG

J14(VSS)

J13(VCC)

+5V

+5V

+5V

+3.3VFROMSDP

LK_VDRIVELK_SDP_VDRIVEA B

+3.3V +5V +9V +5V –5V

LK_DVDDA B

+5V

LK_VCCA B

DACVDD_UNI AVSS

–5V

LK_VSSA B

+5V

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Figure 2. AD7293 Power Connector Defaults and Necessary Supply Voltages









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Figure 3. EVAL-AD7293SDZ Power Connections

Table 1. Connector Functions Connector Description J1-1 External analog VDD power connector J1-2 GND power connector J2-1 External PAVDD power connector J2-2 GND power connector J3-1 VPP0 power connector J3-2 GND power connector J4-1 VPP1 power connector J4-2 GND power connector J5-1 VPP2 power connector J5-2 GND power connector J6-1 VPP3 power connector J6-2 GND power connector J9-1 VDRIVE power connector J9-2 GND power connector J10-1 DVDD power connector J10-2 GND power connector J11-1 PWR (9 V) power connector J11-2 GND power connector J12 Alternative PWR (9 V) power connector J13-1 AVCC unipolar DAC supply power connector J13-2 GND power connector J14-1 AVSS negative supply power connector J14-2 GND power connector



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Table 2. Power Supply Link Options Link Mnemonic Description LK_AVDD This link selects the analog VDD supply for the EVAL-AD7293SDZ. Position A: selects the 5 V regulated supply coming from the ADP7104 voltage regulator. Position B: selects the external VDD (J1) located at the top of the board (default). LK_VDRIVE This link selects the logic supply level for the AD7293. Position A: selects 3.3 V that is supplied from the EVAL-SDP-CB1Z (default). Position B: selects an external VDRIVE (J9) located at the bottom left corner of the board. LK_VCC This link selects the positive supply for the unipolar DACs. Position A: selects the 5 V regulated supply coming from the ADP7104 voltage regulator. Position B: selects the external AVCC (J13) located at the bottom of the board (default). LK_VSS This link selects the negative supply for the bipolar DACs. Position A: selects the −5 V regulated supply coming from the ADP3605 voltage regulator. Position B: selects the external AVSS (J14) located at the bottom of the board (default). LK_DVDD This link selects the supply for the AD7293 digital supply. Position A: selects the 5 V regulated supply coming from the ADP7104 voltage regulator. Position B: selects the external DVDD (J10) located at the bottom of the board (default). LK_DVDD1 This link selects the supply for MC74HC244A. Position A: selects the DVDD (J10) as the supply for the MC74HC244A. Position B: selects GND as the supply for the MC74HC244A. LK_PAVDD This link selects the supply for the PAVDD node on the EVAL-AD7293SDZ. Position A: selects the 5 V regulated supply coming from the ADP7104 voltage regulator. Position B: selects the external PAVDD (J2) located at the top of the board. 5V_EXT This external 5 V link connects J1 to the 5 V node. 5V_REG This link (L9) connects the 5 V regulator output to the 5 V node.


http://www.analog.com/ADP7104?doc=EVAL-AD7293SDZ-UG-817.pdf










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SERIAL COMMUNICATION, GPIO, AND SYSTEM DEMONSTRATION PLATFORM (SDP) The EVAL-SDP-CB1Z (SDP-B), system demonstration platform, handles communication to the EVAL-AD7293SDZ via the PC. The SDP-B may require power from the EVAL-AD7293SDZ depending on the current available from the PC USB interface it is connected to. The default option leaves LK_SDP_PWR disconnected, and the logic level is taken from the EVAL-SDP-CB1Z (3.3 V) by inserting LK_SDP_VDRIVE.

The default for the RESET, GPI07/LDAC, and GPIOx/SLEEPx pins on the AD7293 is controlled by the hardware on the EVAL-AD7293SDZ. Use the GPI07/LDAC, SLEEP0, and SLEEP1 jumpers to tie the inputs high (not inserted) or low (inserted). Control RESET using the push-button interface (low when pushed).

Route the pins out to J8 via the options on the LK_RESET, LK_SLEEP0, LK_SLEEP1, and LK_LDAC links. See Figure 25 and Figure 26 for additional information.

Table 3. Serial Communication Link Options Link Mnemonic Description LK_SDP_PWR Insert to provide 5 V power to the EVAL-SDP-CB1Z. LK_SDP_VDRIVE Insert to take the 3.3 V digital signal high level from the SDP as the reference for the serial peripheral interface. LK_SLEEP0 This link determines whether the GPIO5/SLEEP0 pin is controlled by the SDP or by the SLEEP0 link on the EVAL-AD7293SDZ.

Position A: the pin is controlled by the SDP. Position B: the pin is controlled by the SLEEP0 link and pull-up on the EVAL-AD7293SDZ (default).

SLEEP0 If Link B is selected on LK_SLEEP0, this link controls the polarity of the GPIO5/SLEEP0 pin. If inserted, the signal is pulled low. If not inserted, the signal is pulled high.

LK_SLEEP1 This link determines whether the GPIO6/SLEEP1 pin is controlled by the SDP or by the SLEEP0 link on the EVAL-AD7293SDZ. Position A: the pin is controlled by the SDP. Position B: the pin is controlled by the SLEEP1 link and pull-up on the EVAL-AD7293SDZ (default).

SLEEP1 If Position B is selected on LK_SLEEP0, this link controls the polarity of the GPIO6/SLEEP1 pin. If inserted, the signal is pulled low. If not inserted, the signal is pulled high.

LK_RESET In conjunction with LK_RESET/GPIO0, this link determines whether the RESET pin is controlled by the SDP or by the RESET link on the EVAL-AD7293SDZ. Position A: the pin is controlled by the SDP. Position B: the pin is controlled by the RESET push-button EVAL-AD7293SDZ (default).

LK_RESET/GPIO This link determines whether the signal coming from the SDP controls the RESET pin via LK_RESET or the GPIO0 pin.

Position A: The RESET pin is controlled by the SDP.

Position B: The GPIO pin is controlled by the SDP. LK_LDAC This link determines whether the GPIO7/LDAC pin is controlled by the SDP or by the LDAC link on the EVAL-AD7293SDZ.

Position A: the pin is controlled by the SDP. Position B: the pin is controlled by the LDAC link and pull-up on the EVAL-AD7293SDZ (default).

LDAC If Position B is selected on LK_LDAC, this link controls the polarity of the GPIO7/LDAC pin. If inserted, the signal is pulled low. If not inserted, the signal is pulled high.



















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CLOSED-LOOP CURRENT CONTROL The EVAL-AD7293SDZ has four independent closed-loop drain current controllers. By default, the control loops are populated on the EVAL-AD7293SDZ with all the necessary components, such as a sense resistor, and the closed-loop software window operates with a single loop (Loop 0).

LK_PAVDD supplies the voltage (8 V). This current flows through a PMOS switch controlled by the PA_ON pin.

The PMOS can be turned on and off by using the supplied evaluation software that allows the user to decide when current is supplied to the sense resistor high side.

LK_PMOS/RSO selects if PMOS circuitry is part of the loop.

The EVAL-AD7293SDZ contains a BSS159N depletion mode, low voltage transistor that mimics the characteristics of a higher power depletion mode PA but at lower voltages.

By default, the loops are connected to the BSS159N. R_0 and C_0 are populated with a resistor and a capacitor to form the filter with a time constant of 5 ms to 50 ms.

15 16 17 18 19 20 21 22 23 24 25 26 27 28

UN

I_VO

UT0

UN

I_VO

UT1

AG

ND

UN

I_VO

UT2

UN

I_VO

UT3

REF

INR

EFO

UT

AG

ND

BI_

VOU

T0B

I_VO

UT1

AVS

SD

AC

VDD

_BI

BI_

VOU

T2B

I_VO

UT3

56 55 54 53 52 51 50 49

GPO

I0G

PIO

1G

PIO

2/B

USY

GPI

O3/

ALE

RT0

D0+

D0–

D1+

D1–

48 47 46 45

VIN

0VI

N1

VIN

2VI

N3

44 43A

VDD

AG

ND

123456789

1011121314

FACTORY_TESTGPIO4/ALERT1GPIO5/SLEEP0GPIO6/SLEEP1

RESETGPIO7/LDAC

SCLKCS

DINDOUTDGND

VDRIVEDVDD

DACVDD_UNI

REFADCPAVDDPA_ONRS0+RS0–RS1+RS1–AGNDRS2+RS2–RS3+RS3–VCLAMP1VCLAMP2

4241403938373635343332313029

TOP VIEW(Not to Scale)

8mm × 8mm56-PIN LFCSP

BIVOUT0

GOLD PINFOR LPF

G

D

S

BSS159N ON BORDOR HPA OFF BOARD.

G0

GS

D

P-CHANNEL MOSFET

PMOS0+

RS0(+)

RS0(–)

PMOS0–

CURRENT FLOW

NOTES1. ANY CURRENT SENSE OR DAC OUTPUT CAN BE USED TO CLOSE THE LOOP.

SIMPLY MOVE EXTERNAL CABLES TO THE REQUIRED SMA. 1299

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Figure 4. EVAL-AD7293SDZ Loop Configuration

Table 4. PA_ON Link Options Link Mnemonic Description PMOS_S This link selects the source/supply of the PMOS switch. Position A: selects PMOS1+, Loop 1 (for the supply to be connected, LK_PMOS/RS1 must be in Position A). Position B: selects PMOS0+, Loop 0 (for the supply to be connected, LK_PMOS/RS0 must be in Position B) (default). LK_PMOS/RS3 This link selects the routing of the drain of the PMOS switch. Position A: selects the top of the high-side of the RS1(+) pin. Position B: selects the top of the high-side of the RS0(+) pin (default).






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Table 5. Loop Power Supply Options Link Mnemonic Description LK_PAVDD This link selects the supply for the PAVDD node on the EVAL-AD7293SDZ. Position A: selects the 5 V regulated supply coming from the ADP7104 voltage regulator (default). Position B: selects the external PAVDD (J2) located at the top of the board. LK_VPP0 This link selects the VPP0 supply for Loop 0 on the EVAL-AD7293SDZ. Position A: selects the 5 V regulated supply coming from the ADP7104 voltage regulator (default). Position B: selects the external VPP0 (J3) located at the top of the board. Position C: selects the PAVDD supply that is controlled by the LK_PAVDD. LK_PMOS/RS0 This link selects whether the PA_ON controller is part of Loop 0 or the user can connect directly to the top of the sense

resistor at the RS0(+) node. Position A: connects directly to the top of the RSENSE0 resistor at the RS0(+) node. Position B: PMOS0+ connects to the PA_ON control circuit (default). LK_VPP1 This link selects the VPP1 supply for Loop 1 on the EVAL-AD7293SDZ. Position A: selects the 5 V regulated supply coming from the ADP7104 voltage regulator (default). Position B: selects the external AVPP1 (J4) located at the top of the board. Position C: selects the PAVDD supply that is controlled by the LK_PAVDD link. LK_PMOS/RS1 This link selects whether the PA_ON controller is part of Loop 1 or the user can connect to the top of the sense resistor

at the RS1(+) node. Position A: PMOS1+ connects to the PA_ON control circuit. Position B: connects directly to the top of the RSENSE1 resistor at the RS1(+) node (default). LK_VPP2 This link selects the VPP supply for Loop 2 on the EVAL-AD7293SDZ. Position A: selects the 5 V regulated supply coming from the ADP7104 voltage regulator (default). Position B: selects the external VPP2 (J5) located at the top of the board. LK_VPP3 This link selects the VPP supply for Loop 3 on the EVAL-AD7293SDZ. Position A: selects the 5 V regulated supply coming from the ADP7104 voltage regulator (default). Position B: selects the external VPP3 (J6) located at the top of the board.

Table 6. Closed-Loop (EVAL-AD7293SDZ Closed-Loop Board) Current Control Transistor Options Link Mnemonic Description D_PA0 This link selects the drain connector to the BSS159N. Inserted: selects the bottom of the RS0(−) sense resistor. Not inserted: BSS159N drain not connected to Loop 0. G_PA0 This link selects the gate connector to the BIVOUT0 pin of the AD7293. Inserted: selects BSS159N (R_0 must be populated). Not inserted: BSS159N gate not connected to Loop 0. S_PA0 This link selects the connection to ground for the amplifier. Inserted: connects the BSS159N source to ground. Not inserted: BSS159N source not connected to Loop 0. D_PA1 This link selects the drain connector to the BSS159N. Inserted: selects the bottom of the RS1(−) sense resistor. Not inserted: BSS159N drain not connected to Loop 1. G_PA1 This link selects the gate connector to the BIVOUT1 pin of the AD7293. Inserted: selects BSS159N (R_1 must be populated). Not inserted: BSS159N gate not connected to Loop 1. S_PA1 This link selects the connection to ground for the amplifier. Inserted: connects the BSS159N source to ground. Not inserted: BSS159N gate not connected to Loop 1. D_PA2 This link selects the drain connector to the BSS159N. Inserted: selects the bottom of the RS2(−) sense resistor. Not inserted: BSS159N drain not connected to Loop 2. G_PA2 This link selects the gate connector to the BIVOUT2 pin of the AD7293. Inserted: selects BSS159N (R_2 must be populated). Not inserted: BSS159N gate not connected to Loop 2.
















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Link Mnemonic Description S_PA2 This link selects the connection to ground for the amplifier. Inserted: connects the BSS159N source to ground. Not inserted: BSS159N source not connected to Loop 2. D_PA3 This link selects the drain connector to the BSS159N. Inserted: selects the bottom of the RS3(−) sense resistor. Not inserted: BSS159N drain not connected to Loop 3. G_PA3 This link selects the gate connector to the BIVOUT3 pin of the AD7293. Inserted: selects BSS159N (R_3 must be populated). Not inserted: BSS159N gate not connected to Loop 3. S_PA3 This link selects the connection to ground for the amplifier. Inserted: connects the BSS159N source to ground. Not inserted: BSS159N source not connected to Loop 3.



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LK_PAVDDB

AD7293

PAVDD

PA_ON

RS0+

RS0–

RS1+

RS1–

RS2+

RS2–

RS3+

RS3–

J2(PAVDD)

J3(VPP0)

PAVDD

LK_VPP0

CBA

A

C A5V 5V 5V

A A

A

LK_PMOS/RS0

B

J4(VPP1)

VPP1

J4(VPP1)

VPP1

J4(VPP1)

VPP1

B

LK_PMOS/RS1

B

LK_PMOS/RS3B

PMOS_SB

D_PA0

G_PA0

S_PA0

D_PA1

G_PA1

S_PA1

AD_PA2

A

G_PA2

S_PA2

D_PA3A

G_PA3

S_PA3

LK_VPP2B

LK_VPP3B

BI_VOUT0

BI_VOUT1

BI_VOUT2

BI_VOUT3

5V5V

LK_VPP1

VPP0

A

A

A

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Figure 5. Loop Power Configuration Using On-Board BSS159 Depletion Mode Transistor (Loop 0 with High-Side PMOS Protection)


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LK_PAVDDB

J2 J3(VPP0)(PAVDD)

PAVDD

LK_VPP0 = DNP

LK_PMOS/RS3

RS0(+)

RS0(–)

PA_ON

BI_VOUT0

BI_VOUT1

BI_VOUT2

BI_VOUT3

RS1(+)

RS1(–)

RS2(+)

RS2(–)RS3(+)

RS3(–)

AD7293

PAVDD

PA_ON

RS0+

RS0–

RS1+

RS1–

RS2+

RS2–

RS3+

RS3–

BI_VOUT0

BI_VOUT1

BI_VOUT2

BI_VOUT3

5V

5V

BA

A

LK_PMOS/RS0

LK_VPP1

PMOS_S

B A

B A

LK_PMOS/RS1

VPP0

J4(VPP1)

VPP1

J5(VPP1)

VPP2

J6(VPP1)

VPP3

BC

5V

BA

BACA

D_PA0

G_PA0

S_PA0

D_PA1

G_PA1

S_PA1

D_PA1

G_PA2

D_PA3

G_PA3

S_PA3

5V LK_VPP2A B

5V LK_VPP3A B

Figure 6. Loop Power Configuration Connecting to External Power Amplifier


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ADC INPUT LINKS The EVAL-AD7293SDZ contains an ADC input channel, including the AD8022 amplifier, to buffer the inputs to the ADC. There are different options available that can be configured using the various links. See Figure 31 and Table 7 for more information.

EXTERNAL REFERENCE LINKS These links allow the user to select the on-board reference or an external reference.

TEMPERATURE SENSOR LINKS Three different options are available for use as the input to the AD7293 external temperature sensor:

• A 2NJ906 external diode • A 2NJ904 external diode (default) • The D0x or D1x SMB input

See Table 8 for information on how to configure the external temperature sensor using the various links.

Table 7. ADC Input Links Link Mnemonic Description LK_VIN0 Connects the noninverting input of the AD8022 and the VINO SMB to GND. SL-IN0 Selects the input to the VIN0 pin. Position A: output of the AD8022 op amp. Position B: VINO SMB. LK_VIN1 Connects the noninverting input of the AD8022 and the VIN1 SMB to GND. SL-IN1 Selects the input to the VIN1 pin. Position A: output of the AD8022 op amp. Position B: VIN1 SMB. LK_VIN2 Connects the noninverting input of the AD8022 and the VIN2 SMB to GND. SL-IN2 Selects the input to the VIN0 pin. Position A: output of the AD8022 op amp. Position B: VIN2 SMB. LK_VIN3 Connects the noninverting input of the AD8022 and the VIN3 SMB to GND. SL-IN3 Selects the input to the VIN0 pin. Position A: output of the AD8022 op amp. Position B: VIN3 SMB.

Table 8. Temperature Sensor Links Link Mnemonic Description SLK1 SLK1 and SLK2 determine the use of the D0x SMB, a 2NJ906 or a 2NJ904 external diode, as inputs to the external

temperature inputs, D0− and D0+, on the AD7293. Position A: 2NJ906. Position B: 2NJ904 (default). Position C: D0x SMB. SLK2 SLK1 and SLK2 determine the use of the D0x SMB, a 2NJ906, or a 2NJ904 external diode as inputs to the external

temperature inputs, D0− and D0+, on the AD7293. Position A: 2NJ906. Position B: 2NJ904 (default). Position C: D0x SMB. SLK3 SLK3 and SLK4 determine the use of the D1x SMB, a 2NJ906 or a 2NJ904 external diode, as inputs to the external

temperature inputs, D1− and D1+, on the AD7293. Position A: 2NJ906. Position B: 2NJ904 (default). Position C: D1x SMB. SLK4 SLK3 and SLK4 determine the use of the D1x SMB, a 2NJ906 or a 2NJ904 external diode, as inputs to the external

temperature inputs, D1− and D1+, on the AD7293. Position A: 2NJ906. Position B: 2NJ904 (default). Position C: D1x SMB.

















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Table 9. Default Link Positions for the EVAL-AD7293SDZ Link Mnemonic Description 5V_EXT Inserted 5V_REG Inserted LK_AVDD A LK_DVDD A LK_DVDD1 A D_PA0 Inserted D_PA1 Inserted D_PA2 Inserted D_PA3 Inserted G_PA0 Inserted G_PA1 Inserted G_PA2 Inserted G_PA3 Inserted LK_LDAC A LK_PAVDD A LK_PMOS/RS0 B LK_PMOS/RS1 B LK_PMOS/RS3 B LK_REF A LK_RESET B LK_RESET/GPIO B LK_SDP_PWR Inserted LK_SDP_VDRIVE Inserted LK_SLEEP0 A LK_SLEEP1 A S_PA0 Inserted S_PA1 Inserted S_PA2 Inserted S_PA3 Inserted LK_VCC A LK_VDRIVE A LK_VIN0 Inserted LK_VIN1 Inserted LK_VIN2 Inserted LK_VIN3 Inserted LK_VPP0 C LK_VPP1 B LK_VPP2 B LK_VPP3 B LK_VSS A PMOS_S B SL-IN0 A SL-IN1 A SL-IN2 A SL-IN3 A SLEEP0 Inserted SLEEP1 Inserted SLK1 B SLK2 B SLK3 B SLK4 B



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SOCKETS There are 23 SMB input/output sockets on the EVAL-AD7293SDZ that are relevant to the operation of the AD7293.

These sockets apply an externally generated signal to the EVAL-AD7293SDZ for connecting an external circuit to the EVAL-AD7293SDZ or for accessing an output signal from the AD7293.

Table 10. Socket Functions Socket Mnemonic Description RS0(+), RS1(+), RS2(+), RS3(+), RS0(−), RS1(−), RS2(−), RS3(−) Subminiature bayonet nut connector (BNC) sockets for the input signals applied

directly to the RSx+ and RSx− inputs in the absence of a sense resistor. VIN0, VIN1, VIN2, VIN3 Subminiature BNC sockets for the analog input signals applied directly to the

VIN0, VIN1, VIN2, and VIN3 pins, respectively. D0x, D1x Subminiature BNC sockets for the input signals applied directly to the AD7293

D0± and D1± pins. PA_ON Subminiature BNC sockets for the PA_ON output signal generated by the AD7293. UNI_VOUT0, UNI_VOUT1, UNI_VOUT2, UNI_VOUT3, BI_VOUT0, BI_VOUT1, BI_VOUT2, BI_VOUT3

Subminiature BNC sockets for the VOUTx output signals generated by the AD7293.













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GETTING STARTED INSTALLING THE SOFTWARE The EVAL-AD7293SDZ evaluation kit CD includes self installing software. The software is compatible with Windows® XP, Windows Vista, and Windows 7. Note that the EVAL-AD7293SDZ interfaces to the USB port of the PC via the EVAL-SDP-CB1Z.

To ensure that the EVAL-SDP-CB1Z is recognized when it connects to the PC, install the software before connecting the EVAL-SDP-CB1Z to the USB port of the PC.

1. Start the Windows operating system and insert the CD. 2. The installation software opens automatically. If it does not

open automatically, run the setup.exe file from the CD. Install the software as well as any drivers that are prompted.

3. After installation is complete, power up the EVAL-AD7293SDZ as described in the AD7293 Power Supply section.

4. Plug the EVAL-AD7293SDZ into the EVAL-SDP-CB1Z, and plug the EVAL-SDP-CB1Z into the PC using the USB cable included in the box.

5. To finalize the installation, proceed through any dialog boxes that appear when the software detects the EVAL-AD7293SDZ.

OPERATING THE SOFTWARE To run the AD7293 evaluation software, take the following steps:

1. From the Start menu, go to All Programs, Analog Devices, AD7293, and click AD7293 Evaluation Software. To uninstall the program, click Start, Control Panel, Add or Remove Programs, and then click AD7293 Evaluation Software.

2. Plug the USB cable into the EVAL-SDP-CB1Z, then plug the EVAL-SDP-CB1Z into the EVAL-AD7293SDZ and secure it using plastic screws (see Figure 7).

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Figure 7. EVAL-AD7293SDZ Connected to the EVAL-SDP-CB1Z

3. If the EVAL-SDP-CB1Z is not connected to the USB port when the software is launched, a connectivity error displays (see Figure 8). Plug the USB cable into the EVAL-SDP-CB1Z, then plug the EVAL-SDP-CB1Z into the EVAL-AD7293SDZ, wait a few seconds, click Rescan, and follow the instructions.

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Figure 8. Connectivity Error

4. If the EVAL-SDP-CB1Z is not connected to the EVAL-AD7293SDZ, a message box appears (see Figure 9). Check that the connection between the EVAL-SDP-CB1Z and the EVAL-AD7293SDZ, and run the program again.

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Figure 9. ERROR CONNECTION Window

5. If the EVAL-SDP-CB1Z is connected, the system development platform connects for a brief period.

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Figure 10. System Develop Platform Wait Window

6. The main window of the EVAL-AD7293SDZ then opens. 7. After installing the software, remove the CD from the disc

drive.


































Rev. 0 | of 40

VERIFYING THE LINKS AND POWERING UP THE EVALUATION BOARD Ensure that all links are positioned correctly for the chosen operating mode. Table 9 shows the position in which all links are set when the EVAL-AD7293SDZ is packaged.

When using an external power supply, follow these steps:

1. Ensure that all links are positioned correctly for the chosen operating mode.

2. Ensure that all relevant external power connections are made before using the software for the device.

3. Plug in the USB cable and the EVAL-SDP-CB1Z. If the supplied software is not used and all external supplies are used, this cable is not required.

4. Turn on the external power supply.

After powering up the EVAL-AD7293SDZ, begin using the software to evaluate the board. Note that the EVAL-AD7293SDZ must be repowered when the software window is closed; that is, the USB must be disconnected and reinserted.

EVALUATING THE BOARD The EVAL-AD7293SDZ software allows the user to load values to the eight DACs in the AD7293, read values from the ADC channels ,and then depict these values in a plot, monitor a signal between two limited values, and change the configuration of the device.








Rev. 0 | of 40

USING THE SOFTWARE AD7293 EVALUATION BOARD SOFTWARE WINDOW After following the procedures in the Getting Started section, the AD7293 Evaluation Board Software window, shown in Figure 11, appears when the evaluation software program is started. A number of different tabs are available to navigate through the various operating functions of the EVAL-AD7293SDZ. Click the relevant tab to select the various modes and configurations of the device.

The tabs offer the following options:

System View Hardware Pins ADC Monitoring Temperature Sensing Current Sensing DAC Control Closed Loop Access Register GPIOs/Alerts

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Figure 11. AD7293 Evaluation Board Software Window





Rev. 0 | of 40

HARDWARE PINS Four hardware pins are configurable from the Hardware Pins tab. The hardware pins are LDAC, RESET, SLEEP0, and SLEEP1. The links on the EVAL-AD7293SDZ must be configured as shown in Figure 12 to work accordingly.

LDAC and RESET are active low inputs. To use the pins, the user must set the corresponding switch to either high or low and then click Write to SDP.

Consult the AD7293 data sheet for more information on the function of the pins.

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Figure 12. Hardware Pins Tab




Rev. 0 | of 40

ADC MONITORING TAB To read the converted analog signals from the 4-channel ADC, click Sample in the ADC Monitoring tab of the main window. This tab allows the user to make single-ended measurements on the ADC channels.

The Continuous OFF/ON box allows the user to make continuous measurements in command mode. Within the

ADC Monitoring tab, use the Vin 0, Vin 1, Vin 2, and Vin 3 boxes to select the channel accessed. To read the converted data, click Sample to add one value at a time to a display box, or select Continuous OFF/ON to store the values in an array to draw the scope plot. Various user options are also available in this window, such as range settings and offset settings (see Figure 13).

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Figure 13. ADC Monitoring Tab


Rev. 0 | of 40

TEMPERATURE SENSING TAB To read the temperature from the AD7293, click Sample in the Temperature Sensing tab of the main window. The Continuous OFF/ON box allows the user to make continuous measurements in command mode. Within the Temperature Sensing tab, use the

Tsense 1, Tsense 2, and Tsense INT check boxes to select the channel accessed. To read the converted data, click Sample to add one value at a time to a display box, or select Continuous OFF/ON to store the values in an array to draw the scope plot. Tsense Offset Settings are also available in this tab.

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Figure 14. Temperature Sensing Tab



Rev. 0 | of 40

CURRENT SENSING TAB To read the converted analog signals from the four current sense channels, click Sample in the Current Sensing tab of the main window. The Continuous OFF/ON box allows the user to make continuous measurements in command mode. Checking the Isense 0 to Isense 3 boxes allows the user to select

which channel is accessed. There are two methods of reading the converted data: click Sample to add one value at a time to a display box, or click Continuous OFF/ON to store the values in an array to draw the scope plot. Various user options are also available in this window, such as ISENSE gain and offset settings (see Figure 15).

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Figure 15. Current Sensing Tab


Rev. 0 | of 40

DAC CONTROL TAB The DAC Control tab in the main window allows the user to select any of the eight DAC outputs and then load a value, using the DAC CODE box (see Figure 16). The write is dependent on the LDAC pin when LOAD is selected. If left unselected, the DAC loads when Write to DAC is clicked. If COPY is selected,

the value is copied to all relevant DAC channels (unipolar or bipolar depending on which DAC is selected).

Use the Enable Channels boxes to select which channels are enabled when Write to DAC is clicked.

To select the DAC output range setting, go to the drop-down menu in the relevant channel, make a selection, and then click DAC Offset Set.

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Figure 16. DAC Control Tab


Rev. 0 | of 40

CLOSED LOOP TAB Use the Closed Loop tab to control Loop 0 of the EVAL-AD7293SDZ. Use STEP 1A, STEP 1B, STEP 2, and STEP 3 (see Figure 17 and Figure 18) to set up the AD7293 for closed-loop operation:

STEP 1A allows the user to enable the loop. STEP 1B controls the external PMOS switch on the EVAL-

AD7293SDZ via the PA_ON circuitry on the AD7293. Check off the PA_ON state on/off? box to turn the supply to the top of the sense resistor on or off, allowing current to flow to the rest of the circuit.

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Figure 17. STEP 1B Tab

STEP 2 allows the user to write the target current by writing to the DAC register.

STEP 3 allows the user to enable Bipolar DAC 0, the DAC that controls the gate of the transistor in Loop 0.

The user can also program the target current and ramp time. Click MEASURE CURRENT, VOLTAGE & SET HIGH LIMIT to measure the current at the current sense input (see Figure 18). This button also measures the DAC output voltage and sets the high alert limit on the AD7293. Select the Continuous OFF/ON box to allow continuous measurements in command mode.

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Figure 18. Closed Loop Tab









Rev. 0 | of 40

AD7293 REGISTER INTERFACE WINDOW In the Access Registers tab, click Access All Registers to navigate to the AD7293 Register Interface window (see Figure 19). This window allows access to all registers.

In the left column, select the page under Page Selector. In the Register Selector column, select the register. Use the Register column (shown in the center of Figure 19) to select the data being written to the register. Enter the value in the text box directly under Register or click the relevant bit. Drop-down menus or text boxes appear when appropriate.

Click Write to perform a write to the register in use.

Click Read to read the register contents.

Click Reset to default to reset the register value to the software default. Note that clicking this does not write to the device.

Click Search to search for a phrase. For example, enter DAC to pull up all registers with DAC in the title.

The i icon displays further details on the function of the register.

Click Log>> to enlarge or shrink the window to include the Communications Log.

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Figure 19. AD7293 Register Interface Window





Rev. 0 | of 40

COMMUNICATIONS LOG The Communications Log panel allows the user to play patterns and display the writes or reads made to the device. Use the standard windows highlighting commands to repeat a pattern or a selection of writes and reads from the communications log. Figure 20 shows three items displayed in the communications log. Click Play Selection to play these patterns.

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Figure 20. Communications Log Before Clicking Play Selection

Figure 21 shows the Communications Log after clicking Play Selection.

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Figure 21. Communications Log After Clicking Play Selection

Click Save Selection to save the file. Use a .txt extension when saving the file (see Figure 20 and Figure 22).

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Figure 22. Save Selection Window

To play the sequence at a later point, click Comms Log from the drop-down menu and then click Play From File (see Figure 23). Select the saved file and click OK to play the previously saved pattern.

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Figure 23. Play Previously Saved Selection


Rev. 0 | of 40

GPIOs/ALERTS TAB Use the GPIOs/Alerts tab to control the pin functions of the EVAL-AD7293SDZ. See Figure 24 for the GPIOs/Alerts tab. Each pin has a dual function and is configurable by clicking the relevant button (for example, the GPIO0 button) in the top row. See the AD7293 data sheet for the pin functions. The INPUT/ OUTPUT button on the second row configures the pin for input or output. When INPUT is selected, the third row indicates the state of the pin. When OUTPUT is selected, the user can configure the output as low or high by clicking LOW/HIGH in the third row.

The fourth row of buttons decides the polarity (active high or active low) of the pin when the pin is not configured for GPIO. See Table 11 for a list of the available software configurations.

The user can set the upper and lower limits on the alerts listed. Enter the required limits, select the Enable box on the alert, and then click Write Alerts. To view the alerts status, click Read Alerts.

The alerts can also be routed to either the ALERT0 pin or the ALERT1 pin. Either the high or low limit or both limits on each alert can be configured to activate the relevant alert pin. Click the relevant limits to be routed, and then click Route Alerts to pins.

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ROW 1

ROW 2

ROW 3

ROW 4

Figure 24. GPIOs/Alerts Tab

Table 11. GPIO Configurations Function Row 1 Row 2 Row 3 Row 4 Input GPIO0, GPIO1, GPIO2, GPIO3,

GPIO4, GPIO5, GPIO6, GPIO7 INPUT LOW/HIGH (current pin) Not applicable

Output GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7

OUTPUT LOW/HIGH (output state) Not applicable

Alternate Function IS BLANK, CONVST, BUSY, ALERT0, ALERT1, SLEEP0, SLEEP1, LDAC

Not applicable LOW/HIGH (current pin) HIGH/LOW (active polarity)




Rev. 0 | of 40

EVALUATION BOARD SCHEMATICS AND ARTWORK

ALERT1, SLEEP0, SLEEP1, LDAC,GPIO3, GPIO2, GPIO1, GPIO0 (DEFAULTS)

KEEP R80 AS CLOSE TO DEVICE AS POSSIBLE

0Ω RESISTOR HERESLEE

P0

R23

10k

SLEE

P1

R20

10k

R1

10k

LDA

C

R8

10k

C23 4.7uF

C24

0.1u

F

EXT_

REF

2+VIN

4

GND

5TRIM

7COMP

6VOUT

U4ADR431BRZ

C250.1uF

+

C2610uF

R80

0r

14

RES

ET

R33

DNP

1 FACTORY_TEST2 GPIO4/ALERT13 GPIO5/SLEEP04 GPIO6/SLEEP15 /RESET6 GPIO7/LDAC7 SCLK8 /CS9 DIN

10 DOUT11 DGND12 VDRIVE13 DVDD

14DACVDD_UNI

15U

NI_

VOU

T016

UN

I_VO

UT1

17A

GN

D18

UN

I_VO

UT2

19U

NI_

VOU

T320

REF

IN21

REF

OU

T22

AG

ND

23B

I_VO

UT0

24B

I_VO

UT1

25A

VSS

26D

AC

VDD

_BI

27B

I_VO

UT2

28B

I_VO

UT3

29VCLAMP1

30VCLAMP0

31RS3-

32RS3+

33RS2-

34RS2+

35AGND

36RS1-

37RS1+

38RS0-

39RS0+

40PA_ON

41PAVDD

42REFADC

43A

GN

D

44A

VDD

45VI

N3

46VI

N2

47VI

N1

48VI

N0

49D

1-

50D

1+

51D

0-

52D

0+

53G

PIO

3/A

LER

T0

54G

PIO

2/B

USY

55G

PIO

1

56G

POI0

57 PADDLE

U1

AD7293BCPZ

C730.1uF

C750.1uF

C770.1uF

C79 0.1uF

C810.1uF

C830.1uF

C850.1uF

ABLK

_SLE

EP0

BA

LK_REF

AB

LK_S

LEEP

1

AB

LK_R

ESET

AB

LK_L

DA

C

C_PAVDD

R_PAVDDJ20-1

J20-2

J20-3

J20-4

J20-5

J20-6

J20-7

J20-8

J20-9

J20-10

J20-11

J20-12

J20-13

J20-14

J17-1

J17-2

J17-3

J17-4

J17-5

J17-6

J17-7

J17-8

J17-9

J17-10

J17-11

J17-12

J17-13

J17-14

J18-

1

J18-

2

J18-

3

J18-

4

J18-

5

J18-

6

J18-

7

J18-

8

J18-

9

J18-

10

J18-

11

J18-

12

J18-

13

J18-

14

J19-1

J19-2

J19-3

J19-4

J19-5

J19-6

J19-7

J19-8

J19-9

J19-10

J19-11

J19-12

J19-13

J19-14

/CS

SCLK

DIN

PA_ON

RS0(+)

RS0(-)

RS1(-)

VDRIVE

GPI

O6

DVDD

DACVDD_UNI

AVSS

VDD

PAVDD

VDD

UNI_VOUT0

UNI_VOUT1

UNI_VOUT2

UNI_VOUT3

BI_VOUT0

BI_VOUT1

BI_VOUT2

BI_VOUT3

VDD

RS1(+)

RS2(+)

RS2(-)

RS3(+)

RS3(-)

D1-

D1+

D0-

D0+ VIN

0

VIN

1

VIN

2

VIN

3

2.5V_REF

VCLAMP0

VCLAMP1

AVSS

GPI

O3

GPI

O2

GPI

O1

GPI

O0

GPI

O4

RES

ET

DOUT

VDRIVE

GPI

O5

GPI

O7

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Figure 25. EVAL-AD7293SDZ Schematic, AD7293 Block




Rev. 0 | of 40

Board ID EEPROM (24LC32) must be on I2C bus 0.

LK_SDP_PWR

+ C36

10uF

C37

0.1uF

LK_SDP_VDRIVE

*NC on BLACKFIN SDP

****

****

*

**

**

TIMERS

INPUT/OUTPUTGENERAL

I2C

SPI

SPORT

PORTPARALLEL

SDPSTANDARD

CONNECTOR

120NC119NC118GND117GND116VIO(+3.3V)115GND114PAR_D22113PAR_D20112PAR_D18111PAR_D16110PAR_D15109GND108PAR_D12107PAR_D10106PAR_D8105PAR_D6104GND103PAR_D4102PAR_D2101PAR_D0100PAR_WR99PAR_INT98GND97PAR_A296PAR_A095PAR_FS294PAR_CLK93GND92SPORT_RSCLK91SPORT_DR090SPORT_RFS89SPORT_TFS88SPORT_DT087SPORT_TSCLK86GND85SPI_SEL_A84SPI_MOSI83SPI_MISO82SPI_CLK81GND80SDA_079SCL_078GPIO177GPIO376GPIO575GND74GPIO773TMR_B72TMR_D71NC70NC69GND68NC67NC66NC65NC64NC63GND62UART_TX61BMODE160 RESET_IN59 UART_RX58 GND57 NC56 NC55 NC54 NC53 NC52 GND51 NC50 NC49 TMR_C48 TMR_A47 GPIO646 GND45 GPIO444 GPIO243 GPIO042 SCL_141 SDA_140 GND39 SPI_SEL1/SPI_SS38 SPI_SEL_C37 SPI_SEL_B36 GND35 SPORT_INT34 SPORT_DT333 SPORT_DT232 SPORT_DT131 SPORT_DR130 SPORT_DR229 SPORT_DR328 GND27 PAR_FS126 PAR_FS325 PAR_A124 PAR_A323 GND22 PAR_CS21 PAR_RD20 PAR_D119 PAR_D318 PAR_D517 GND16 PAR_D715 PAR_D914 PAR_D1113 PAR_D1312 PAR_D1411 GND10 PAR_D179 PAR_D198 PAR_D217 PAR_D236 GND5 USB_VBUS4 GND3 GND2 NC1 VIN

J7

SCLK

DOUT DIN /CS

AGND

1 A02 A13 A24 VSS

8VCC 7WP 6SCL 5SDA

U7

24LC32

R39 DNP

R42 100k

R79 100k

R84 0r

R85 0r

R86

0r

R87

0r

R88 0r

R89 0r

R90 0r

R91 0r

R94 0r

R95 0r

R96 0r

R97 0r

AGND1 AGND2 AGND3 AGND4ABLK_RESET/GPIO

J8-1

Harwin

CO

NN

ECTO

R, H

EAD

ER, T

HT,

2.5

4MM

, 36W

AY

(cut

to 1

4-pi

n)

M20-9993646

J8-2J8-3J8-4J8-5J8-6J8-7J8-8J8-9

J8-10J8-11J8-12J8-13J8-14

SDA_SDPSCL_SDP

+5V

+3.3V

SCLK

DOUT

DIN

/CS

GPIO2

GPIO4

GPIO1

GPIO3

GPIO5

GPIO6

GPIO7

VDRIVEVDRIVE

GPIO0/RESET

/CSDINDOUTSCLK

SCL_SDPSDA_SDP

GPIO0/RESETGPIO1GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7

GPIO0RESET

DVDD

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4

NOTES1. CARE MUST BE TAKEN TO ENSURE DAUGHTER BOARD I2C

EEPROM ADDRESS IS NOT 0x50 OR 0x51. THIS IS TO ENSURETHE I2C ADDRESS RANGE DOES NOT OVERLAP THAT OF THEEI3 BREAK-OUT BOARD.

Figure 26. EVAL-AD7293SDZ Schematic, SDP Connector Block



Rev. 0 | of 40

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5

PWR 7-9V

SCREW BLOCK FOR POWER

KEEP JUMPERS IN A LINE FOR EASE OF PLACMENT

VDRIVEFOR DRAIN VOLTAGES HIGHER THAN 20V IT IS RECOMMENDEDTO TIE PAVDD TO VDD AND SCALE THE CONTROL SIGNAL EXTERNALLY.

PWR 4V to 20V

PWR 4.5V to 12.5V

1VOUT

2SENSE

3GND

4N/C

5 EN/UVLO

6GND

7PG

8 VIN

9EP

U10

ADP7104ARDZ-5.0

R9

100kR6

100k

R7100k

J9-1

J9-2

VDD

J1-1

J1-2

VDAC

J13-1

J13-2

J12-1

J12-2

J12-3

J12-4

J11-1

J11-2

J14-1

J14-2

DVDD

J10-1

J10-2

J2-1

J2-2

BA

LK_AVDD

BA

LK_VDRIVEVDRIVE

BA

LK_VCC

BA

LK_VSS

BA

LK_PAVDD

+ C48

10uF +C1110uF

L9

600 ohms @ 100MHz

5V_REG_STATUS

POWER

R83

2k

+ C55

10uF

+ C2

10uF

+ C1210uF

+ C57

10uFC580.1uF

C590.1uF

C600.1uF

C620.1uF

C630.1uF C56

0.1uF

BA

LK_D

VDD

AVSS

PAVDD

+ C70

10uF

C710.1uF

+ C9

10uFC61

0.1uF

D3

5V_REG

5V_EXT

PWR

+5V

VDD

EXT_VDD

+5V

EXT_AVCC

PWR

+3.3V

DACVDD_UNI

EXT_VSS AVSS

+5V

EXT_DVDD

DVDD

EXT_PADD

PAVDD

VDRIVE

+5V

-5V

+5V

Figure 27. EVAL-AD7293SDZ Schematic, Power Supply Block



Rev. 0 | of 40

HIGH POWER INPUTS THAT CAN CARRY A LOT OF CURRENT

+ C6510uF

C660.1uF

+C6810uF

R82

30k

C690.1uF

1 CP+

2GND

3 CP-

4 SD

5SENSE

6NC

7VOUT8 VIN

U3

ADP3605ARZ

+ C6410uF

J3-1

J3-2

J4-1

J4-2

J5-1

J5-2

J6-1

J6-2

C

B A LK_VPP0

C

B A

LK_VPP1

AB

LK_P

MO

S/R

S0A

BLK

_PM

OS/

RS1

AB

LK_V

PP2

AB

LK_V

PP3

R18

1k6

C200.1uF + C21

10uF

-5V_REG_STATUS

L10

600 ohms @ 100MHz

BLM31AJ601SN1L

+5V

-5V

AGND

AGND

+5V

RS2(+)

+5V

+5V

+5V

VPP0

VPP1

RS3(+)

PAVDD

VPP0

PMOS0+

RS0(+)

VPP1RS1(+)

PMOS1+

PAVDD

EXT_VPP0

EXT_VPP1

EXT_VPP2

EXT_VPP3

1299

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Figure 28. EVAL-AD7293SDZ Schematic, VPP and Negative Power Supply Block



Rev. 0 | of 40

INSERT AN OP AMP TO ALLOW FOR INPUT SIGNAL CONDITIONING

UNI_VOUT0

UNI_VOUT1 UNI_VOUT2

UNI_VOUT3

RS3(+) RS3(-)

RS0(+) RS0(-)

RS1(+) RS1(-)

RS2(+) RS2(-)R2

0rC3DNP

C4DNP

C5DNP

C6DNP

R3

0r

R4

0r

R5

0r

UNIVOUT0 UNIVOUT3

UNIVOUT1 UNIVOUT2 RS1(-)RS1(+)

RS2(-)RS2(+)

L1

DNP

+ C39

DN

P+

C40 DNP

+

C41 DNP

+ C42DNP

+

C43

DNP

+

C44

DNP

L2

DNP

L4

DNP

L3

DNP

RS0(-)RS0(+)

L5

DNP

+ C14DNP

+

C15 DNP

+

C16 DNP

L6

DNP

RS3(-)RS3(+)

+ C17DNP

+

C18

DNP

+

C19

DNP

L7

DNP

L8

DNP

RSENSE0

100r

R35 0r

R12 0r

R15 0r

R36 0r

R10 0r

R11 0r

R13 0r

R14 0r

RSENSE1

100r

RSENSE2

100r

RSENSE3

100r

UNI_VOUT0 UNI_VOUT3

UNI_VOUT1 UNI_VOUT2 RS2(+)

RS2(-)

RS1(-)

RS1(+)

RS0(-)

RS0(+)

RS3(+)

RS3(-)

1299

8-02

7

Figure 29. EVAL-AD7293SDZ Schematic, Current Sensors Block

E

B

C

Q8

2N3904

+ C1DNP

R24

100r

R31

100r

C2810pF

E

B

C

Q32N3906

E

B

C

Q4

2N3904

+ C27DNP

R34

100r

R37

100r

C29

10pF

E

B

C

Q52N3906

D(0) D(1)

A B C

SLK

4

A B C

SLK

1

A B C

SLK

2

A B C

SLK

3

D0- D0+D1-

D1+ 1299

8-02

8

Figure 30. EVAL-AD7293SDZ Schematic, Temperature Sensors Block




Rev. 0 | of 40

R25

510r

R26

51r

LK_VIN1

C71nF

R28

22rC8DNP

R38 1k

R43 DN

P

C10 10pF

3 +

2 - 1

U5-A

AD8022ARMZVIN1

R27

510R

R44

51r

LK_VIN3

C131nF

R45

22rC30DNP

R46 1k

R47 DN

P

C31 10pF

VIN3

R48

510R

R49

51r

LK_VIN0

C321nF

BA

SL-IN0R50

22rC33DNP

R51 1k

R52

DNP

C34 10pF

VIN0

R53

510R

R54

51r

LK_VIN2

C351nF

R55

22rC38DNP

R56 1k

R57 DN

P

C45 10pF

VIN2

8

V+

4

V-U5-C C460.1uF

C470.1uF

BUFF_VIN1

BUFF_VIN3

BUFF_VIN0

BUFF_VIN2

8

V+

4

V-U6-C

5 +

6 - 7

U5-B

AD8022ARMZ

3 +

2 - 1

U6-A

AD8022ARMZ

5 +

6 - 7

U6-B

AD8022ARMZ

BA

SL-IN2

BA

SL-IN1

BA

SL-IN3

VIN1

VIN3

VIN0

VIN2

AVSS

VDD

AVSS

VDD 1299

8-02

9

Figure 31. EVAL-AD7293SDZ Schematic, ADC Inputs Block

C22DNP R21

DNP

C541nF

S

G

D

U2

SO8NB

BA

PMOS_S

BA

LK_PMOS/RS3

PA_O

N

R19

0rPA_ON

RS0(+)

PMOS0+

PMOS1+

RS1(+)

1299

8-03

0

Figure 32. EVAL-AD7293SDZ Schematic, PMOS Switch Controlled by PA_ON Block




Rev. 0 | of 40

1299

8-03

1

GOLD PINS

BI_VOUT0

R0

C0

G_0

R1030r

BI_VOUT0 G0

Figure 33. EVAL-AD7293SDZ Schematic, BI_VOUT0 Filter Block

GOLD PINS

BI_VOUT1

R1

C1

G_1

R1050r

BI_VOUT1 G1

1299

8-03

2


12

998-

033

GOLD PINS

BI_VOUT2

R2

C2

G_2

R1060r

BI_VOUT2 G2


GOLD PINS

BI_VOUT3

R3

C3

G_3

R1040r

BI_VOUT3 G3

1299

8-03

4







Rev. 0 | of 40

ENABLE

DISABLE

ENABLE

DISABLE

NO REF BUFFER NEEDED AS REF CAPABLE OF SUPPLYING 30mA, 2.5/160k= 15uA.

THESE DIGITAL POTENTIOMETERS HAVE NONVOLATILE MEMORY. CAN BE PROGRAMMED TO DESIRED VALUE USING NVM PUSH BUTTONS.

1 4

PU

D4

RED

R58 1k8

1 4

NVM

R59 110k

R60 110k

1 4

PD

1VDD

2 A

3W

4 B

5GND

6PD

7PU

8ASE

9EP

U8

AD5116BCPZ80

R61

750r

R62

12r

C50

0.1uF

1 4

PU1

D5

RED

R63 1k8

1 4

NVM1

R64 110k

R65 110k

1 4

PD1

1VDD

2 A

3W

4 B

5GND

6PD

7PU

8ASE

9EP

U11

AD5116BCPZ80

R66

750r

R67

12r

C51

0.1uF

VCLAMP0

VCLAMP1

AB

LK_ASE

AB

LK_ASE1

1

2V-

3IN+

4IN-

5PD

6V+

U9

ADA4860-1YRJZ

1

2V-

3IN+

4IN-

5PD

6V+

U12

ADA4860-1YRJZ

+

C88 10uF

C89 0.1uF

+

C86 10uF

C87 0.1uF

VDD

VDD

VDD

VDD

AGND

VDD

2.5V_REF

VCLAMP0

VDD

VDD

VDD

VDD

AGND

VDD

2.5V_REF

VCLAMP1

1299

8-03

5

Figure 37. EVAL-AD7293SDZ Schematic, VCLAMP Input Voltage Block

NOTES1. R16, R17, R40, R41, R81, R92, R93, AND R101 ARE OPTIONAL 0Ω SHORTS (NOT NORMALLY INSERTED).

1 ENABLE-A

2 A1 3YB44 A2 5YB36 A3 7YB28 A4 9YB1

10GND

11 B112YA4

13 B214YA3

15 B316YA2

17 B418YA1

19ENABLE-B

20VCC

U13

MC74HC244ADTG

D0 R102 2k

D1 R71 2k

D2 R72 2k

D6 R73 2k

D7 R74 2k

D8 R75 2k

D9 R76 2k

D10 R77 2k

C49 0.1uF

R78

10k

R98

10kR99

10k

R100

10k

R16 DNPR17 DNPR40 DNPR41 DNPR81 DNPR92 DNPR93 DNP

R101 DNP

R70

AB

LK_D

VDD

1

R22 1M R29 1MR30 1M

VDRIVE

GPIO0GPIO1GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7

DVDD

1299

8-03

6

Figure 38. EVAL-AD7293SDZ Schematic, LED Indicator Block




Rev. 0 | of 40

1299

8-03

7

Figure 39. EVAL-AD7293SDZ Evaluation Board Layout, Component Side View

1299

8-03

8

Figure 40. EVAL-AD7293SDZ Evaluation Board Layout, Silkscreen View




Rev. 0 | of 40

1299

8-03

9

Figure 41. EVAL-AD7293SDZ Evaluation Board Layout, Solder Side View

1299

8-04

0

Figure 42. EVAL-AD7293SDZ Daughter Board Layout, Component Side View




Rev. 0 | of 40

1299

8-04

1

Figure 43. EVAL-AD7293SDZ Daughter Board Layout, Silkscreen View

1299

8-04

2

Figure 44. EVAL-AD7293SDZ Daughter Board Layout, Solder Side View




Rev. 0 | of 40

ORDERING INFORMATION BILL OF MATERIALS

Table 12. Daughter Board Bill of Materials Reference Designator Description Manufacturer Part Number AGND1 to AGND4 Red test point Farnell Electronics, Inc. 8731144 C_0 to C_3, D_0 to D_3, R_0 to R_3 Socket pin, PCB, PK100 (two pins only) Farnell Electronics 329563 D_PA0 to D_PA3, G_PA0 to G_PA3, S_PA0 to S_PA3

2-pin (0.1 inch pitch) header and shorting shunt Farnell Electronics 1022247, 150411

G_0 to G_3 Black test point Farnell Electronics 8731128 J1 Header, 26-pin (2 × 13), 2 mm pitch SMD Digi-Key SAM1167-13-ND J2 Receptacle, 26-pin (2 × 13), 2 mm pitch SMD Digi-Key MMS-113-02-L-DV-P-ND Q0 to Q3 MOSFET, N, depletion mode Farnell Electronics 1471702

Table 13. Evaluation Board Bill of Materials Reference Designator Description Manufacturer Part Number −5V_REG_STATUS, /CS, 5V_REG_STATUS, AGND, AGND1 to AGND4, BUFF_VIN0 to BUFF_VIN3, DIN, DOUT, SCLK

Red test points Farnell Electronics 8731144

5V_EXT, 5V_REG, LDAC, LK_SDP_PWR, LK_SDP_VDRIVE, LK_VIN0 to LK_VIN3

2-pin (0.1 inch pitch) headers and shorting shunts

Farnell Electronics 1022247, 150411

AVSS, DVDD, G_0 to G_3, PAVDD, VCLAMP0 to VCLAMP1, VDAC, VDD, VDRIVE

Black test points Farnell Electronics 8731128

BI_VOUT0 to BI_VOUT3, PA_ON, RS0(+)/RS0(−) to RS3(+)/RS3(−), UNIVOUT0 to UNIVOUT3

50 W, gold plated PCB, SMA jacks Farnell Electronics 1248990

C1, C3 to C6, C8, C14 to C19, C22, C27, C30, C33, C38 to C44, L1 to L8, R16, R17, R21, R33, R39 to R41, R43, R47, R52, R57, R81, R92, R93, R101

Do not insert Do not insert

C2, C11, C12, C21, C26, C36, C48, C55, C57, C64, C65, C68, C70, C86, C88

Capacitors, Case A, 10 µF, 10 V Farnell Electronics 197130

C7, C13 ,C32, C35 50 V, X7R, multilayer ceramic capacitors Farnell Electronics 9406174 C9 Capacitors, Case D, 10 µF, 50 V Farnell Electronics 2250169 C10, C28, C29, C31, C34, C45 50 V, NPO, multilayer ceramic capacitors Farnell Electronics 499110 C23 Capacitors, MLCC, X7R, 4.7 µF, 50 V, 1206 Farnell Electronics 1908177 C20, C24, C25, C37, C46, C47, C49 to C51, C58 to C60, C56, C62, C63, C66, C69, C71, C73, C75, C77, C79, C81, C83, C87, C89

Capacitors, 0603, 0.1 µF, 16 V, X7R Farnell Electronics 9406140

C54 50 V, X7R, multilayer ceramic capacitors Farnell Electronics 1759337 C61, C85 Capacitors, 0603, 0.1 µF, 100 V, X7R Farnell Electronics 1828921 C_0 to C_3, C_PAVDD, R_0 to R_3, R_PAVDD Socket pins, PCB, PK100 (two pins only) Farnell Electronics 329563 D0x, D1x, VIN0 to VIN3 50 W, gold plated PCB, SMB jacks Farnell Electronics 1206013 D0 to D2, D6 to D10, POWER Red SMD LEDs Farnell Electronics 5790840 D3 Diode, Schottky, 30 V, 200 mA, 0603 Farnell Electronics 2211954 D4, D5 Red SMD LEDs Farnell Electronics 1685068 EXT_REF 50 W, gold plated PCB, SMB jacks Do not insert Do not insert J1 to J6, J9 to J11, J13, J14 2-pin terminal blocks (5 mm pitch) Farnell Electronics 151789 J7 120-way connector, 0.6 mm pitch Farnell Electronics 1324660 J8 Connector, header, THT, 2.54 mm, 36-way

(cut to 14-pin) Farnell Electronics 1022264

J12 DC power connectors, 2 mm SMT power jack Mouser Electronics 806-KLDX-SMT20202A J15 Receptacle, 26-pin, (2 × 13) 2 mm pitch SMD Digi-Key MMS-113-02-L-DV-P-ND J16 Header, 26-pin, (2 × 13), 2 mm pitch SMD Digi-Key SAM1167-13-ND J17 to J20 14-pin SIL headers, 2 mm pitch Digi-Key M22-2011405-ND L9, L10 Inductor, SMD, 600Z Farnell Electronics 9526862


Rev. 0 | of 40

Reference Designator Description Manufacturer Part Number LK_ASE, LK_ASE1, LK_REF 2-way solder links (use 0 Ω, 0603 resistors) Farnell Electronics 9331662 LK_AVDD, LK_DVDD, LK_DVDD1, LK_LDAC, LK_PAVDD, LK_PMOS/RS0, LK_PMOS/RS1, LK_PMOS/RS3, LK_RESET, LK_RESET/GPIO, LK_SLEEP0, LK_SLEEP1, LK_VCC, LK_VDRIVE, LK_VPP2, LK_VPP3, LK_VSS, PMOS_S

3-pin SIL headers and shorting links Farnell Electronics 1022248, 150410

LK_VPP0, LK_VPP1 4-pin (3 + 1) headers (cut to size) and shorting links

Farnell Electronics 1022264, 150410

NVM, NVM1, PD, PD1, PU, PU1, RESET SMD push button switches (sealed 6 mm × 6 mm)

Farnell Electronics 177807

Q3, Q5 Transistors, 45 V, 200 mA, PNP, TO-92 Farnell Electronics 1574372 Q4, Q8 Transistors, NPN, 40 V, 200 mA, TO-92 Farnell Electronics 9846743 R1, R8, R20, R23 Resistors, 10 kΩ, 0.063 W, 1%, 0603 Farnell Electronics 9330399 R2 to R5, R9, R10 to R15, R19, R35, R36, R103 to R106, SL-IN0 to SL-IN3, SLK1 to SLK4

Resistors, 0603, 1%, 0 Ω Farnell Electronics 9331662

R6, R7, R42, R79 Resistors, 100 kΩ, 0.063 W, 1%, 0603 Farnell Electronics 9330402 R18 Resistor, 1.6 kΩ, 0.1 W, 1%, 0805 Farnell Electronics 9332669 R22, R29, R30 Resistors, 1 MΩ, 0.1 W, 1%, 0805 Farnell Electronics 9332413 R24, R31, R34, R37 Resistors, 100 Ω, 0.063 W, 1%, 0603 Farnell Electronics 9330364 R25, R27, R48, R53 Resistors, 510 Ω, 0.063 W, 1%, 0603 Farnell Electronics 9331298 R26, R44, R49, R54 Resistors, 51 Ω, 0.063 W, 1%, 0603 Farnell Electronics 9331336 R28 R45, R50, R55 Resistors, 22 Ω, 0.063 W, 1%, 0603 Farnell Electronics 9330844 R38, R46, R51, R56 Resistors, 1 kΩ, 0.063 W, 1%, 0603 Farnell Electronics 9330380 R58, R63 Resistors, 1.8 kΩ, 0.1 W, 1%, 0805 Farnell Electronics 9332715 R59, R60, R64, R65 Resistors, 110 kΩ, 0.063 W, 1%, 0603 Farnell Electronics 9330461 R61, R66 Resistors, 750 Ω, 0.063 W, 1%, 0603 Farnell Electronics 9331506 R62, R67 Resistors, 12 Ω, 0.063 W, 1%, 0603 Farnell Electronics 9330534 R70, R78, R98 to R100 Resistors, 10 kΩ, 0.1 W, 1%, 0805 Farnell Electronics 9332391 R71 to R77, R83, R102 Resistors, 2 kΩ, 0.063 W, 1%, 0603 Farnell Electronics 9330763 R80, R84 to R91, R94 to R97 Resistors, 0402, 1%, 0 Ω Farnell Electronics 1357983 R82 Resistor, 30 kΩ, 0.1 W, 1%, 0805 Farnell Electronics 9333002 RSENSE0 to RSENSE3 Resistors thin film, 100 Ω, 0.1%, 2512 Farnell Electronics 2325372 SLEEP0, SLEEP1 2-pin (0.1-inch pitch) headers and shorting

shunts Farnell Electronics 1022247, FEC 150411

U1 AD7293BCPZ Analog Devices, Inc. AD7293BCPZ U2 MOSFET P-CH, 30 V, 8.1 A, SOIC8 Farnell Electronics 1858951 U3 120 mA switched capacitor voltage inverter

with regulated output Analog Devices ADP3605ARZ-R7

U4 Ultralow noise XFET voltage reference Analog Devices ADR431BRZ U5, U6 Dual op amps Analog Devices AD8022ARMZ U7 32 kb, I2C serial EEPROM Farnell Electronics 1331330 U8, U11 Digital potentiometers, 64 taps, 8% resistor

tolerance Analog Devices AD5116BCPZ80-500R7

U9, U12 Precision rail-to-rail op amps Analog Devices ADA4860-1YRJZ U10 Linear regulator 5 V, 20 V, 500 mA, ultralow

noise, CMOS Analog Devices ADP7104ARDZ-5.0-R7

U13 74 HC CMOS, SMD, 74HC244, TSSOP20 Farnell Electronics 1104721




http://www.analog.com/ADR431?doc=EVAL-AD7293SDZ-UG-817.pdf



http://www.analog.com/ADA4860-1?doc=EVAL-AD7293SDZ-UG-817.pdf



Rev. 0 | of 40

NOTES

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

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