euv mask process development

EUV Mask Workshop 2004 1

Challenges of EUV masks and preliminary evaluation

Naoya HayashiElectronic Device LaboratoryDai Nippon Printing Co.,Ltd.


Contents• Recent Lithography Options on Roadmap • Challenges for EUV Mask

– Multi Layer Substrates– Defect Free Mask

• Absorber Delineation (Writing Tools & Processes)• Inspection & Repair• Metrology

– With Preliminary Results

• Summary


Technology Node

2007 2013 20192004 20162010

hp90 hp65 hp32 hp16hp22hp45

2003 2005 2006 2008 2009 2011 2012 2014 2015 2017 2018

Research Required Development Underway Qualification/Pre-Production Continuous Improvement

This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.

DRAM Half-pitch(dense lines)

Tech

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t Tec

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ogy

Nod

es(D

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M H

alf-P

itch,

nm

)90 193 nm

65 Narrowoptions

193nm + LFD193nm immersionPEL

32EUV193nm immersion + LFD157nm immersion + LFD, ML2Imprint

Narrowoptions

22 Narrowoptions

EUVInnovative 157nm or 193 nm immersionML2Imprint, innovative technology

16 Narrowoptions

Innovative technologyML2, EUV + RET, imprint

45193nm immersion + LFDEUVML2, 157nm immersion, PEL

Narrowoptions

Potential Lithography Solutions


65nm-45nm node lithography/mask options 193nm extension (RET from mask side)

• Aggressive OPC (ie Scattering Bar of 100nm width) will be inevitable.• High transmission att-PSM (both embedded shifter type and CLM) with “tritone” feature is thought as a possible option.• Aggressive Alt-PSM adoption..

193nm immersion lithography• There is no major mask related issue for immersion lithography.• RET will be accelerated.• 157nm Dry and/or Immersion will be the backup for 45nm and beyond.

Electron beam lithography• LEEPL technology has been focusing on hole pattern for memory devices.• Image placement measurement, defect Inspection/repair, are still in development stage.

EUV lithography• Research & Development for production engineering is required.• Especially, defect-free multi layer substrate, inspection/repair, are critical issues.


Current Status and Schedule for EUV Mask Development

• Current Status– Through research activity with consortia, trying to

define EUV mask specifications• Absorber, buffer/capping layer materials• Patterning processes• Printable defects, inspection, metrology, etc.

– Starting to provide evaluation plate 2004/H2.– Multilayer substrate will be available from several

vendors.• Future Plan

– Investment for production will start 2006


EUVL mask stacking structure

Absorber layer(s)

Buffer layer

Capping layer

Multilayer (about 40 pairs of Mo and Si)

Underlayer

LTEM

Conductive coating


EUVL blank initial test results•Tantalum based absorber on Chromium based buffer•Etching capability test of 200nm patterns

•Repair capability test with Micromachining

Hole Iso-Space

Iso-Line L&S

Defect size 160nm

Ref

eren

ceA

fter r

epai

r

•Currently, several sets of materials from various blank suppliers are tested to investigate their capability as absorber and buffer.


Cross section profile of TaGeN

Dense hole Isolate lineDense line

CF4 gas process

Cl2 gas process

Pattern size 200nm

•Vertical side wall were obtained in both gas process

courtesy by ASET


Etch bias uniformityExposure tool : 50kV EB Measurement tool : CD-SEMArea size : 122 X 122 mm2 Pattern : 400 nm Iso-Space

+5nm -5nmCF4 process Cl2 process

Mean : -27.3nmMax : -21.62nmMin : -33.71nm3sigma : 8.36nm

Mean : 2.05nmMax : 9.31nmMin : -4.31nm

3sigma : 9.95nm


EUV mask reflectivity

0

10

20

30

40

50

60

70

12.5 13 13.5 14 14.5Wavelength [nm]

Ref

lect

ivity

[%]

•Centroid wavelength : 13.54nm•Peak reflectivity : 63.8%

EUV reflectivity after buffer layer dry etchingAbsorber layer : CF4 gas process

Buffer layer : Cl2 + O2 gas process

courtesy by ASET


EUV mask pattern and wafer print result70nm line and space pattern

Mask pattern Wafer pattern( Exposure tool : HiNA set 3)

5um 1um

courtesy by ASET and Nikon


Availability of mask infrastructures


Mask Writing SystemsVendor Systems

Etec Systems MEBES-RSB

Etec Systems ALTA-4000

JEOL JBX-3030

Hitachi HT HL-7000M

Nu Flare EBM-4000

Writing Strategy

Variable Shaped E-Beam

Raster Scan

Spot Multi-Laser-Beam

Raster Scan


Vector Scan


Vector Scan


Vector Scan Accelerating Voltage

50KeV (257nm) 50KeV 50KeV 50KeV

Max.Substrate Size

6 inch sq. 6 inch sq. 7 inch sq. 7 inch sq. 230mm sq.

Writing Area - 144 x 144 mm - 7 inch x 7 inch 222 x 228.6 mm

Min.Feature Size

0.20 um 0.35 um - 0.10 um 0.25 um

Min.Addressing 1.0 nm 2.5 nm 1.0 nm 1.0 nm 1.0 nm

Pattern Position Accuracy

12 nm(3σ) 22 nm(3σ) 15 nm(Max.) 15 nm(3σ) 12 nm(3σ)

Overlay Accuracy

8 nm(3σ) 15 nm(3σ) - - 10 nm(3σ)

Butting Error 10 nm(Mean+R/2) 10 nm (Mean+R/2) 15 nm(Max.) 10 nm(Mean+3σ) -

CD Accuracy (Global Unif.)

7 nm ( 3σ) 12 nm (Range/2) 8 nm(3σ) 8 nm(3σ) 7 nm(3σ)

Remarks 2 Pass Writing 4 Pass Writing 2 Pass Writing 2 Pass Writing 4 Pass Writing


Resist material vs. Resolution•Resist SEM Image (minimum resolution)

CAR_A100nm

40nm

70nm

90nm

Isolated space

40nm

55nm

65nm

CAR_B100nm

80nm 35nm

75nm

65nm

Non-CAR_A300nm

Dense space 100nm

Hole

120nm

ResistThickness

CAR_A400nm


Mask Inspection Systems

Syetem MD3000 LM7000 LM7000B SLF87KLA575(576)

DUV Aera193

Maker Lasertec NEC NEC KLA-Tencor KLA-Tencor AMAT

Mode D/D (Cell shift) D/B, D/D D/B, D/D D/B, D/D, SL D/B, D/D D/D, (D/M)(Aerial Image)

Illumination forinspection

Trans only Trans only Trans andReflect

Trans andReflect

Trans, Reflect Trans only

Wavelength[nm]

248 266 266 365 257 193

Pixel size [nm] 125 100 100 150 125 (90) 150

Sensitivity [nm] 100 (80) 100 80 100 80 (70) 10%CD@wafer

Min. Line width[nm]

300 400 280 400 B225/W255(B180/W200)

Not specified

Scan Time [min]100mm sq.

120 122 195 74 90 (175) 120


Absorber layer defect repair

Evaluated repair technique• FIB-GAE (Gas Assist Etching)• AFM Machining

XeF2 gas

Ga+ beam

TaGeN

SubstrateCr

FIB-GAE AFM Machining

TaGeN

SubstrateCr

AFM tip (Diamond)


SEM images of AFM machining defect repair results

ReferenceBefore buffer layer dry etching

•1um line and space•Defect pattern size 0.5 um

TEST 1-3X bias 0nmZ bias 5nm





Mask Topography Measurement with CD-AFM

Differences Between 1D and 2D SFM Scan

direction

Servo direction

Scan direction

Servo direction


Summary• Mask technology development for EUV has been

establishing with Consortia at feasibility study stage.• Most of current infrastructures and technologies have been

adapting for preliminary evaluation of EUV mask making.• Ta based absorber material has been patterned successfully.• Various repair technologies for absorber pattern has been

evaluating.• Issues are

– Quality of substrate material (Specifications??)– Improvement of mask quality (CD, etc.)– Inspection & repair– Cleaning and mask handling

• What do you really want?!• Need feed back from exposure result to define “realistic”

specifications.– Printable defects, flatness, surface treatment, etc.

euv mask process development

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