ese 570 static sequential cmos logic cellsese570/spring2015/ese570_seqlog15.pdfese 570 static...

Kenneth R. Laker, University of Pennsylvania, updated 25Mar15

1

ESE 570 STATIC SEQUENTIAL CMOS LOGIC CELLS


2

Classes of Logic Circuits

two stable op. pts.Latch – level triggered.

Flip-Flop – edge triggered.

one stable op. pt.One-shot – single

pulse output

no stable op. pt.Ring Oscillator

Combinational Circuits: a. Current Output(s) depend ONLY on Current Inputs.b. Suited to problems that can be solved using truth tables.

Sequential Circuits or State Machines: a. Current Output(s) depend on Current Inputs and Past Inputs via State(s).b. Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner.


3

SequentialOperationsCombinational

OperationsCombinational

Operations

Flip-Flops/Latches

Data Transfer

Binary Counting

Binary Counting

DecadeCounting

FrequencyDivision

FrequencyCounting

ShiftRegister

ArithmeticLogic Unit

Parallel

Serial

Microprocessor

Microcomputer

are performed in an

which is acomponent of a

which is thecore of a

may usememory cells such as to accomplish

to accomplish

which may be

using a

andand

or

Functions Using Sequential Operations


4

-> Memory is used to Store Past Values of State(s) and Output(s).-> Asynchronous Sequential Circuit – no clock, outputs change after inputs change-> Synchronous Sequential Circuit – clock, outputs change with clock event

Vo1Vo2

Sequential Circuit (or State Machine) Construct

.

.

.

.

.

.

.

.

Vo3

PresentState

NextState

Inputs Outputs

Clock


5

Combinational Logic

Combinational Logic

Comb LogOutputs

State Register

Clock

State Register

Clock

State FeedbackState Feedback

Xj

Inputs

Xj

Inputs

Yk Outputs

Yk Outputs

Moore FSM

Mealy FSM

Yk's are solely function of

current states. Y

k's change in sync with

state clock.

Yk's function of inputs &

current states. Y

k's change when inputs

change. Y

k's are asynchronous


6

Static Bistable Sequential Circuits

Basic Cross-coupled Inverter pair

Q

Q


7

Bistable Sequential Circuits - cont.

Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s) to change the circuit's State.

Basic Cross-coupled Inverter pair

Q

Q

VOH

= VDD

VOL

= 0

maintain stable state.STATIC: VDD and GND are required to maintain a stable state.


8

Basic Sequential Circuits (Cells)

LatchAsynchronous or synchronousIf synchronous, clock input is level sensitive.If synchronous, output can change multiple times during a clock cycle.If synchronous, output changes while clock is active.

Flip-FlopSynchronousInvolves two synchronous latches.

Output is edge sensitive, i.e. Output only changes on rising (or falling) edge of clock.Output can change only once during a clock cycle.Output changes on clock transition.


9

Asynchronous Latch Circuits

NOR Based Latch

Full CMOS Asynchronous SR Latch

Q t1=1,Q t1=0Q t1=0,Qt1=1Q t1=Qt0 ,Q t1=Qt0

pair

basic cross-coupled inverter pair

Qt1= 0, Q

t1= 0 is forbidden state

or not allowed state S

t1 = 1, R

t1 = 1


10

Asynchronous CMOS NOR SR Latch Operation

-> initial state

-> set state

Let at t = t0:Q t0=0,Q t0=V DD

At t = t1 > t0:S

t1= 1 Q t1=0

Rt1= 0 Q t1=0 Q t1=1Q t1=1 Q t1=0

SET OP:S = 1, R = 0


11

Asynchronous CMOS NOR SR Latch Operation - cont.

-> initial state

-> reset state

RESET OP:R = 1, S = 0


12

Asynchronous CMOS NOR SR Latch Operation - cont.HOLD OP:S = 0, R = 0

1

1


13

Asynchronous CMOS NOR SR Latch Operation - cont.HOLD OP:S = 0, R = 0

1

1


14

Asynchronous CMOS NOR SR Latch Operation - cont.

*rise ,Q (SR−Latch)≈*rise ,Q (NR2)%* fall , 'Q (NR2)

NR2Q NR2Q

CQ = Cload-NR2Q = 2Cn-int + 3Cp-int + Cext

CQ = Cload-NR2Q = 2Cn-int + 3Cp-int + Cext


15

Asynchronous Latch Circuits - cont.

“ACTIVE HIGH”

t0 t0


16

Asynchronous CMOS NAND SR Latch Circuit

“ACTIVE LOW”

Is NAND OR NOR SR LATCH PREFERRED?


17

Asynchronous CMOS NAND SR Latch Circuit - cont.

t1 > t0


18

CMOS Level Sensitive Synchronous Latches

NAND SR Latch

“ACTIVE HIGH”

NOTE: S and R are asynchronous.

CK

S or R S'

or R'

IS CK = 1, S = 0, R = 0 a HOLD STATE?

When CK = 0, S' = R' =1 independent of the values of S and R => HOLD

S't1 R't1

HOLD STATE: CK = 0, S = x, R = x => S' = 1, R' = 1 => Qn+1 = Qn, Qn+1 = QnSET STATE: CK = 1, S = 1, R = 0 => S' = 0, R' = 1 => Qn+1 = 1, Qn+1 = 0RESET STATE: CK = 1, S = 0, R = 1 => S' = 1, R' = 0 => Qn+1 = 0, Qn+1 = 1NOT ALLOWED: CK = 1, S = 1, R = 1 => S' = 0, R' = 0

CK

S'orR'

SR LATCH:NAND SR LATCH

NAND SR FLIP FLOPSorR


19

R

Q error due to glitch on S

CMOS Level Sensitive Synchronous Latches - cont.

T glitch&*rise ,QT glitch

NOT ALLOWED: CK = 1, S = 1, R = 1HOLD STATE: CK = 1, S = 0, R = 0


20

Gate level schematic of clocked NAND based SR Latch or Flip-Flop


“ACTIVE LOW”

When CK = 1, S' = R' =1 independent of the values of S and R => HOLD

S' = R' = 0

S't1 R't1

S'

R'

Another Gate Level schematic of a Clocked NAND Based SR Latch

Set and Reset operations only occur when CK = 0.

SR LATCH

SR Flip Flop


21

CMOS NAND Based Clocked SR Latch


“ACTIVE LOW”

1 1

SR Latch


22

CK = 1

CK = 1

When CK = 1, the latch state Q and Q is independent of inputs S and R , and the latch is in Hold operation.

CMOS NAND Based SR Clocked Latch

SR Flip Flop



23

CK = 0

CK = 0When CK = 0, the state Q and Q depend on inputs S and R, and the schematic reduces to that of a NAND based SR latch.

CMOS NAND Based SR Clocked Latch

Latch



24

NAND BASED JK Synchronous Latch

NAND SR

LATCH


S = R ≠ 0 for all values of J, K, CK

CK = 1 => active


25

NAND JK Synchronous Latch Operation

“ACTIVE HIGH”

The not-allowed S, R values S = R = 0 do not occur for any values of J, K, CK.

reset (hold)

set (hold) not desirable, but the state Q

n+1, Q

n+1 is

not forbidden

CK = 0 => Holdi.e. S = R = 1 independent of J, K

CK = 1 => active

SR LATCH


26

(high speed clock may be impractical)

2nd TIME)FLIP FLOP

NAND Based JK Synchronous Latch in Toggle Mode


27

Clocked Negative Edge Triggered SR Flip-Flop (FF)

to propagate to Latch2.

- S = R = 0 are Not Allowed Inputs

X

X'

Y

Y'

● Start with CK = 0 => X = X' = 1, Latch 1 is Hold => Q1, Q1 are independent of S, R.● Changes in S, R can't change the state of Latch 1 nor the state Q2, Q2 of Latch 2.

● When CK = 1, inputs S, R control the state of Latch 1.● Inverted CK = 0 applied to Latch 2 (=> Y = Y' = 1) and Latch 2 is Hold and state Q2, Q2

are independent of Q1, Q1.● When CK = 1 changes to S, R are tracked by Latch 1, but not reflected in the state Q2, Q2

of Latch 2.

● When CK = 0, the state of Latch 1 Q1, Q1 are independent of inputs S, R.● Inverted CK = 1 enables the Held state of Latch 1 to effect the state Q2, Q2 of Latch 2.● CK → 1 to 0 is the the falling (negative) edge of the CK signal.

+ Synchronous Op+ Not Level Sensitive- S, R = 1 Not Allowed

Xt1 X't1CK = 1

Q1

Q1

Q2

Q2

S

R

CKCK

CK

SR-NAND Latch 1 (master) SR-NAND Latch 2 (slave)


28

Clocked Negative Edge Triggered JK Flip-Flop

J

K

CK

- Complex circuit, requiring 42 transistors- Note: SR FF circuit requires 32 transistors

CK

Q2

Q2

Q1 Q2

Q1

+ Synchronous Operation+ No Not-Allowed States+ Not Level Sensitive+ No Q2, Q2 Oscillation when J = K = 1; i.e.

toggle of JK-Latch1 is not seen by JK-Latch2

CK = 1

JK – Latch 1 JK – Latch 2

S1

R1

Q1n-1

Q1n-1

Q1n Q1

n

S2

R2


29

Static CMOS D-LATCHGate level implementation by modifying a NAND SR Latch.

CK D S' R' Qn+1

Qn+1

1 1 0 1 1 0 SR-Set 1 0 1 0 0 1 SR-Reset 0 x 0 0 Q

n Q

n SR-Hold

+ NO TOGGLE+ NO NOT-ALLOWED INPUTS

S

R

LATCH

18 Transistors

OUT

IN1

IN1IN2

IN2


30

**Transistor level implementation using transmission gates requires fewer transistors

Static CMOS TG D-LATCH – Eight Transistors

8 Transistors


31

QQ

Q

Q

Q

Q

D

D

D

CKCK

CK

CK

CK=1

CK=0

CMOS TG D-LATCH Operation

Since when CK = 1 output Q = D, and tracks D until CK = 0, the D-Latch is referred to positive level triggered.

When CK → 1 to 0, the Q = D is captured, held (or stored) in the Latch.


32

D-LATCH Timing Requirements

CLK

NEG(pos)

NEG(pos)

NEG(pos)


33

D-Latch Metastability and Synchronization Failureslatch,

latch,

the flip-flop output to “0” or “1”.

case)


34

CMOS D Edge Triggered Flip-FlopNegative Level Triggered D Latch

Positive Edge Triggered D Flip-Flop = Negative D-Latch + Positive D-LatchNegative Edge Triggered D Flip-Flop = Positive D-Latch + Negative D-Latch

Positive Level Triggered D Latch


35

CMOS D Flip-Flop – Positive Edge Triggered

unaffected by

unaffected by

unaffected by

i.e. positive level sensitive

master (neg. D) slave (pos. D)i.e. negative level sensitive

master (neg. D)


36

CLK

CLK

CLKideal non-ideal

CLK & CLK

CLK + τD

Impact of Non-ideal Clock on D-Latch Operation

CLK & CLK + τD

tt


37

φ2

φ1

φ1

φ2

t

t

φ1

φ2

Two-Phase Clocked D-Latch


38

Practical CMOS D Edge Triggered Flip-Flop

NOT Practical

Practical

φ2φ

1

φ2φ

1


39

CMOS Dynamic D Latch

Cx is usually a

parasitic capacitance

Positive level-sensitive

D Q


40

Comparison CMOS Static & Dynamic D Latches

Data bit stored on Cx

when CK = 1 → 0

Dynamic D-Latch

φ2φ

1

φ2φ

1

Static D-Latch

Data bit stored in bistable-loop when φ1 = 1 → 0


41

φ2

φ1

φ2

φ1

φ1

φ2

φ2

φ1

CMOS Static & Dynamic D FFs

ese 570 static sequential cmos logic cellsese570/spring2015/ese570_seqlog15.pdfese 570 static...

Documents