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Errata for Digital Systems Design Using VHDL, 2nd edition

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Errata for Digital Systems Design Using VHDL, 2nd edition, 3rd printing p. 33, line 7: "2. Clock period" should be "2. Propagation delays" p. 33, line 8: Q fed back should be Q was fed back p. 57, box with Common Abbreviations - expansion for ASCII: exchange should be interchange p. 74, line 4 from bottom: "G changes. Then F" should be "C changes. Then, B" line 5 from bottom: "E" should be "A" p. 94, line 8: add "treat" after "operators" p. 97, Figure 2-45, last column of table: interchange "(increment count)" and "(no change)" p. 98, lines 6-7: hyphen missing, "whenever" is split incorrectly between the two lines without a hyphen. Insert hyphen after when. p. 119, Section 2.19, 3rd line of code segment for assert: ";]" should be "];" i.e. Change [severity severity-level;] to [severity severity-level]; p. 130, Problem 2.35, line 6: "UP 0" should be "UP = 0" p. 133, Problem 2.43, line 1 of code: Change "4to1mux" to "Fourto1mux". (VHDL names cannot begin with a numeral.) p. 195, Figure 4-7, labeling of rightmost full adder input: Change "B20" to "B0". p. 202, Figure 4-15, line 14 of the code: must be when 0 to 4 => Ga
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p. 435, Table 9-3, 4th instruction store halfword: in second column, sw should be sh p. 455, line 28: for consistency, change npc to nPC and change pc to PC p. 488, lines 4-5 from bottom of code: add spacing to make it St = ShiftDR and St = ShiftIR p. 549 and also p. 551, the two lines after signal assignment statement: should read: signal

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