epc8002 – enhancement mode power transistor - epc...
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eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 | | PAGE 1
EPC8002
EPC8002 – Enhancement Mode Power Transistor
VDS , 65 VRDS(on) , 480 mID , 2 A
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.
EFFICIENT POWER CONVERSION
New Product
EPC8002 eGaN FETs are supplied only in passivated die form with solder barsDie Size: 2.1 mm x 0.85 mm
Applications• Ultra High Speed DC-DC Conversion• RF Envelope Tracking• Wireless Power Transfer• Game Console and Industrial Movement
Sensing (LiDAR)Benefits• Ultra High Efficiency• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
HAL
Maximum Ratings
VDSDrain-to-Source Voltage (up to 10,000 5 ms pulses at 150° C) 78
Drain-to-Source Voltage (Continuous) 65V
ID
Continuous (TA = 25˚C, RθJA= 37 ˚C/W) 2
2A
Pulsed (25˚C, TPulse = 300 µs)
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJ Operating Temperature -40 to 150˚C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
RθJC Thermal Resistance, Junction to Case 8.2 ˚C/W
RθJB Thermal Resistance, Junction to Board 16 ˚C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1) 82 ˚C/W
TYP UNIT
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics (TJ= 25˚C unless otherwise stated)
Specications are with substrate shorted to source where applicable.
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 µA 65 V
IDSS Drain Source Leakage VDS = 52 V, VGS = 0 V 20
20
100 µA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.1 1µA
mA
Gate-to-Source Reverse Leakage VGS = –4 V 100
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.1 mA 0.8 1.4 2.5 V
V
RDS(ON) Drain-Source On Resistance VGS = 5 V, ID = 0.5 A 380 480 mΩ
VSD 2.6Source-Drain Forward Voltage IS = 0.4 A, VGS = 0 V
www.epc-co.com/epc/Products/eGaNFETs/EPC8002.aspx
eGaN® FET DATASHEET
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EPC8002
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
CISS Input Capacitance
COSS Output Capacitance
CRSS
COSS(ER)
COSS(TR)
Reverse Transfer Capacitance
Eective Output Capacitance, Energy Related (Note 2)Eective Output Capacitance, Time Related (Note 3)
RG Gate Resistance
QG Total Gate Charge
QGS Gate-to-Source Charge
QOSS Output Charge
QRR Source-Drain Recovery ChargeNote 2: COSS(ER) is a xed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.Note 3: COSS(TR) is a xed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
VDS = 32.5 V, VGS = 0 V
VDS = 0 to 32.5 V, VGS = 0 V
VDS = 32.5 V, VGS = 5 V, ID = 0.5 A
VDS = 32.5 V, ID = 0.5 A
VDS = 32.5 V, VGS = 0 V
20
pF
Ω
6.7
0.12
8.9
10
57
0.3
133
pC15
46
334
0
24
10
0.18
167
500
26QGD Gate-to-Drain Charge
QG(TH) Gate Charge at Threshold
Figure 1: Typical Output Characteristics at 25°C
VDS– Drain-to-Source Voltage (V)
I D– Dr
ain
Curre
nt (A
)
1.5
1.0
2.0
0.5
0.5 1.5 1.0 2.0 2.5 3.0
VGS
GS
GS
GS
= 5 VV = 4 VV = 3 VV = 2 V
0 0
1.5
1.0
2.0
0.5
0
VGS– Gate-to-Source Voltage (V)
I D– Dr
ain
Curre
nt (A
)
0.5 1.0 1.5 2.0 3.02.5 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
25˚C125˚C
VDS = 3 V
1500
1200
900
600
300
0
VGS– Gate-to-Source Voltage (V)
2.5 3.0 3.5 4.54.0 5.0
Figure 3: RDS(on) vs VGS for Various Drain Currents
R DS(o
n)–
Drai
n-to
-Sou
rce R
esist
ance
(mΩ)
ID= 0.5 A
ID= 1.0 A
ID= 1.5 A
ID= 2.0 A
Figure 4: RDS(on) vs VGS for Various Temperatures
R DS(o
n) –
Drai
n-to
-Sou
rce R
esist
ance
(mΩ) 25˚C
125˚C
ID = 0.5 A
VGS – Gate-to-Source Voltage (V)
2.5 3.0 3.5 4.54.0 5.0
1500
1200
900
600
300
0
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EPC8002
25
20
15
10
5
00 10 30 40 5020 60
Figure 5: Capacitance (Linear Scale)
VDS– Drain-to-Source Voltage (V)
C – Ca
pacit
ance
(pF)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
100
10
1
0.1
0.010 10 403020 6050
Figure 5A: Capacitance (Log Scale)
VDS– Drain-to-Source Voltage (V)
C – Ca
pacit
ance
(pF)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
4
5
3
1
2
00.05 0.150.1
Figure 6: Gate Charge
QG– Gate Charge (nC)
V GS –
Gate
-to-S
ourc
e Vol
tage
(V) ID= 0.5 A
VDS = 32.5 V
0
25˚C125˚C
2.0
1.5
1.0
0.5
0
VSD – Source-to-Drain Voltage (V)
I SD –
Sour
ce-to
-Dra
in Cu
rrent
(A)
0.5 0 1.0 1.5 2.0 3.02.5 3.5 4.0 4.5 5.0
Figure 7: Reverse Drain-Source Characteristics
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.80 5025 75 100 125 150
Figure 8: Normalized On-State Resistance vs Temperature
Norm
alize
d On
-Sta
te R
esist
ance
– R
DS(o
n)
TJ – Junction Temperature (°C)
ID = 0.5 AVGS = 5 V
ID = 0.1 mA
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
TJ– Junction Temperature (°C)
Norm
alize
d Th
resh
old
Volta
ge (V
)
0 25 50 75 125100 150
Figure 9: Normalized Threshold Voltage vs Temperature
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EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 | | PAGE 4
EPC8002
1.00.90.
80.7
1.2 1.
4 1.6
1.8
2.0
0.6
0.5
0.4
0.3
0.2
0.1
3.0
6.0
8.010
5.0
4.0
20
RF Café2002
100 0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
1.0
0.9
0.8
0.7
1.2
1.4
1.6
1.8
2.0
3.0
6.0
8.010
5.0
4.0
0.6
0.5
0.4
0.3
0.2
0.1
20
S11 – Gate ReectionS22 – Drain Reection
Figure 11: Smith Chart
S-Parameter CharacteristicsVGSQ = 1.17 V, VDSQ = 30 V, IDQ = 0.2 A
Pulsed Measurement, Heat-Sink Installed, Z0 = 50 Ω
Figure 12: Gain Chart Figure 13: Device Reflection
Figure 14: Taper and Reference Plane details – Device Connection
Frequency Gate (ZGS) Drain (ZDS)
[MHz] [Ω] [Ω]
200 3.09 - j29.97 63.13 - j71.32
500 2.20 - j11.92 15.96 -j46.65
1000 1.14 - j4.46 3.35 - j23.47
1200 0.95 - j2.76 1.91 - j18.52
1500 0.87 - j0.55 1.66 - j12.66
2000 1.09 + j2.61 2.28 - j6.12
2400 1.44 + j4.87 4.35 - j2.80
3000 2.36 + j8.79 6.41 + j0.69
S-Parameter Table - Download S-parameter files at www.epc-co.com
ZDS
ZGS
Gate Circuit Reference Plane
Drain Circuit Reference Plane
Device Outline
914
1621
1621
149
1000
271
271
All dimensions in µm 914 355
Gmax
45
40
35
30
25
20
15
10
5
0100 1000
Ampl
itude
(dB)
Frequency (MHz)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-0.2
25˚C125˚C
0.30
0.25
0.20
0.15
0.10
0.05
010 32 4 5 6
Figure 10: Gate Leakage Current
VGS – Gate-to-Source Voltage (V)
I G –
Gate
Curre
nt (m
A)
Micro-Strip design: 2-layer½ oz (17.5 µm) thick copper30 mil thick RO4350 substrate
All measurements were done with substrate shortened to source.
eGaN® FET DATASHEET
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EPC8002
Figure 16: Safe Operating Area
0.1
1
0.1 1 10 100
I D - D
rain
Curre
nt (A
)
VDS – Drain Voltage (V)
Pulse Width100 ms 10 ms 1 ms 100 µs 10 µs
Limited by RDS(on)
tp– Rectangular Pulse Duration (s)
1
0.1
0.01
0.001
Z θJB
Nor
mal
ized
Ther
mal
Impe
danc
e
Figure 15: Transient Thermal Response Curves
Single Pulse
Junction-to-Board
0.020.01
0.5
0.20.10.05
Duty Factors:
Duty Factor = tp/TPeak TJ = PDM x ZθJB x RθJB + TB
Notes:
tp
T
P DM
Duty Factor = tp/TPeak TJ = PDM x ZθJC x RθJC + TC
Notes:
tp
T
P DM
Single Pulse
0.020.01
0.5
0.2
0.10.05
Duty Factors:
10-410-5 10-3 10-2 10-1 1 10
10-410-5 10-3 10-2 10-1 1 10
tp– Rectangular Pulse Duration (s)
Junction-to-Case
Z θJC
Nor
mal
ized
Ther
mal
Impe
danc
e
1
0.1
0.01
0.001
TAPE AND REEL CONFIGURATION4mm pitch, 8mm wide tape on 7” reel
8002 YYYY
ZZZZ
Gate Pad bump is
under this edge of die
Die orientation
dot
Die is placed into pocket bump side down (face side down)
7” reel
Loaded Tape Feed Direction
a
d e f g
c
b
Dimension (mm) target min maxa 8 7.9 8.3b
EPC8002 (Note 1)
Note 1: MSL1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,not the pocket hole.
c (see note 2) 3.5 3.45 3.55d 4 3.9 4.1e 4 3.9 4.1
f (see note 2) 2 1.95 2.05g 1.5 1.5 1.6
1.75 1.65 1.85
8002 YYYY
ZZZZ Die orientation dot
Gate Pad bump is under this edge of die
Part Number
Laser Markings
Part #Marking Line 1
Lot_Date CodeMarking line 2
Lot_Date CodeMarking Line 3
EPC8002 8002 YYYY ZZZZ
DIE MARKINGS
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EPC8002
850
570
2050
1 2
4
3
6
5
400
190
600 600 400
440
190
190
RECOMMENDEDLAND PATTERN (units in µm)
The land pattern is solder mask defined.
Recommended stencil should be 4 mil (100 μm) thick, must be laser cut, openings per drawing.
Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.
Additional assembly resources available at: http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
Information subject to change without notice.
Revised November, 2015
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398; 8,785,974; 8,890,168; 8,969,918; 8,853,749; 8,823,012
Pad no. 1 is GatePad no. 2 is Source Return for Gate Driver Pad no. 3 and 5 are SourcePad no. 4 is DrainPad no. 6 is Substrate
DIE OUTLINESolder Bar View
Side View(units in µm)
DimMicrometers
Min Nominal Max
A 2020 2050 2080
B 820 850 880
C 555 580 605
D 400 400 400
E 600 600 600
F 200 225 250
G 175 200 225
H 425 450 475
I 175 200 225
J 400 400 400
Pad no. 1 is GatePad no. 2 is Source Return for Gate Driver Pad no. 3 and 5 are SourcePad no. 4 is DrainPad no. 6 is Substrate
RECOMMENDED STENCIL DRAWING (units in µm) 2050
R 60
850
325 200 245 230 450 272275
272
200
592
250
200
B A
i
1 2
3
4
5
6
j
gx2
e e d f
h
C
i X2
815 M
ax
100 +
/- 20
SEATING PLANE
(685
)