Sill Torres: AMA

Enhancement of System-Lifetime by Alternating Module Activation

Frank Sill TorresDepartment of Electronic Engineering,

Federal University of Minas Gerais, Belo Horizonte, Brazil

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Focus / Main ideas

1. Approach aiming at extension of expected

lifetime

2. Enabling of detection of faulty design blocks

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Motivation Alternating Module Activation Extended Alternating Module Activation Results Conclusion

Outline

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Probability for failures increases due to: Increasing transistor count Shrinking technology

MotivationTechnology Development

2002 2004 2006 2008 20100

300

600

900

1200

nm

20 nm

40 nm

60 nm

80 nm

100 nm

120 nm

140 nm

130 nm

90 nm 65 nm 45 nm

32 nm

Ano

Tecn

olog

ia

2002 2004 2006 2008 20100

300

600

900

1200

Year

# Tr

ansi

stor

s (M

ill.)

Wolfdale410 Mil.

Northwood55 Mil.

Prescott125 Mil.

Yonah151 Mil.

Gulftown1.170 Mil.

Wolfdale410 Mil.

Tecn

olog

y

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Electromigration (EM)– Performance reduction and errors– Depending on currents and temperature

Negative Bias Temperature Instability (NBTI)– Performance reduction– Depending on voltage level and temperature

Time Dependent Dielectric Breakdown (TDDB) – Performance reduction and errors– Depending on voltage level and temperature

MotivationTime Dependent Failure Mechanisms

Increase of lifetime through reduction of supply voltage and activity

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SLEEP

Basic idea: Reduction of degradation via module deactivation Problem: What to do at run-time?

Alternating Module ActivationConcept and Realization

ModuleModule

Module 1Instance 2

Module 1Instance 1

Module 2

MUX

tlife-new ≈ tlife-old + toff

tlife-system = tlife-module

≈ tlife-old + toff

≈ 2* tlife-old + tsleep

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Test Environment– BPTM 22nm, Monte-Carlo simulations– Modeling of TDDB and EM (w/o consideration of temperature) – Estimation of expected life time via Mean Time To Failure (MTTF)

Results– Lifetime increase by factor 2.2 (aver.)– Delay increase by 7 % (aver.)– Power increase (dynamic and leakage) by 5 % (aver.)– Area increase by 110 % (aver.)

Alternating Module ActivationPrevious Results (Cornelius, Sill Torres;JOLPE;2011)

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Extended Alternating Module ActivationDiscussion

Considerably extension of expected lifetime Moderate increase of delay and power

Advantages

Strong increase of area No detection of faulty elements

Disadvantages

Utilization of overlapping activity phases Additional comparators and BIST mode Identification and deactivation of faulty elements

Proposed Improvements

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Extended Alternating Module ActivationComparator

Additional Comparator → enabling detection of inconsistent results of all module’s instances for same inputs

Deactivation via Sleep Transistor

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Extended Alternating Module ActivationBuilt-In Self Test (BIST) - Mode

Additional BIST Mode → Enabling identification of faulty instances Deactivation via Sleep Transistor

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Instance i active

All Instances active

All C-M active

transition to output of

instance (i+1)

All Instanceswithout i+1

deactive

All C-M deactive

All C-BIST and memory

active

System Halt

Instance j removed from list

All C-BIST and memory

deactive

Transition to Test-In

Transition to Data-In

System Reactivated

Error

No Error

transition to output of instance j Run BIST

i++

j++

No Error

Error

j=0

Error detection via comparators C-M

BIST mode

Extended Alternating Module ActivationControl Flow

BIST mode (system paused)

Inconsistence detection while instances in transition

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0.0

0.5

1.0

1.5

2.0

2.5

b05 b15 b21 c1355 c3540 mult32 MIPS

Incr

ease

of S

yste

m's

MTT

F

ResultsMean Time To Failure (vs. raw designs)

(Verilog cell models, technology and error data based on BPTM 22nm, 100 simulations, error free control circuitry)

2.0

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ResultsImprovements for Instances with Different MTTFs

(Verilog cell models, data based on BPTM 22nm, 100 simulations, error free control circuitry, 7 standard designs from previous slide)

1

1.5

2

2.5

3

3.5

1 1.25 1.5 1.75 2

Incr

ease

of S

yste

m's

MTT

F

Relation of instances MTTFs

min max average

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ResultsTest Chip

CMOS ams c35 (0.35µm)

Normal Adder

Redundant Adder based on AMA

Sleep Transistors

Prepared for Controlled Destruction

External Control Circuitry

In testing phase

Standard Adder

AMA based Adder

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Progressing susceptibility of current technologies against severe failure mechanisms

Extension of expected lifetime by alternating (de-)activation of redundant blocks via sleep transistors

Identification and deactivation of faulty blocks Extended control flow Increase of MTTF by

– Factor 2 for equally distributed failure probabilities– More than factor 3 for unequally distributed failure probabilities

Conclusion

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Thank you!franksill@ufmg.br

ART

OptMAlab / ARTwww.asic-reliability.com