Engineering Test Coverage on Complex Sockets

Myron Schneider

Purpose

• Obtain the maximum possible test coverage

on a complex socket with a reliable and cost-

effective approach.

… including fixed pins and inaccessible pins

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Outline

• The Importance of Socket Test Coverage

• Pin Classification for the Purposes of Test

• Socket Test Methods

• Engineered Interposer Design

• Results

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Why is test coverage on sockets important?

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• Highly integrated target devices

Interconnect matters more

Increased pin density

• More emphasis on signal integrity

Grounds are not trivial

• Coverage Quality

Socket F 1207

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Pin Classification

• All pins are not equal for the purposes of test.

The effectiveness of some test methods

depends on the functionality of the pin tested.

1) Signal Pins

2) Fixed Pins Used for Signal Integrity

3) Fixed Pins Used for Power Distribution

4) Inaccessible Pins

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Example Socket Pin Classification

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Socket Test Methods

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• Automated X-Ray Inspection

• Functional

• Silicon Surrogates

• Vector-less test with Network Parameter

Measurement (NPM)

Engineered Interposer

• Utilizes vector-less test since it is an

unpowered, cheap, and proven technology

• Engineers relationships on a mating PCB to

extend NPM technology

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Interposer and Sense Plate

Interposer Sense Plate

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Four Pin Electrical Model

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Engineering Relationships

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Primary Design Constraints

• Low CostFR4

• Fast turn-aroundStandard-cell design and automatic netlist

generator

• Reliable coverage on maximum number of pinsEngineered redundancy

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Interposer Design

1) Look at CPU datasheet to match all

dimensions, pad size and pitch

2) Find locations of all fixed and inaccessible

pins (coverage slightly negotiable)

3) Run netlist generator software

4) Layout board

1.5 days14

Interposer PCB

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Diagnostic Software

• Needs netlist output to know which

relationships are engineered

• Accounts for possible variations in

interposers, DUTs, insertions, etc.

• Aided by statistical methods and engineered

redundancy

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Results – Seeded Faults

• Goal: Validate theory and test out first pass

algorithm

• 26 seeded defects introduced

• Initial algorithm caught all but 3

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Socket 1207 Pin Classification and Seeded Defects

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Results – Production Run

• Goal: Use larger sample of boards (that had

passed functional test) to investigate

algorithm stability and to catch real random

defects.

• 88 sockets

• Found 2 defective pins on 1 socket

• No other pins indicted

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Conclusion

• Effective

• Quick to design

• Cheap

• Low false calls

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