eng241 digital design week #7 sequential circuits (part b)
DESCRIPTION
3Resources Chapter #6, Mano Sections 6.4 Sequential Circuit Analysis 6.5 Sequential Circuit Design 6.7 VHDL Representation of Sequential circuitsTRANSCRIPT
![Page 1: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/1.jpg)
ENG241 ENG241 Digital DesignDigital Design
Week #7 Sequential Circuits (Part B)
![Page 2: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/2.jpg)
2
Week #7 TopicsWeek #7 Topics
Sequential Circuit Analysis Sequential Circuit Design
Designing with D Flip-Flops Designing with JK Flip-Flops Designing with T Flip-Flops
VHDL Representations Examples
![Page 3: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/3.jpg)
3
ResourcesResources
Chapter #6, Mano Sections 6.4 Sequential Circuit Analysis 6.5 Sequential Circuit Design 6.7 VHDL Representation of Sequential
circuits
![Page 4: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/4.jpg)
4
Analysis of Sequential CircuitsAnalysis of Sequential Circuits
Earlier we learned how to analyze combinational circuits
We will extend analysis to synchronous sequential
We’ll use1. State tables and 2. State diagrams
![Page 5: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/5.jpg)
5
Review: Flip FlopsReview: Flip Flops
![Page 6: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/6.jpg)
6
Analysis of Sequential CircuitsAnalysis of Sequential Circuits
The behavior of a sequential circuit is determined from:
Inputs, Outputs, Present state of the circuit.
The analysis of a sequential circuit consists of:
Obtaining a suitable description that demonstrates the time sequence of inputs, outputs and states (STATE DIAGRAM).
![Page 7: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/7.jpg)
7
Step #1: Derive Input EquationsStep #1: Derive Input Equations
Can describe inputs to FF with logic equations
)( CYXBJ A )( CBYK A
![Page 8: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/8.jpg)
8
Another ExampleAnother Example
)( BXAXDA
XADB
XBAY )(
![Page 9: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/9.jpg)
9
Input EquationsInput Equations
The input equations1. Imply the type of flip-flop from the
letter symbols, 2. Fully specify the combinational circuit
that drives the flip-flops.
![Page 10: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/10.jpg)
10
Time is ImpliedTime is Implied Note that previous circuit used the
Present state (A, B, ..) to determine next statenext state State and inputs to determine outputoutput
Synchronous circuit When are transitions?
)( BXAXDA
XADB
XBAY )(
![Page 11: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/11.jpg)
Step #2: State TableStep #2: State Table Similar to truth table with state added A sequential circuit with `m’ FFs and `n’
inputs needs 2m+n rows in state table.
)( BXAXDA XADB XBAY )( 11
![Page 12: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/12.jpg)
12
Step#3: State Diagram “Mealy Model”Step#3: State Diagram “Mealy Model”
An alternative representation to State Table
Input/Output
InputOutput
![Page 13: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/13.jpg)
13
Sequential Circuit TypesSequential Circuit Types
Moore modelMoore model – outputs depend on states onlystates only.
Mealy modelMealy model – outputs depend on inputs & statesinputs & states
![Page 14: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/14.jpg)
14
State Diagram: MooreState Diagram: Moore
Alternative representation for state table
State/OutputInputs
![Page 15: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/15.jpg)
15
Moore vs. Mealy MachineMoore vs. Mealy Machine
Moore Machine: Moore Machine: Easy to understand and easy to code. Might requires more states (thus more hardware).
Mealy Machine:Mealy Machine: More complex since outputs are a function of both the state and
input. Requires less states in most cases, therefore less components.
Choice of a model depends on the application and personal preference.
You can transform a Mealy Machine to a Moore Machine and vice versa.
![Page 16: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/16.jpg)
16
State Table vs. DiagramState Table vs. Diagram
Provides same information Table is perhaps easier to fill in from
description Diagram is easier for understanding and
writing code Analysis for sequential circuits that employs
D flip flops is easy. Why? Because the next state values are
obtained directly from the input equations.
![Page 17: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/17.jpg)
17
Analysis with JK Flip FlopsAnalysis with JK Flip Flops
For circuits with other types of flip flops such as JK, the next state values are obtained by following the two step procedure:
1. Obtain the binary values of each flip-flop input equation in terms of the present state and input variables.
2. Use the corresponding flip-flop flip-flop characteristiccharacteristic to determine the next state.
![Page 18: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/18.jpg)
18
Analysis with JK Flip FlopsAnalysis with JK Flip Flops
JA = B JB = x’ KA = Bx’ KB = A’x + Ax’ = A x
![Page 19: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/19.jpg)
19
JK Analysis: State TableJK Analysis: State Table
JA = B KA = Bx’ JB = x’ KB = A’x + Ax’ = A x
Flip Flop Inputs
JK Characteristic Table
I. Use the Input equations to determine the FF inputs.
II. Use the FF inputs and Table to determine the next state.next state.
![Page 20: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/20.jpg)
20
JK Analysis State TableJK Analysis State Table
JA = B JB = x’ KA = Bx’ KB = A’x + Ax’ = A x
Flip Flop Inputs
![Page 21: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/21.jpg)
21
JK Analysis: State DiagramJK Analysis: State Diagram
00
01 10
11
1
0 0
11
0
10
![Page 22: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/22.jpg)
22
Analysis vs. DesignAnalysis vs. Design
The analysis of sequential circuits starts from a circuit diagram and culminates in a state table or state diagram.
The design of a sequential circuit starts from a set of specifications and we should obtain the state diagram and finally the logic diagram.
![Page 23: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/23.jpg)
23
Design ProcedureDesign Procedure
Design starts from a specificationspecification and results in a logic diagram or a list of Boolean functions.
The steps to be followed are:1. Derive a state diagram2. Reduce the number of states3. Assign binary values to the states4. Obtain the binary coded state table5. Choose the type of flip flops to be used6. Derive the simplified flip flop input
equations and output equations7. Draw the logic diagram
![Page 24: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/24.jpg)
24
Sequential Circuit DesignSequential Circuit Design
Remember that a synchronous sequential circuit is made up of flip flops and combinational gates.
Part of the design is to choose the flip-flop type and combinational circuit structure which, together with the flip-flops produce a circuit that fulfills the stated specification.
How many FLIP FLOPS?1. The number of flip-flops is determined from the
number of states in the circuit2. n flip-flops can represent up to 2n binary states.3. Examples:
1. 2 states requires a single Flip Flop2. 4 states requires two flip flops3. 8 states requires three flip flops4. 7 states requires again three flip flops …
![Page 25: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/25.jpg)
25
Designing with D Flip-FlopsDesigning with D Flip-Flops
Design a clocked sequential circuit that operates according to the state diagram.
![Page 26: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/26.jpg)
26
Synthesizing Using D Flip FlopsSynthesizing Using D Flip Flops
The next step is to create a state table and then select two D flip flops to represent the four states, labeling their outputs as A and B.
There is one input, x, and one output, y, representing the input sequence and the output value respectively.
Remember that the characteristic equation of the D flip flop is Q(t + 1) = DQ This means that the next-state values in the state
table specify the D input condition for the flip flop.
![Page 27: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/27.jpg)
27
Designing with D Flip-FlopsDesigning with D Flip-FlopsInput equations can be obtained directly from the table using minterms:
A(t + 1) = DA(A, B, x) = ∑m(2,4,5,6) B(t + 1) = DB(A, B, x) = ∑m(1,3,5,6)
![Page 28: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/28.jpg)
28
Designing with D Flip-FlopsDesigning with D Flip-Flops
However, we have to minimize the expression in a similar way used for combinational logic design!
![Page 29: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/29.jpg)
29
Designing with D Flip-FlopsDesigning with D Flip-Flops
![Page 30: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/30.jpg)
30
Designing with D Flip-FlopsDesigning with D Flip-Flops
DA = AB’ + BX’
DB= A’X + B’X+ ABX’
Y = B’X
![Page 31: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/31.jpg)
31
A Sequence DetectorA Sequence Detector
Design a circuit that detects a sequence of three ones.
Circuit Detects`111’ at input
Input Output
I. Create the state diagram
Moore Machine
![Page 32: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/32.jpg)
32
Synthesizing Using D Flip FlopsSynthesizing Using D Flip Flops
II. The next step is to create a state table and then select two D flip flops to represent the four states, labeling their outputs as A and B.
III. There is one input, x, and one output, y, representing the input sequence and the output value respectively.
IV. The output y is `1’ only when we detect the input sequence of `111’
![Page 33: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/33.jpg)
33
State Table for Sequence DetectorState Table for Sequence Detector
Input equations can be obtained directly from the table using minterms: A(t + 1) = DA(A, B, x) = ∑m(3, 5, 7) B(t + 1) = DB(A, B, x) = ∑m(1, 5, 7) y(A, B, x) = ∑m(6, 7)
![Page 34: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/34.jpg)
34
Boolean MinimizationBoolean Minimization
K-Maps can be used to minimize the input equations, resulting in DA = Ax + Bx DB = Ax + B’x Y = AB
![Page 35: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/35.jpg)
35
Logic Diagram of Sequence DetectorLogic Diagram of Sequence Detector
![Page 36: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/36.jpg)
36
Sequential Circuits with different Sequential Circuits with different Flip Flops (JK, T)Flip Flops (JK, T)
The design of sequential circuits other than D type flip flops is complicated by the fact that input equations must be derived indirectly from the state table. It is necessary to derive a functional
relationship between the state table and the input equations.
![Page 37: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/37.jpg)
37
Excitation TableExcitation Table
During the design, we usually know the transition from present to next state but we need to find the flip flop input conditions that will cause the required transition.
We need a table that lists the required inputs for a given change of state, called an excitation table.
![Page 38: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/38.jpg)
38
Excitation TablesExcitation Tables
Characteristic Table Excitation Table
Characteristic Table Excitation Table
![Page 39: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/39.jpg)
39
Synthesis Using JK Flip FlopsSynthesis Using JK Flip Flops
Synthesis of circuits with JK flip flops is the same as with D flip flops Except that the input equations must
be evaluated from the present-state to the next-state transition derived from the excitation table.
![Page 40: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/40.jpg)
40
Example: JK SynthesisExample: JK Synthesis
00
11
10
01
0
0
0
1 1 1
10
Example: No output
Step #1: Obtain State TableStep #1: Obtain State Table
![Page 41: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/41.jpg)
41
JK Synthesis: State TableJK Synthesis: State Table
0 0
PresentState
Next State
0 1
0 00 1
![Page 42: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/42.jpg)
42
Cont .. Example JK SynthesisCont .. Example JK SynthesisStep #2: Use K-MapsStep #2: Use K-Maps
![Page 43: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/43.jpg)
43
Cont .. Example JK SynthesisCont .. Example JK Synthesis
ABx
00 01 11 10
0
1
0 0 0 1
XXXXJA = BX’
![Page 44: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/44.jpg)
44
Cont .. Example JK SynthesisCont .. Example JK Synthesis
![Page 45: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/45.jpg)
45
Cont .. JK Synthesis Logic DiagramCont .. JK Synthesis Logic Diagram
![Page 46: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/46.jpg)
46
Synthesis Using T Flip FlopsSynthesis Using T Flip Flops
Synthesis of circuits with T flip flops is the same as with JK flip flops … except that the input equations must be evaluated from the present-state to the next-state transition derived from the T excitation table.
![Page 47: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/47.jpg)
47
Synthesis Using T Flip FlopsSynthesis Using T Flip Flops
Design a counter that counts from “000” to “111” and then back to “000” again. Constraint: Use T Flip-Flops
![Page 48: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/48.jpg)
48
A Counter using T Flip FlopsA Counter using T Flip Flops
000 001 010 011
100101110111
Notice the only input is the clock!
![Page 49: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/49.jpg)
49
Example: T Flip Flop SynthesisExample: T Flip Flop Synthesis
0
![Page 50: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/50.jpg)
50
Cont .. T Flip FlopsCont .. T Flip Flops
By using K-maps we can minimize the flip flop input equations.
T
T
T
1 A0
A1
A2
![Page 51: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/51.jpg)
51
One Dimensional TablesOne Dimensional Tables
![Page 52: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/52.jpg)
52
Two Dimensional TablesTwo Dimensional Tables
Same thing, different layoutSame thing, different layout
![Page 53: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/53.jpg)
53
Example – Sequence Recognizer Example – Sequence Recognizer (VHDL)(VHDL)
Circuit has input: W and output: Z Recognizes sequence of 11 on W
Specifically, if W has been 1 and next bit is 1, make Z high
Design a Moore and Mealy Machines
Sequence Recognizer
W Z
1010110111
![Page 54: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/54.jpg)
54
Sequence Recognizer (Mealy)Sequence Recognizer (Mealy)
Clk: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1z: 0 0 0 0 1 0 0 1 1 0 0
A B
w=1/z=0
w=0/z=0
Reset
w=0/z=0 w=1/z=1
![Page 55: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/55.jpg)
55
Mealy: ImplementationMealy: Implementation
Clk: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 1 0 0 1 1 0 0
A B
w=1/z=0
w=0/z=0
Reset
w=0/z=0 w=1/z=1
![Page 56: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/56.jpg)
56
-- (Mealy Machine of Sequence Recognizer)library IEEE;use IEEE.std_logic_1164.all;
entity SeqRec_Mealy isport (reset, clk, w: in std_logic; z: out std_logic);end entity SeqRec_Mealy;
architecture behavioral of SeqRec_Mealy is type statetype is (A, B); -- define new type signal present_state, next_state: statetype;Begin
clk_process: process(reset,clk) begin if reset = ‘1’ then -- Check for reset and initialize state present_state <= A; Elsif (rising_edge(clk)) then -- wait until the rising edge present_state <= next_state; end if;end process clk_process;
end architecture behavioral;
next_out_process: process(present_state,w) isbegin case present_state is -- depending upon current state when A => -- set output signals and next state if w = '0' then next_state <= A; z <= ‘0'; else next_state <= B; z <= '0'; end if; when B => if w = '1' then next_state <= B; z <= ‘1'; else next_state <= A; z <= ‘0'; end if; end case; end process next_out_process;
A B
w=1/z=0
w=0/z=0
Reset
w=0/z=0 w=1/z=1
![Page 57: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/57.jpg)
57
Sequence Recognizer (Moore)Sequence Recognizer (Moore)
A/z=0 B/Z=0
C/z=1
w=1
w=0
w=1w=0
w=1
w=0
Reset
Clk: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1z: 0 0 0 0 0 1 0 0 1 1 0
![Page 58: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/58.jpg)
58
Moore: ImplementationMoore: Implementation
A/z=0 B/Z=0
C/z=1
w=1
w=0
w=1w=0
w=1
w=0
Reset
Clk:
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 0 1 1 0
![Page 59: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/59.jpg)
-- (Moore Machine of Sequence Recognizer)library IEEE;use IEEE.std_logic_1164.all;
entity SeqRec_Moore isport (reset, clk, w: in std_logic; z: out std_logic);end entity SeqRec_Moore;
architecture behavioral of SeqRec_Moore is type statetype is (A, B,C); -- define new type signal present_state, next_state: statetype;Begin
clk_process: process( reset, clk) begin if reset = ‘1’ then -- Check for reset and initialize state present_state <= A; Elsif (rising_edge(clk)) then -- wait until the rising edge present_state <= next_state; end if;end process clk_process;
next_state_process: process( present_state, w) isbegin case present_state is -- depending upon current state when A => -- set next state if w = '0' then next_state <= A; else next_state <= B; end if; when B => if w = ‘0' then next_state <= A; else next_state <= C; end if; when C => if w = ‘0’ then next_state <= A; else next_state <= C; end case; end process next_state_process;
output_process: process( present_state) is begin case present_state is -- depending upon current state when A => -- set output signals z<= ‘0’; when B => z<= ‘0’; when C => z<= ‘1’; end case; end process output_process;End architecture behavioral,
A/z=0 B/Z=0
C/z=1
w=1
w=0w=1w=0
w=1
w=0
Reset
59
![Page 60: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/60.jpg)
![Page 61: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/61.jpg)
61
T Flip Flop AnalysisT Flip Flop Analysis
Analysis of a sequential circuit with T flip flops follows the same procedure outlined for JK flip flops.
The next state values in the state table can be obtained by using the characteristic table or the characteristic equation Q(t + 1) = T Q = T’Q + TQ’
![Page 62: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/62.jpg)
62
T Flip Flop Analysis ExampleT Flip Flop Analysis Example
T
T
yA
B
R
R
x
CLK Reset
TA = Bx TB = x Y = AB
![Page 63: ENG241 Digital Design Week #7 Sequential Circuits (Part B)](https://reader035.vdocuments.site/reader035/viewer/2022062906/5a4d1b337f8b9ab05999be69/html5/thumbnails/63.jpg)
63
T Flip Flop Analysis State TableT Flip Flop Analysis State Table
TA = Bx TB = x Y = AB
A(t + 1) = TA A = Bx A B(t + 1) = TB B = x B