energy-efficient stanford university design...
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Stanford University
Department of Electrical Engineering2011.03.10Center for Integrated Systems
Emerging Non-volatile Memory:Energy-efficient Design with
Carbon Nano-materials
Ethan C. Ahn, Ph.D.Electrical Engineering, Stanford University, CA, U.S.A.
IEEE SFBA Nanotechnology Council, Sep. 15, 2015
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong2
Data sources: AMD, Koomey et al. (2011)
50 years of Moore’s law, “how about energy?”
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong3
“Technology node transitions (volume production)”
Ethan C. Ahn 2015. 09. 15.
Slowing below 32 nm
?
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong4
“What’s the difference?”
vs.
$ 299 $ 399Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong5
vs.
16 GB 64 GBEthan C. Ahn 2015. 09. 15.
“Adding more NAND”
(DRAM + NAND) (DRAM + MORE NAND)
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong6
Emerging non-volatile memory (NVM); sub-10 nm scalability & low cost (<0.1$/GB)
3D DRAM (TSV)
SK Hynix, 2013 (product) Toshiba, 2009(32 Gb-chip prototype)
3D NAND- Tohiba (BiCS)- Sandisk (BiCS)- Samsung (TCAT)- SK-Hynix- Micron- …
“Fundamental solution”
“New tricks to further increase density”
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong7
More than 50% powerconsumed by memory
Ref: ITRS 2011 Edition (System Drivers)
Memory: Limiting factor for energy-efficient system
Memory Static Power
(Consumer Portable Chips)
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong8
“New” Players in NVM
filamentoxygen ion
Top Electrode
Bottom Electrode
metaloxide
oxygenvacancy
Bottom Electrode
Top Electrode
oxideisolation
switchingregion
phase change material
filament
Bottom Electrode
solidelectrolyte
Active Top Electrode
metalatoms
STT-MRAM CBRAMRRAMPCMSpin torque transfer magnetic
random access memoryPhase change
memoryResistive switching
random access memoryConductive bridge
random access memory
Soft Magnet
Pinned Magnet
tunnel barrier (oxide)
current
Random access, non-volatile, no erase before write
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong9
Nothing fasterthan STT-MRAMNothing fasterthan STT-MRAM
Speed limitedby physicsSpeed limitedby physics
Energy vs Speed Trade-Off @ Device Level
Wong and Ahn et al. “Stanford Memory Trends”, https://nano.stanford.edu
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong10
1. Energy-efficient Cell design
2. Energy-efficient Architecture design
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong11
PCM: Phase-change memory (PRAM/PCRAM)
HDDNAND/NOR
DRAMSRAMCPU
volatileworkingmemory
nonvolatile(storage)
Speed
Density(Cost)
Phase-Change Memory (PCM)
Packaged MCP that includes 512 Mb PCM(NOR-compatible, Samsung, 2010)
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong12
PCM at a glance: Based on Joule-heating
Poly-CrystallineAmorphous
High Resistivity Low Resistivity
Annealing(Crystallization/SET)
Melt-quenched(Amorphization/RESET)
‘0’ State ‘1’ State
Time
Tmelt
Tcrys
Read
SET pulse
RESET pulse
Troom
Programming region(amorphous)
Oxide isolationBottom Electrode
Top Electrode
Phase-change material(GeSbTe, etc.)
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong13
PCM: Key challenges and issues
Physics of threshold switching, crystallization, etc. High write latency (due to long crystallization time) Cost-effective array architecture High programming (RESET) current Resistance drift (difficulty in MLC) Cross-talk (thermal disturbance) etc.
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong14
PCM: Key challenges and issues
Physics of threshold switching, crystallization, etc. High write latency (due to long crystallization time) Cost-effective array architecture High programming (RESET) current Resistance drift (difficulty in MLC) Cross-talk (thermal disturbance) etc.
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong15
“How hot is Ge2Sb2Te5?” Melt(RESET)
Crystallize(SET)
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong16
Toward lower IRESET: Materials EngineeringExample:Recent studies with GeTe/Sb2Te3 super-lattice structure
IPCM (Interfacial PCM)(R.E. Simpson, Nature Nanotech. 6, 2011)
Charge-injectionSuper-lattice PCM(N. Takaura, VLSI 2013)
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong17
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong18
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Generated heat
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong19
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Heat dissipated during RESETin a typical mushroom PCM cell
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
Q1
Q1 Used for switching
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong20
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Heat dissipated during RESETin a typical mushroom PCM cell
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
Q1
Q1 Used for switching
Q2
Q2 Stored in the heater
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong21
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Heat dissipated during RESETin a typical mushroom PCM cell
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
Q1
Q1 Used for switching
Q2
Q2 Stored in the heater
Q3
Q3 Diffused into oxide
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong22
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Heat dissipated during RESETin a typical mushroom PCM cell
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
Q1
Q1 Used for switching
Q2
Q2 Stored in the heater
Q3
Q3 Diffused into oxide
Q4
Q4 Flows into the metal(at the bottom)
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong23
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Heat dissipated during RESETin a typical mushroom PCM cell
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
Q1
Q1 Used for switching
Q2
Q2 Stored in the heater
Q3
Q3 Diffused into oxide
Q4
Q4 Flows into the metal(at the bottom)
Q5
Q5
Diffused into surroundingGST (crystalline)
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong24
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Heat dissipated during RESETin a typical mushroom PCM cell
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
Q1
Q1 Used for switching
Q2
Q2 Stored in the heater
Q3
Q3 Diffused into oxide
Q4
Q4 Flows into the metal(at the bottom)
Q5
Q5
Diffused into surroundingGST (crystalline)
Q6
Q6
Flows into the metal(at the top)
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong25
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Heat dissipated during RESETin a typical mushroom PCM cell
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
Q1
Q2Q3Q4
Q5
Q6Percentiles (%)
Q4: 60-72%
Q3: 21-25%
Q5 + Q6: 3-17%
“Only a very small fraction (< 1 %)of the generated heat is actuallyused in the active region”
Q2: 0.2%
Q1 S. M. Sadeghipour et al., ITHERM 2006
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong26
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Heat dissipated during RESETin a typical mushroom PCM cell
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
“Only a very small fraction (< 1 %)of the generated heat is actuallyused in the active region”
“WO3 (130 nm)(k ~ 1.6 W/mK)”
F. Rao, Nanotech. 19, 2008
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong27
Toward lower IRESET: Thermal Engineering
Remembering that PCM operation is based on “Joule Heating,”
Heat dissipated during RESETin a typical mushroom PCM cell
Programming region(amorphous)
OxideBottom Electrode(heater plug)
Top Electrode
GST
“Only a very small fraction (< 1 %)of the generated heat is actuallyused in the active region”
“C60 (fullerene)(k ~ 0.4 W/mK)”
C. Kim, APL 92 2008
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong28
“How about graphene?”
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong29
“In-plane” “Out-of-plane”
The Janus faces of graphene
Ethan C. Ahn 2015. 09. 15.
See references[1] Pop et al. MRS Bull. 2012[2] Guzman et al. ITherm. 2014[3] Koh et al. Nano Lett. 2010[4] Mak et al. APL 2010
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong30
Graphene as a thermal barrier: TDTR measurements
Q1: Is a single-layer graphene good as a thermal barrier?(Is a single-layer graphene thermally-resistive well enough?)
0 1 2 3 4
0.6
0.7
0.8
0.9
1.0
1.1
Nor
mal
ized
Ref
lect
ance
Time (ns)
Al/GST/SiO2/SiAl/GST/SLG/SiO2/Si
“TDTR (Time Domain ThermoReflectance)”
Slower thermal decay with SLG
Larger Thermal Boundary Resistance
A1: YES
Ethan C. Ahn 2015. 09. 15.
Ahn et al. Nano Letters 2015
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong31
Graphene as a thermal barrier: TDTR measurements
Q1: Is a single-layer graphene good as a thermal barrier?(Is a single-layer graphene thermally-resistive well enough?)
0 1 2 3 4
0.6
0.7
0.8
0.9
1.0
1.1
Nor
mal
ized
Ref
lect
ance
Time (ns)
Al/GST/SiO2/SiAl/GST/SLG/SiO2/Si
“TDTR (Time Domain ThermoReflectance)”
Slower thermal decay with SLG
Larger Thermal Boundary Resistance
A1: YES
ΔTBR (m2K/GW)= 32 +/- 10 for as-dep. GST
44 +/- 3 for crystalline GST
Q2: HOW LARGE?A2:
Ethan C. Ahn 2015. 09. 15.
Ahn et al. Nano Letters 2015
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong32
GST (10 nm)Pt/Ti/TiN (50 nm)
SLG (Single-Layer Graphene)
W (30 nm)
SiO2 (30 nm)SiO2 (100 nm)
GND
W via
Vtop
wSLG
PCM heat plug (W)
G-PCM: Device structure
Ahn et al. Nano Letters 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong33
GST (10 nm)Pt/Ti/TiN (50 nm)
SLG (Single-Layer Graphene)
W (30 nm)
SiO2 (30 nm)SiO2 (100 nm)
GND
W via
Vtop
wSLG
PCM heat plug (W)
G-PCM: Device structure
Active device region Ahn et al. Nano Letters 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong34
GST (10 nm)Pt/Ti/TiN (50 nm)
SLG (Single-Layer Graphene)
W (30 nm)
SiO2 (30 nm)SiO2 (100 nm)
GND
W via
Vtop
wSLG
PCM heat plug (W)
G-PCM: Raman & TEM studies
Ahn et al. Nano Letters 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong35
G-PCM: IRESET of traditional PCM
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0.00.51.01.52.02.53.03.5
IR
PCM (wB.E. = 200 nm)
Res
ista
nce
(M
)
Current (mA)
trise/twidth/tfall= 10ns/100ns/10ns
twidth
trise tfall
a-GST
c-GST
Heater (W plug)
SiO2
T.E.
B.E.
“PCM”SET
RESET
Ahn et al. Nano Letters 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong36
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0.00.51.01.52.02.53.03.5
IR
G-PCM (A)(wSLG = 1 m)
PCM (wB.E. = 200 nm)
Res
ista
nce
(M
)
Current (mA)“G-PCM (A)”Heater (W plug)
SiO2
T.E.
B.E.
wSLG
c-GST
a-GSTSLG
G-PCM: IRESET of GPCM (A) – Control sample
Ahn et al. Nano Letters 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong37
G-PCM: IRESET of GPCM (B) – Optimal design
“G-PCM (B)”Heater (W plug)
SiO2
T.E.
B.E.
wSLG
c-GST
a-GSTSLG
Ahn et al. Nano Letters 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong38
G-PCM: Verifying endurance is of great importance“Programming endurance” “Resistance distribution”
100 101 102 103 104 1050.01
0.1
1
10
LRS
200 nm PCM100 nm PCM50 nm PCM
Res
ista
nce
(M
)
Endurance Cycle
HRS
0.01 0.1 10
20
40
60
80
100
50 nm
100 nm
LRS HRSCum
ulat
ive
Perc
enta
ge (%
)
Resistance (M)
200 nm
(wB.E.)
100 101 102 103 104 1050.01
0.1
1
10
LRS
200 nm GPCM (B)100 nm GPCM (B)50 nm GPCM (B)
Res
ista
nce
(M
)
Endurance Cycle
HRS
0.01 0.1 10
20
40
60
80
100
50 nm
100 nm
LRSHRSC
umul
ativ
e Pe
rcen
tage
(%)
Resistance (M)
200 nm
(wB.E.)
PCM
G-PCM (B)
Ahn et al. Nano Letters 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong39
1. Energy-efficient Cell design
2. Energy-efficient Architecture design
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong40
RRAM: Resistive (switching) RAM or Metal-oxide RAM
Panasonic, 2013(Embedded)
Crossbar, 2014
HDDNAND/NOR
DRAMSRAMCPU
volatileworkingmemory
nonvolatile(storage)
Speed
Density(Cost)
RRAM
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong41
RRAM: Emerging candidate for sub-10 nm NVM
2000 2002 2004 2006 2008 2010 2012
0
100
200
300
400
500
600
700N
umbe
r of P
ublic
atio
ns
Year P. Wong, Proc. IEEE, 2012
HfOx, AlOx,TaOx, ZnO,etc.
“Simple device structure”
“I-V (hysteresis)”
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong42
RRAM: Emerging candidate for sub-10 nm NVM
2000 2002 2004 2006 2008 2010 2012
0
100
200
300
400
500
600
700N
umbe
r of P
ublic
atio
ns
Year Wong, Proc. IEEE, 2012
“Less than 10 X 10 nm2 RRAM”
B. Govoreanu et al. (IMEC),IEDM 2011
Stanford (2013)
Z. Zhang, EDL 34 2013
W. Yi, IEDM 2013
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong43
RRAM: Key attributes (electrical performance) High endurance (> 1012 cycles) with MLC High speed (< 1 ns)
H. Y. Lee, IEDM 2010
Low programming voltage, current, and powerEstimated power:< 100 nW (10 fJ per bit)
C.-L. Tsai, ACS Nano 7, 2013
CMOS compatible Low temperature High degree of freedom
(engineering design) …
C.-W. Hsu, VLSI 2013
W. Kim, VLSI 2011
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong44
RRAM: Key challenges and issues
Physics of resistive switching and conduction Array architecture Killer application
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong45
RRAM: Key challenges and issues
Physics of resistive switching and conduction Array architecture Killer application
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong46
July 2015Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong47
July 2015Ethan C. Ahn 2015. 09. 15.
3D X-point
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong48
RRAM array: Cross-point structure
“attractive,” due to Easy to fabricate Small cell size: 4F2
Potential for 3D stacking(4F2/N, N = number of layers)
(WLs)
(BLs)
2F
2F
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong49
RRAM array: Cross-point structure
“attractive,” due to Easy to fabricate Small cell size: 4F2
Potential for 3D stacking(4F2/N, N = number of layers)
“problematic,” due to Sneak path problem- Increased power consumption- Reduced write/read margin(limiting maximum allowablearray size)
2F
2F
(WLs)
(BLs)
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong50
RRAM array: Cross-point structure
“attractive,” due to East to fabricate Small cell size: 4F2
Potential for 3D stacking(4F2/N, N = number of layers)
“problematic,” due to Sneak path problem- Increased power consumption- Reduced write/read margin(limiting maximum allowablearray size)
2F
2F
We need “Selection Device”to cut-off sneak leakage current
(WLs)
(BLs)
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong51
“What selector will be the best choice for you?”
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong52
Carbon nanotube field-effect transistors (CNFETs)
Schematic representation of CNFET
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong53
Carbon nanotube field-effect transistors (CNFETs)
Schematic representation of CNFET
Rolling up a sheet of graphene
Ref: J. Wilder et al, Nature 391, 1998
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong54
Carbon nanotube field-effect transistors (CNFETs)
Ref: J. Wilder et al, Nature 391, 1998
Schematic representation of CNFET
Rolling up a sheet of graphene
“Why CNTs to replace Si?”Ballistictransport
Ultra-thinbody
Higher on-currentLower operating voltage
Aggressive scalingExcellent electrostatic control
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong55
High forward-current (Ion) densities (Jon)to program aggressively scaled memory deviceJon > 10 MA/cm2
High On/off ratio (Ion/Ioff)to have high selectivity of memory bitsIon/Ioff > 106
Low off-current (Ioff)to accommodate un- and half-selected cellsIoff < 10 pA
Low processing temperature (T)to allow 3D stackingT < 300 °C
Bipolar operationto allow for best-of-breed RRAMSymmetric I-V at both polarities
+ “small device area”
CNFET: Ideal selection device for memory array
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong56
1TnR array: Based on CNFET selection device
*R.S.L. (Resistive Switching Layer)- Metal-oxide for RRAM- Phase-change material for PCMAhn et al. VLSI 2014
Ahn et al. IEEE TED 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong57
1TnR array: Reduced sneak leakage
“Sneak leakage is much reduced from 2D to 1D,”as it is confined within the 1D CNT channel
“selected WL”
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong58
1TnR: (1) Requires NO additional contacts/wiring
“CNFET selector is tightly integrated, with CNT as B.E.”Ahn et al. VLSI 2014Ahn et al. IEEE TED 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong59
1TnR: (2) Rectangular array preferred
Ahn et al. VLSI 2014Ahn et al. IEEE TED 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong60
Electrical results: IVs of fabricated CNFETs
High current-drive (> 20 MA/cm2)Good electrostatic control by gateNear-symmetric I-V (bipolar)
High on/off ratio (105 ~ 107)Low leakage current < 10 pA(even at high Vd)
Ethan C. Ahn 2015. 09. 15.
Ahn et al. IEEE TED 2015
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong61
Integration: CNFET + Memory = 1TnR“Integrating with Al2O3-based RRAM”
“Integrating with PCM (GST)”
Ahn et al. IEEE TED 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong62
Electrical results: 1TnR RRAM – Selective switching
-5 -4 -3 -2 -1 0 1 2 3 4 510-9
10-7
10-5
10-3
10-1
101
Selected CellNon-selected Cell
(as-dep.)Non-selected Cell
(LRS or HRS)
Cur
rent
(I)[
A]
Top Electrode Voltage (Vtop) [V]
Forming should not occur, as the turned-offCNFET is NOT able to carry high currents
CNFET: OFF
(DC)
(VWL = + 2V)
“n = 1 cell is NOT selected”
Ethan C. Ahn 2015. 09. 15.
Ahn et al. IEEE TED 2015
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong63
-5 -4 -3 -2 -1 0 1 2 3 4 510-9
10-7
10-5
10-3
10-1
101
Selected CellNon-selected Cell
(as-dep.)Non-selected Cell
(LRS or HRS)
Cur
rent
(I)[
A]
Top Electrode Voltage (Vtop) [V]
The cell is not programmable, as the voltagemostly drops across more-resistive CNFET
CNFET: OFF
Electrical results: 1TnR RRAM – Selective switching(DC)
(VWL = + 2V)
“n = 2 cell is NOT selected”
Ethan C. Ahn 2015. 09. 15.
Ahn et al. IEEE TED 2015
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong64
-5 -4 -3 -2 -1 0 1 2 3 4 510-9
10-7
10-5
10-3
10-1
101
Selected CellNon-selected Cell
(as-dep.)Non-selected Cell
(LRS or HRS)
Cur
rent
(I)[
A]
Top Electrode Voltage (Vtop) [V]
Forming
Vform
“CNFET: ON”
Electrical results: 1TnR RRAM – Selective switching(DC)
(VWL = - 5V)
“n = 3 cell is selected”
Ethan C. Ahn 2015. 09. 15.
Ahn et al. IEEE TED 2015
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong65
“CNFET: ON”
Electrical results: 1TnR RRAM – Selective switching(DC)
-5 -4 -3 -2 -1 0 1 2 3 4 510-9
10-7
10-5
10-3
10-1
101
HRS
Selected CellNon-selected Cell
(as-dep.)Non-selected Cell
(LRS or HRS)
RESET
Cur
rent
(I)[
A]
Top Electrode Voltage (Vtop) [V]
Forming
Vform
LRS“n = 3 cell is selected”
(VWL = - 5V)
Ethan C. Ahn 2015. 09. 15.
Ahn et al. IEEE TED 2015
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong66
-5 -4 -3 -2 -1 0 1 2 3 4 510-9
10-7
10-5
10-3
10-1
101
Selected CellNon-selected Cell
(as-dep.)Non-selected Cell
(LRS or HRS)
SET
RESET
Cur
rent
(I)[
A]
Top Electrode Voltage (Vtop) [V]
Forming
Vform
“CNFET: ON”
Electrical results: 1TnR RRAM – Selective switching(DC)
“n = 3 cell is selected”
(VWL = - 5V)
Ethan C. Ahn 2015. 09. 15.
Ahn et al. IEEE TED 2015
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong67
Semiconducting CNT
GND
I-VBL = Vdd
VWL= Vdd (ON)
Gate oxideE-field
Resistive-switching layer(Oxide), HRS -> LRS
Critical roles of CNTs
“selected cell case”
I+
RRAM CNT
~Vdd
>>
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong68
Critical dimension: < 5 nm2
Ethan C. Ahn 2015. 09. 15.
Ref: F. Xiong et al, Nano Letters 13, 2013
“PCM reset current scales withthe effective contact area”
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong69
Critical dimension: < 5 nm2
Ethan C. Ahn 2015. 09. 15.
Ref: F. Xiong et al, Nano Letters 13, 2013
“Sub-1 µA RESET current PCMintegrated into the 1TnR array”
(=CNT)
This work (Ahn 2015)
1TnR PCM
Ahn et al. IEEE TED 2015
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong70
Electrical results: 1TnR RRAM – Pulsed endurance
Al2O3 RRAM Low programming power Size of CF: small
(1)
(0)
Wong, Proc. IEEE, 2012
oxygen ionoxygen vacancy
Ahn et al. IEEE TED 2015
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong71
Energy-efficientNVM design
Cell
Graphene-PCM, Low-power PCMAhn et al. Nano Letters, in press, 2015(DOI: 10.1021/acs.nanolett.5b02661)
1TnR X-point array, 1D selectorAhn et al. IEEE TED 62, 2197, 2015
Architecture
“Summary”
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong72
“Acknowledgement”
Ethan C. Ahn 2015. 09. 15.
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong73
“Closely-related publications”
Ethan C. Ahn 2015. 09. 15.
1. J. Sohn et al. IEDM 2015.
2. H.-Y. Chen et al. VLSI 2014.
3. S. Yu et al. ACS Nano 7(3), 2320, 2013.
4. Liang et al. ACM JETC 9(1), 2013.
3D Vertical RRAM
Wire Scaling
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong74 Ethan C. Ahn 2015. 09. 15.
Ethan Ahn, Stanford University Ph.D. Dissertation(available online at http://purl.stanford.edu/fp960bw6447)
“Which memory?”
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong75 Ethan C. Ahn 2015. 09. 15.
“Just imagine”
Wearable tech gets stylish (Apple, Aug. 2014)
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong76 Ethan C. Ahn 2015. 09. 15.
“Just imagine”
Wearable tech gets stylish (Apple, Aug. 2014)
Graphene/CNTinterconnects?
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong77 Ethan C. Ahn 2015. 09. 15.
“Just imagine”
Wearable tech gets stylish (Apple, Aug. 2014)
Graphene/CNTinterconnects?
All-spin low powermicrochip?
Stanford University
Department of Electrical Engineering2014.02.18H.-S. Philip Wong78 Ethan C. Ahn 2015. 09. 15.
“Just imagine”
Wearable tech gets stylish (Apple, Aug. 2014)
Graphene/CNTinterconnects?
All-spin low powermicrochip?
RRAM-basedstorage device?