energy efficient circuit design and the future of power...

Energy Efficient Circuit Energy Efficient Circuit Design and the Future of Design and the Future of

Power DeliveryPower Delivery

Greg TaylorGreg Taylor

EPEPS 2009EPEPS 2009

OutlineOutline

•• Looking backLooking back

•• Energy efficiency in CMOSEnergy efficiency in CMOS

•• Side effectsSide effects

•• SuggestionsSuggestions

2

•• SuggestionsSuggestions

•• ConclusionConclusion

Energy Efficient Circuit Design and the Future of Power Delivery

Looking BackLooking Back

•• Microprocessor scaling has been a Microprocessor scaling has been a topic of interest both at EPEP and to the topic of interest both at EPEP and to the IC design community in generalIC design community in general

–– MOS MOS scaling scaling helps set our expectations for helps set our expectations for

3

–– MOS MOS scaling scaling helps set our expectations for helps set our expectations for the futurethe future

–– Microprocessors tend to bound the high Microprocessors tend to bound the high power density edge of the product spacepower density edge of the product space


EPEP 2003EPEP 2003

•• In his “Architecting Interconnect” address, In his “Architecting Interconnect” address, Peter Peter HofsteeHofstee identified the major challenges identified the major challenges facing microprocessors:facing microprocessors:

–– Software inertiaSoftware inertia

4

–– I/O bandwidthI/O bandwidth

–– Power deliveryPower delivery

–– CoolingCooling

•• The future is simpler architecture and more The future is simpler architecture and more corescores


SPI 2004SPI 2004

•• In my “Design Challenges of the 90 nm In my “Design Challenges of the 90 nm Pentium® 4 Processor” address Pentium® 4 Processor” address highlighted similar issues:highlighted similar issues:


5


–– CoolingCooling

–– VariationVariation

–– Gate leakageGate leakage

•• But scaling will continueBut scaling will continue


Power density Power density vsvs CDCD

Pentium® 4 processorPentium® 4 processor

100100

10001000

W/c

mW

/cm

22

Nuclear ReactorNuclear Reactor

Rocket NozzleRocket Nozzle

6

Pentium® 4 processorPentium® 4 processor

Pentium® III processorPentium® III processorPentium® II processorPentium® II processor

Pentium® Pro processorPentium® Pro processor

Pentium® processorPentium® processor

i486i486

i386i38611

1010

0.010.010.10.1111010

CD (CD (µµµµµµµµm)m)

W/c

mW

/cm

Hot PlateHot Plate


Core 2 Duo® processorCore 2 Duo® processor

Atom™ ProcessorAtom™ Processor

Energy Energy Efficiency Efficiency in CMOSin CMOS

•• CMOS power is determined by C, V, f:CMOS power is determined by C, V, f:

–– Power ~ CVPower ~ CV22f + f + IIleakleakVV

•• Process technology can improve CProcess technology can improve C

•• Reducing V Reducing V reduces performancereduces performance

7

•• Reducing V Reducing V reduces performancereduces performance

•• Delay ~ C * Delay ~ C * VccVcc/(/(VccVcc –– VVtt))αααααααα

•• But But it reduces power even fasterit reduces power even faster

–– IIleakleak is also a function of Vis also a function of V


Frequency and Power MeasurementsFrequency and Power Measurements

65nm CMOS, 5065nm CMOS, 50°°CCM

axim

um

Fre

qu

en

cy (

MH

z)

Maxim

um

Fre

qu

en

cy (

MH

z)

To

tal P

ow

er

(mW

)To

tal P

ow

er

(mW

)

101

103

104

102

10-1

1

101

102

8

•• From: A 320mV 56From: A 320mV 56µµW 411GOPS/Watt W 411GOPS/Watt UltraUltra--Low Voltage Motion Estimation Low Voltage Motion Estimation Accelerator in 65nm CMOS Accelerator in 65nm CMOS –– ISSCC ‘08ISSCC ‘08

Maxim

um

Fre

qu

en

cy (

MH

z)

Maxim

um

Fre

qu

en

cy (

MH

z)

To

tal P

ow

er

(mW

)To

tal P

ow

er

(mW

)

Supply Voltage (V)Supply Voltage (V)

1

101

10-2

10-1

0.2 0.4 0.6 0.8 1.0 1.2 1.4

EnergyEnergy--Efficiency MeasurementsEfficiency Measurements

9.6X9.6X

Acti

ve L

eakag

e P

ow

er

Acti

ve L

eakag

e P

ow

er

(mW

)(m

W)

En

erg

y E

ffic

ien

cy

En

erg

y E

ffic

ien

cy

(GO

PS

/Watt

)(G

OP

S/W

att

)65nm CMOS, 5065nm CMOS, 50°°CC

101

1

10-1150

225

300

375

450

9

•• From: A 320mV 56From: A 320mV 56µµW 411GOPS/Watt W 411GOPS/Watt UltraUltra--Low Voltage Motion Estimation Low Voltage Motion Estimation Accelerator in 65nm Accelerator in 65nm CMOS CMOS –– ISSCC ‘08ISSCC ‘08

320mV320mV


Acti

ve L

eakag

e P

ow

er

Acti

ve L

eakag

e P

ow

er

En

erg

y E

ffic

ien

cy

En

erg

y E

ffic

ien

cy

(GO

PS

/Watt

)(G

OP

S/W

att

)

10

10-2 0

75

150

0.2 0.4 0.6 0.8 1.0 1.2 1.4

Voltage ScalingVoltage Scaling10

Vo

lta

ge

(V

)

2

3

4

5

0.7x/gen0.7x/gen

10Energy Efficient Circuit Design and the Future of Power Delivery

1

2000 1000 800 500 350 250 180 130 90 65 45

CD (nm)

•• Voltage scaling has slowed on recent Voltage scaling has slowed on recent technologiestechnologies

–– This is the technology maximum voltageThis is the technology maximum voltage

Side EffectsSide Effects

•• Reduced Reduced voltage voltage operation increases operation increases sensitivity to temperature and within die sensitivity to temperature and within die variationvariation

–– RDF sensitivity of state elements is RDF sensitivity of state elements is

11

–– RDF sensitivity of state elements is RDF sensitivity of state elements is increased requiring redesign or larger increased requiring redesign or larger sizessizes

–– SRAM SRAM VminVmin tends to increase on more tends to increase on more aggressive technologiesaggressive technologies

–– Combinatorial delay variation is increasedCombinatorial delay variation is increased


Temperature Induced VariationsTemperature Induced Variations65nm CMOS65nm CMOS Typical Die MeasurementsTypical Die Measurements

Maxim

um

Fre

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Maxim

um

Fre

qu

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cy

(MH

z)

(MH

z)

Frequency variation Frequency variation across 0across 0--110110°°CC

103

104

102

±±5%5%

110110°°CC

00°°CC5050°°CC

12

•• Frequency variation across 0Frequency variation across 0--110110°°C:C:

–– Increases from Increases from ±±5% at 1.2V to 5% at 1.2V to ±±2X at 320mV2X at 320mV

Maxim

um

Fre

qu

en

cy

Maxim

um

Fre

qu

en

cy


across 0across 0--110110°°CC

320mV320mV


1

101

0.2 0.4 0.6 0.8 1.0 1.2 1.4

±±2X2X

Low Voltage Process VariationsLow Voltage Process VariationsN

orm

ali

zed

Dis

trib

uti

on

No

rmali

zed

Dis

trib

uti

on 65nm CMOS Monte Carlo Simulations, 5065nm CMOS Monte Carlo Simulations, 50°°CC

1.2V1.2VFrequency variation Frequency variation

across fastacross fast--slow skewsslow skews

±±18%18%

±±2X2X

11

13

●● Frequency variation across fastFrequency variation across fast--slow skewsslow skews::

●● Increases from Increases from ±±18% at 1.2V to 18% at 1.2V to ±±2X at 320mV2X at 320mVEnergy Efficient Circuit Design and the Future of Power Delivery

No

rmali

zed

Dis

trib

uti

on

No

rmali

zed

Dis

trib

uti

on

Normalized FrequencyNormalized Frequency

320mV320mV

±±2X2X

00

0.5 1.0 1.5 2.0

Supply Voltage CompensationSupply Voltage Compensation

65nm CMOS, 320mV 65nm CMOS, 320mV Typical DieTypical Die

23M

Hz

23M

Hz

Fre

qu

en

cy (

MH

z)

Fre

qu

en

cy (

MH

z)

Fre

qu

en

cy (

MH

z)

Fre

qu

en

cy (

MH

z)

23M

Hz

23M

Hz

65nm CMOS, 65nm CMOS, 320mV, 50320mV, 50°°CC

14

28

42

56

14

28

42

56

14

•• Adjust supply voltage to maintain constant performanceAdjust supply voltage to maintain constant performance

•• ±±50mV adjustment about 320mV: 50mV adjustment about 320mV:

ðð Nominal 23MHz performance sustained across 0Nominal 23MHz performance sustained across 0--110110°°C C and fastand fast--slow skewsslow skews

23M

Hz

23M

Hz

Temperature (Temperature (°°C)C)

Fre

qu

en

cy (

MH

z)

Fre

qu

en

cy (

MH

z)

Fre

qu

en

cy (

MH

z)

Fre

qu

en

cy (

MH

z)

23M

Hz

23M

Hz

Process SkewProcess SkewSlowSlow TypicalTypical FastFast


00 50 110

0

Other Side EffectsOther Side Effects

•• Very low power delivery impedanceVery low power delivery impedance

•• Granularity: Each core may differGranularity: Each core may differ

•• Stability of state elements: Stability of state elements: VminVmin

–– Some invention neededSome invention needed

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–– Some invention neededSome invention needed

•• TestTest

–– Adaptation to performance, Adaptation to performance, VminVmin

–– Slowest low voltage operation is at coldSlowest low voltage operation is at cold

–– Do we need to operate across the supply Do we need to operate across the supply range?range?


SuggestionsSuggestions

•• Take advantage of many coresTake advantage of many cores

•• Use fine grained power management to Use fine grained power management to overcome within die variationsovercome within die variations

• On die/pkg, point of load regulation

16

• On die/pkg, point of load regulation

• Adaptation is a test challenge


VRVRVRVRVRVRVRVRVRVRVRVR

CoreCoreCoreCoreCoreCoreCoreCoreCoreCoreCoreCore

I/OI/O

PowerPower

How Will This Change Power How Will This Change Power Delivery?Delivery?

•• Regulator Regulator inefficiency moves on dieinefficiency moves on die

++ Under the big heat sinkUnder the big heat sink

–– But the hot spot gets But the hot spot gets hotterhotter

++ Reducing voltage wherever possible Reducing voltage wherever possible

17

++ Reducing voltage wherever possible Reducing voltage wherever possible reduces overall powerreduces overall power



•• Eliminate multiple regulators from the Eliminate multiple regulators from the motherboardmotherboard

++ Fewer componentsFewer components

++ Higher voltage, lower current requirementsHigher voltage, lower current requirements

18

++ Higher voltage, lower current requirementsHigher voltage, lower current requirements



•• Regulators are constant power loadsRegulators are constant power loads

–– Which means negative input impedanceWhich means negative input impedance

++ Power supply Power supply and package designers and package designers still still have interesting work to dohave interesting work to do

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have interesting work to dohave interesting work to do



•• Regulators will be needed inside the Regulators will be needed inside the die/packagedie/package

–– Need to deal with “high” voltages and Need to deal with “high” voltages and precision analog electronics on precision analog electronics on

20

precision analog electronics on precision analog electronics on microprocessorsmicroprocessors

++ New power management New power management opportunities will ariseopportunities will arise


ConclusionConclusion

•• Power delivery, cooling, and variation Power delivery, cooling, and variation are still challenges for many core chipsare still challenges for many core chips

•• Power Power efficient performance has efficient performance has become a key processor metricbecome a key processor metric

21

become a key processor metricbecome a key processor metric

•• Operation at very low Operation at very low supply voltage supply voltage offers significant improvement in power offers significant improvement in power efficiencyefficiency

•• These combine well with the previously These combine well with the previously identified manyidentified many core directioncore direction


ConclusionConclusion (cont)(cont)

•• Low Low voltage voltage operation significantly operation significantly exacerbates within die variationexacerbates within die variation

•• Distributed, on die supply regulation Distributed, on die supply regulation can compensate for this variationcan compensate for this variation

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can compensate for this variationcan compensate for this variation

–– Bringing new design, Bringing new design, manufacturing, manufacturing, and and test challengestest challenges


Thank YouThank You


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