ENEE313 Homework #11 Solutions

1. (11.1) Qualitative MOSFET questions

(a) The cross section for an N-MOSFET under zero gate voltage is shown below:

In the above case, all terminal voltages are zero (grounded).

In the next graph, when the gate voltage is large enough to establish a channel, electrons

are pulled from the source into the channel.

(b) Inversion layer: The inversion layer in an N-MOSFET is a conducting channel which contains

electrons that are attracted by a positive gate-source voltage. This gate-source voltage

forward biases the source (n) – substrate (p) junction, causing electrons diffusing across the

junction, and the associated E field keeps them near the surface. The surface of the P-type

substrate is “inverted” to contain mobile electrons. These channel electrons will flow to the

drain under a positive drain-source voltage. No gate current is required to maintain the

inversion layer since the gate oxide (insulator) blocks any carrier flow. Thus, the gate

voltage controls the formation of an inversion layer, which in turn forms the flow of

electrons from the source to the drain once an additional voltage is applied at the drain

terminal. In other words, the MOSFET is a voltage-controlled current source, and the

inversion layer is the key concept connecting the input (gate control voltage) and response

(drain output current).

Carrier types: Mobile carriers in N-channel MOSFETs are electrons. Mobile carriers in P-

channel MOSFETs are holes.

(c) The higher the gate voltage is applied, the more change in the substrate (body) surface

potential, and the deeper the inversion gets into. This results in higher electron

concentration in the inversion layer (channel). Since the channel current is mainly drift

current under the drain-source field, it depends on the carrier concentration by:

𝐽𝑐ℎ𝑎𝑛𝑛𝑒𝑙 = 𝐽𝑑𝑟𝑖𝑓𝑡 ∝ 𝑛𝑐ℎ𝑎𝑛𝑛𝑒𝑙

The higher the electron concentration, the higher the channel current.

2. (11.2) Qualitative description of MOSFET operation

The MOSFET is usually considered to be a three-terminal device. The three terminals are the

gate, source, and drain. (The MOSFET also has a fourth terminal called the body, but the

body is usually shorted to the source or grounded, it thus plays a secondary role, and we

won’t worry about it too much in this context.)

One of the key features of the MOSFET is the gate oxide. This is a very thin insulating layer

that separates the gate terminal from the rest of the device. Because of this oxide, when we

apply a DC voltage to the gate, no gate current will flow. Despite many nuances, the general

operation goes as follows.

A voltage applied to the gate terminal and the electric field associated with it control the

current that flows between the drain and the source. This is where the MOSFET gets its

name as a “field-effect transistor”. For an N-channel device, we apply a positive voltage

from the gate to the source. The resulting electric field penetrates the oxide and then

forward biases the source-substrate n-p junction near the top of the device close to the

surface (between the oxide and the silicon). Because of the insulating oxide layer, there is

virtually no gate current. This is in contrast to a BJT where there is a DC base current and a

very specific ratio between the base (input) and collector (output) currents.

The electrons that come out of the source then form the conducting channel along the

surface. A positive voltage on the drain terminal reverse biases the drain-substrate n-p

junction near the surface, and the drain field parallel to the surface pulls channel electrons

into the drain, which give rise to the drain current. The drain current is proportional to the

concentration of electrons in the channel, which is controlled mainly by VGS.

3. (11.3) Reason for MOSFET being a field effect device

A MOSFET has a very thin layer of silicon dioxide (SiO2) or other types of dielectric materials

which separates the gate terminal and the rest of the device. Because such oxide layer is

insulating (SiO2 is an insulator), during normal device operation, there is no DC current

flowing through the gate terminal (the input terminal) under DC gate voltages. Thus, the DC

input resistance of a MOSFET is infinity.

In an N-MOSFET, a conducting channel forms when an applied gate voltage and its

associated E field pulls electrons from the source into the substrate near the surface.

Meanwhile, there is no input current at the gate terminal. Therefore, the MOSFET is

completely controlled by the electric field, and the device is a field-effect device. Another

applied voltage at the drain and its associated E field attracts the channel electrons so they

flow into the drain, forming conduction current. Similar things happen with holes in P-

MOSFETs.

On the other hand, in a BJT, the conduction current is formed when the emitter-base

junction is forward biased. Since there is a forward current from the base to the emitter,

the device is not completely controlled by field.

4. (11.4) Threshold voltage

The threshold voltage is the required gate-source voltage 𝑉𝐺𝑆 to be applied to:

1. Induce surface inversion, and

2. Form a channel at the surface of the substrate.

For an N-MOSFET, in the p-type substrate, there are 𝑝0 = 𝑁𝐴 holes and 𝑛0 =𝑛𝑖2

𝑁𝐴 electrons

per unit volume. Also, 𝑛0 ≪ 𝑝0. We know that the substrate potential is:

𝜙𝑝 = −𝑉𝑇 ln (𝑝0

𝑛𝑖) = −𝑉𝑇 ln (

𝑁𝐴

𝑛𝑖)

Which equivalently gives:

𝑝0 = 𝑁𝐴 = 𝑛𝑖𝑒−𝜙𝑝

𝑉𝑇

When the surface potential is changed to 𝜙𝑠 = −𝜙𝑝 by applying a gate voltage equal to the

threshold voltage, the electron concentrations is:

𝑛|𝜙𝑠= 𝑛𝑖𝑒

𝜙𝑠𝑉𝑇 = 𝑛𝑖𝑒

−𝜙𝑝

𝑉𝑇 = 𝑝0

This shows that the electron concentration at the surface is equal to the deep-substrate

hole concentration where the effect from the gate field diminishes. So, the type of the

material has been inverted.

5. (11.5) MOSFET calculations

Given quantities:

𝑁𝐴 = 1017 cm−3

𝑁𝐷−𝑝𝑜𝑙𝑦 = 1019 cm−3

𝑡𝑜𝑥 = 10 nm = 10 × 10−7 cm = 10−6 cm

𝐿 = 0.5 μm = 5 × 10−5 cm

𝑊 = 20 μm = 2 × 10−3 cm

𝜇𝑛 = 500 cm2/V s

𝑉𝑇 = 0.0259 V

(a) Threshold voltage:

𝜙0 = 𝑉𝑇 ln (𝑁𝐴𝑁𝐷−𝑝𝑜𝑙𝑦

𝑛𝑖2 )

𝜙0 = 0.954 𝑉

𝜙𝑝 = −𝑉𝑇 ln (𝑁𝐴

𝑛𝑖)

𝜙𝑝 = −0.418 𝑉

𝐶𝑜𝑥 =𝜖𝑜𝑥

𝑡𝑜𝑥=

3.9 × 8.85 × 10−14 F/cm

10−6 cm

𝐶𝑜𝑥 = 3.45 × 10−7 F/cm2

So, the threshold voltage is:

𝑉𝑇𝐻 =1

𝐶𝑜𝑥[4𝑞𝜖𝑆𝑖𝑁𝐴|𝜙𝑝|]

12 + 2|𝜙𝑝| − 𝜙0

𝑉𝑇𝐻 = 0.363 𝑉

(b) For the linear region, i.e., when 𝑉𝐷𝑆 ≤ 𝑉𝐺𝑆 − 𝑉𝑇𝐻, the drain current is:

𝐼𝐷 = 𝜇𝑛𝐶𝑜𝑥

𝑊

𝐿[(𝑉𝐺𝑆 − 𝑉𝑇𝐻)𝑉𝐷𝑆 −

1

2𝑉𝐷𝑆

2 )]

For the saturation region, i.e., when 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻, the drain current is:

𝐼𝐷 =1

2𝜇𝑛𝐶𝑜𝑥

𝑊

𝐿(𝑉𝐺𝑆 − 𝑉𝑇𝐻)2

The 𝐼𝐷-𝑉𝐷𝑆 graph is shown below:

(c) The depletion region width 𝑥𝑝 under the gate is given by:

𝑥𝑝 = [2𝜖𝑆𝑖

𝑞𝑁𝐴(𝜙𝑠 − 𝜙𝑝)]

1/2

When the surface potential 𝜙𝑠 = 0 V, the equation becomes:

𝑥𝑝 = [2𝜖𝑆𝑖

𝑞𝑁𝐴(−𝜙𝑝)]

12

The substrate potential 𝜙𝑝 = −𝑉𝑇 ln (𝑁𝐴

𝑛𝑖) = −0.4175 𝑉 is calculated in (a), so we get:

𝑥𝑝 = 7.35 × 10−6 cm = 0.0735 μm

(d) When the surface potential 𝜙𝑠 = 0 V, using the value for 𝑥𝑝 from (c) above, the electric

field in the oxide is:

𝐸𝑜𝑥 =𝑞𝑁𝐴𝑥𝑝

𝜖𝑜𝑥

𝐸𝑜𝑥 = 3.41 × 105 V/cm

6. (11.6) Deriving the MOSFET linear region current formula

When the drain-source voltage 𝑉𝐷𝑆 is low, the drain terminal current is mainly drift current.

We start with the drain current density formula (Equation 11.3):

𝐽𝐷𝑆,𝑑𝑟𝑖𝑓𝑡 = 𝑞𝜇𝑛𝑛𝑐ℎ𝐸𝑐ℎ

To get the terminal current in Amperes, multiply the current density per unit area (A/cm2)

by the cross-section area of the conducting channel:

𝐼𝐷 = 𝐴𝑐ℎ 𝐽𝐷𝑆,𝑑𝑟𝑖𝑓𝑡

The cross sectional area is 𝐴𝑐ℎ = 𝑊𝑡𝑐ℎ where 𝑊 is the channel width (perpendicular to

what we drew for the MOSFET “cross section” in Question 1; the “cross sectional area” in

this context refers to a different plane.) and 𝑡𝑐ℎ is the effective thickness of the channel

layer below the surface. Putting things together, we have:

𝐼𝐷 = 𝐴𝑐ℎ 𝐽 = 𝐴𝑐ℎ𝑞𝜇𝑛𝑛𝑐ℎ𝐸𝑐ℎ = 𝑊𝑡𝑐ℎ𝑞𝜇𝑛𝑛𝑐ℎ𝐸𝑐ℎ

𝐼𝐷 = 𝑊(𝑞𝑛𝑐ℎ𝑡𝑐ℎ)(𝜇𝑛𝐸𝑐ℎ)

There are two important components in the above formula:

1. The channel charge density 𝑄𝑐ℎ = 𝑞𝑛𝑐ℎ𝑡𝑐ℎ represents the amount of mobile electrons

per unit surface area capable of forming drain current. Its unit is Coulomb/cm2. It is

mainly controlled by the gate voltage, which gives rise to surface inversion and pulls

electrons across the source-substrate junction, which form the channel.

2. The other term 𝜇𝑛𝐸𝑐ℎ represents the drift velocity, which is apparently controlled by the

channel field 𝐸𝑐ℎ, which is parallel to the channel and the surface.

We continue and derive the low-field drain current formula (Equation 11.8) as follows.

First, treating the MOSFET like a capacitor, the charge stored in it is 𝑄 = 𝐶𝑉. But we want

the result in Coulomb/cm2, so use 𝐶𝑜𝑥 =𝜖𝑜𝑥

𝑡𝑜𝑥 in F/cm2. Also, we need to only count the

conducting (mobile) electrons in the channel and exclude the background charges due to

ionized acceptors; the threshold voltage will do the job. Thus,

𝑄𝑐ℎ = 𝑞𝑛𝑐ℎ𝑡𝑐ℎ = 𝐶𝑜𝑥(𝑉𝐺𝑆 − 𝑉𝑇𝐻)

Next, find the channel field 𝐸𝑐ℎ. From the definition of field and potential, 𝐸𝑐ℎ = −𝑑𝜙

𝑑𝑥.

Neglecting the minus sign (merely indicating direction), under a low drain voltage 𝑉𝐷𝑆, it is

approximated by:

𝐸𝑐ℎ ≈𝑉𝐷𝑆

𝐿

𝐿 is the channel length.

Finally,

𝐼𝐷 = 𝑊(𝑞𝑛𝑐ℎ𝑡𝑐ℎ)(𝜇𝑛𝐸𝑐ℎ) = 𝑊𝑄𝑐ℎ (𝜇𝑛

𝑉𝐷𝑆

𝐿) = 𝑊[𝐶𝑜𝑥(𝑉𝐺𝑆 − 𝑉𝑇𝐻)] (𝜇𝑛

𝑉𝐷𝑆

𝐿)

𝐼𝐷 = 𝜇𝑛𝐶𝑜𝑥

𝑊

𝐿(𝑉𝐺𝑆 − 𝑉𝑇𝐻)𝑉𝐷𝑆

7. (11.7) MOSFET linear region and saturation region

In the case of an N-MOSFET, when a positive gate-source voltage is applied that exceeds the

threshold voltage, surface inversion occurs. Electrons from the source flow into the p-type

body region, forming a channel. In this situation, a positive drain-source voltage and its

associated E-field parallel to the channel pulls mobile electrons to the drain, forming drain

current. It has two operation regions as the following:

When the drain voltage is low 𝑉𝐷𝑆 ≤ 𝑉𝐺𝑆 − 𝑉𝑇𝐻, the drain current 𝐼𝐷 is linearly dependent

on the drain bias as shown in Question 6. Hence, we call it the linear region of operation.

For a relatively large 𝑉𝐷𝑆 (still below 𝑉𝐺𝑆 − 𝑉𝑇𝐻), the I-V characteristic curves transition

away from the “linear” shape as the MOSFET approaches saturation, but we still call this

region of operation the linear region. Increasing 𝑉𝐷𝑆 is associated with linearly increasing

electric field (in the channel’s direction), and the pull of the channel electrons linearly

increases, until we enter the saturation region.

When the drain voltage is high 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻, surface inversion is barely maintained near

the drain, and the channel is considered to be depleted. We call the channel as “pinched

off” under this condition, and the increase in the drain voltage and drain-source field does

not increase the conduction current any more. Thus, we call the channel current as

“saturated”, and the MOSFET is operating in the saturation region. The depletion region

around the drain-body junction is reverse biased, and it is much larger than in the linear

operating region. The extra drain-source voltage in [𝑉𝐷𝑆 − (𝑉𝐺𝑆 − 𝑉𝑇𝐻)] is dropped across

the drain-body depletion region.

8. (11.8) MOSFET small signal model parameters

The two small signal parameters asked about, output resistance 𝑟𝑜 and transconductance

𝑔𝑚 are defined by the small-signal change in the drain current – terminal voltage

relationship (Equation 11.67):

Δ𝐼𝐷 =𝜕𝐼𝐷

𝜕𝑉𝐺𝑆Δ𝑉𝐺𝑆 +

𝜕𝐼𝐷

𝜕𝑉𝐷𝑆Δ𝑉𝐷𝑆

Δ𝐼𝐷 = 𝑔𝑚 Δ𝑉𝐺𝑆 + 𝑔𝑜 Δ𝑉𝐷𝑆

𝑟𝑜 = 𝑔𝑜−1

When the MOSFET operates in the saturation region, we have the drain current formula

with channel modulation effect given as (Equation 11.66):

𝐼𝐷 =𝜇𝑛𝐶𝑜𝑥𝑊

2𝐿(𝑉𝐺𝑆 − 𝑉𝑇𝐻)2(1 + 𝜆 𝑉𝐷𝑆)

The small signal transconductance is defined as:

𝑔𝑚 =𝜕𝐼𝐷

𝜕𝑉𝐺𝑆

𝑔𝑚 =𝜇𝑛𝐶𝑜𝑥𝑊

𝐿(𝑉𝐺𝑆 − 𝑉𝑇𝐻)(1 + 𝜆 𝑉𝐷𝑆)

When the channel length modulation is negligible under many practical circumstances, we

may ignore the “𝜆” for the calculation of 𝑔𝑚. Using the large-signal drain current 𝐼𝐷

(typically achieved by the bias circuit) and ignoring the small effect from the “𝜆” term, we

can re-write the last equation as:

𝑔𝑚 =2𝐼𝐷

(𝑉𝐺𝑆 − 𝑉𝑇𝐻)= √

2𝜇𝑛𝐶𝑜𝑥𝑊𝐼𝐷

𝐿

The small-signal output conductance is defined as:

𝑔𝑜 =𝜕𝐼𝐷

𝜕𝑉𝐷𝑆

=𝜕

𝜕𝑉𝐷𝑆[𝜇𝑛𝐶𝑜𝑥𝑊

2𝐿(𝑉𝐺𝑆 − 𝑉𝑇𝐻)2(1 + 𝜆 𝑉𝐷𝑆)]

𝑔𝑜 =𝜇𝑛𝐶𝑜𝑥𝑊

2𝐿(𝑉𝐺𝑆 − 𝑉𝑇𝐻)2 𝜆

The small-signal output resistance is the reciprocal of the above quantity:

𝑟𝑜 = 𝑔𝑜−1

Using the large-signal drain current 𝐼𝐷 (typically achieved by the bias circuit) and ignoring

the small effect from the “1 + 𝜆” term, we can re-write it as:

𝑟𝑜 = 𝑔𝑜−1 = (𝜆𝐼𝐷)−1

9. (11.9) MOSFET small signal equivalent circuit model parameter calculations

Given quantities are:

𝑉𝐺𝑆 = 2 V

𝑉𝐷𝑆 = 3 V

From Question 5, we know 𝑉𝑇𝐻 = 0.363 V.

Since 𝑉𝐺𝑆 − 𝑉𝑇𝐻 = 2 V − 0.363 V = 1.637 V ≤ 𝑉𝐷𝑆 = 3 V, the MOSFET is operating in

saturation region. Therefore, the drain current is

𝐼𝐷 =𝜇𝑛𝐶𝑜𝑥𝑊

2𝐿(𝑉𝐺𝑆 − 𝑉𝑇𝐻)2 = 0.0093 A

The small-signal transconductance can be found in two ways:

𝑔𝑚 =𝜇𝑛𝐶𝑜𝑥𝑊

𝐿(𝑉𝐺𝑆 − 𝑉𝑇𝐻) = 0.0113 Ω−1

or

𝑔𝑚 =2𝐼𝐷

(𝑉𝐺𝑆 − 𝑉𝑇𝐻)= 0.0114 Ω−1

It is a bit larger due to rounding errors in our previous calculations.

The output transconductance can also be found in two ways:

𝑔𝑜 =𝜇𝑛𝐶𝑜𝑥𝑊

2𝐿(𝑉𝐺𝑆 − 𝑉𝑇𝐻)2 𝜆 = 0.000462 Ω−1

Or with the alternative formula, 𝑔𝑜 = 𝜆𝐼𝐷 = 0.000465 Ω−1 which is a bit larger due to

rounding errors in our previous calculations.

So, the output resistance is:

𝑟𝑜 = 𝑔𝑜−1 = 2.17 kΩ

The gate-source capacitance 𝐶𝑔𝑠 and gate-drain capacitance 𝐶𝑔𝑑 are given by Equations 11.72

and 11.73:

𝐶𝑔𝑠 =2

3𝐶𝑜𝑥𝐿𝑊 = 2.30 × 10−14 F

𝐶𝑔𝑑 = 𝐶𝑜𝑥𝐿𝑑𝑊 = 3.45 × 10−15 F

The small signal equivalent circuit of this N-MOSFET is as follows:

GATE TERMINAL

SOURCE TERMINAL

DRAIN TERMINAL