End to End Self-Heating Analysis Methodology and Toolset for High

Performance Microprocessor DesignsNagu Dhanwada, Leon Sigal, William Dungan, Mike Scheuermann, Arun Joseph, Arjen

Mets, Sungjae Lee, Karl Moody, Shashidhar Reddy, Kartik Acharya, Erich Schanzenbach, Andrew Bianchi, Richard Wachnik, James Warnock, Derrick Smith

IBM Systems Group

Motivation Supplying and dissipating power in a chip has been a

module and chip design issue

Scaled devices with higher power density are hot, especially with large, multi-finger FETs and this can be a reliability issue- Self-heating of devices during normal circuit operation is becoming

significant causing BEOL reliability and EM wear out issues.

Localized self heating is a serious concern that should be managed across IP types by the design methodology in high-performance chip design.- Need to manage how this heat is dissipated through devices, wires,

and substrate

Main Idea Comprehensive Framework containing different

solution approaches to assess and mitigate self -heating issues in high performance designs.

Framework brings together workload specific switching data, detailed power models, and thermal modeling to help assess self heating impacts from an early stage to a detailed sign-off stage.

Encapsulated self heating APIs built on top of the various analysis techniques to guide design optimization and closure tools to be self-heating aware.

Efficient and Accurate in being able to predict overheating at the time of macro construction at a fraction of time with comparable accuracy to detailed field solver based approaches, and hardware measurements.

High Switching Factor Net Identification

Design Construction

And Optimization

Power AnalysisPower Grid Integrity Checking

Self Heating API

Early Self-HeatingAnalysis

Detailed Self-Heating Analysis

Corner Conditions

SignalElectro

MigrationAnalysis

Macro workload

Macro workload

GenerationSystem

Workload

Details: Gate Level Early Self Heating Analysis Activity Processing

Uses activity data generated at higher levels of design hierarchy (unit, core, chip), and generates switching data for the internals of a macro, while considering the mapping between logical and physical hierarchies.

RTH CharacterizationComputes the effective thermal resistance (Rth) from the

schematic / layout of the standard cell considering topology of the cell and the finger, fin count and stores it into the power rule for the standard cell.

Self Heating APICalculates increase in temperature above ambient,

DeltaT  efficiently using thermal resistance, Rth, and the switching information. Computes the power by intelligently using the workload specific switching data along with assertions to ensure adequate coverage. Provides these data efficiently to the various applications like design optimization

Self Heating Aware Design OptimizationDesign optimization step addresses self heating in both

the construction phase and as a fix up step, where the objective would be to address any self heating violations without impacting the timing and with minimal area overhead. Uses the high switching and deltaT information through the self heating API and does steps like sharpening input slews, changing power level of the gates, in order to minimize the self-heating violations.

I

Analytical Model for Self Heating ComputationAnalytical model that computes the deltaT using the area and perimeter component, which makes it possible to compute deltaT with fairly high accuracy to be used during the design construction phase.

Ambient

• Rth is thermal resistance (deg C / W), a constant between device temperature increase and dissipated Power

• DT=Rth x Power

• DT is proportional to the dissipated power with a proportionality constant of Rth

• Gth=1/Rth, thermal conductivity

• Rth x Cth determines self-heating time constant • Cth can be thought of as “heat capacity”

Experimental Results• Accuracy comparison of the deltaT

map generation approaches against a detailed field solver based thermal simulation approach (ANSYS Icepak TM) on two gate level macros from the load store unit of a high performance micro processor design shown.

• DeltaT from an ambient of 50C• Max difference between predicted

and actual dT was around 2C on certain non-critical areas

• Run time ~50x faster

• Snapshot of automatic self heating violation mitigation during design construction

• Activity conditions: 35% switching, No Clock gating

• Violation threshold set of 5C• Minimum area cost

Figure 1: Macro Designs 1 and 2 Early Delta T vs Detailed Field Solver Comparison

Design # Violations (Before)

# Violations (After)

Area Cost

Macro 1 68 0 0.04%

Macro 2 730 95 0.13%

Macro 3 39 0 0.02%

Macro 4 58 0 0.05%