enabling an interconnected digital world cadence eda and...

Enabling an Interconnected Digital WorldCadence EDA and IP Update

Jonathan SmithDirector, Strategic AlliancesSept 21, 2017

2 © 2017 Cadence Design Systems, Inc. All rights reserved.

EDA Requirements for Foundry Technology NodeFor customer fast ramp and efficient usage

• Available PDK and tech files to enable EDA tool usage

– Custom analog design, digital design, physical verification decks, library characterization

• Specific tool features enabled

– Back-biasing, forward-biasing in placement, routing, timing, IR drop

• Reference flows available

– Custom, digital

• Mixed-signal support, full system design support

– Mixed-Signal Open Access (MSOA) PDK

– Packaging, signal integrity analysis for system-level

• Proof points

– High-performing industry-standard IP used in tapeout

• Working silicon and proven IP

– Signoff proven, Vision/DDR4, working boards running system and application software


IoT Market Definition and Growth EstimatesLarge and widely varying

Known: IoT will include a large mixed-signal component, with complex packaging


Cadence Implementation LeadershipTechnology innovation: fast, smart, and optimized

Quantus™

Tempus™

Voltus™

Genus™

Modus™

Innovus™

Massively parallel for speed and capacity

Best PPA and intelligent flows

Rapid convergence and ECO

Fully integrated mixed signal

Implementation FabricCommon Engines, UI, and Flows

Pegasus™

PLACE and ROUTEFRONT END ELECTRICAL SIGNOFF

LogicalConformal®

ElectricalTiming, Power

PPA EnginesOptimization

PhysicalDRC, LVS, DFM

• Best-in-class core tools

• Common foundation

engines

• Differentiated productivity

DESIGN RULE CHECK


CHARACTERIZATIONLiberate™

Variety

Cadence Custom IC and PCB Design LeadershipEnabling smart product design from start to finish

PACKAGEAllegro®

Virtuoso®

CHIPVirtuoso®

Spectre®

ANALYSISSigrity™ Market leadership for

over 25 years

In excess of 70 different

ecosystem partners

Differentiated and

comprehensive

support for IoT,

automotive, and

aero/defense designs

System Design Enablement via an Extensive Ecosystem

BOARDAllegro®

PSpice®

OrCAD®

Mixed signal

Analog/RF

Photonics support

Rigid-flex board enablement

Advanced node (16nm to 5nm)

Advanced packaging


Cadence Verification SuiteTechnology innovation leadership: fast, smart, and optimized

VIPVERIFICATION IP

Perspec™

SW-DRIVEN TEST

vManager™

METRICS

Indago™

DEBUGUniform multi-engine verificationVerification Fabric

Palladium® Z1EMULATION

Xcelium™

SIMULATION

JasperGold®

FORMAL and STATIC

Protium™ S1FPGA PROTOTYPE

Total throughput

Metric-driven signoff

Application optimized

Cloud-centric architecture

• Fast: Best-in-class engines

• Smart: Flow-driven engine

integrations

• Optimized:

Comprehensive solutions


2015

Digital and Signoff Tools

22FDX Enabled

2016

V0.5 22FDX tapeoutsupported

EAD in 22FDX at CDNLive

2017

Phase III of 22FDX reference flow

Digital reference flow for 28FDS presented at CDNLive

Voltus 28FDS certification presented at CDNLive

Successful Foundry Node Requires an EcosystemStrong collaboration history – tool enablement and design flows


Samsung-Cadence Collaboration on 28FDSOI

Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology

Reference flow enables system and semiconductor companies to accelerate delivery of IoT and mixed-signal designs on Samsung’s process

SAN JOSE, Calif., May 24, 2017—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its custom/analog tools and full-

flow digital and signoff tools have achieved certification for the process design kit (PDK) and foundation library for the Samsung

Electronics’ 28nm fully depleted silicon-on-insulator (FDS), also known as FD-SOI , process technology. The Cadence® 28nm FDS

reference flow has been certified by Samsung using a quad-core design with the ARM® Cortex®-A53 processor covering forward body

bias (FBB) with a bias controller, a power-gating scheme, UPF2.1 compliance, multi-bit FF optimization, SCAN/PMBIST/ATPG and

SI/EM-aware design.


Slot for Upcoming Press Release


SOI Advanced-Node EDA Enablement – 28FDS

Samsung 28FDS Cadence Digital Reference Flow presented at CDNLive Silicon

Valley 2017: “Fast Ramp to Reap 28FDSOI Benefits ”

Design Capabilities 28FDS

Logic Simulation (Incisive)

Dig

ital I

mple

menta

tion a

nd S

ignoff

(RT

L to G

DS

)

Synthesis (Genus)

Power Analysis (Joules)

Test (Modus)

Place and Route (Innovus)

Timing Analysis (Tempus)

Extraction (Quantus)

EM/IR Analysis (Voltus)

Physical Verification (PVS)

Litho Physical Analysis (DFM/LPA)

Litho Electrical Analysis (DFM/LEA)

Chemical Mechanical Polishing (DFM/CMP)

Custo

m a

nd A

nalo

g

Desig

n

Schematic Editing (Virtuoso VSE)

Analog Design Environment (Virtuoso ADE)

Layout System (Virtuoso VLS)

Circuit Simulation (Spectre APS/XLS)

Electrically Aware Design (EAD)

EM/IR Analysis (Voltus-Fi)

Certified

Enabled

This slide contains forward-looking statements about Cadence business or products. Actual results may differ materially from the information presented here.


SOI Advanced-Node EDA Enablement – 22FDX

Design Capabilities 22FDX

Logic Simulation (Incisive)

Dig

ital I

mple

menta

tion a

nd S

ignoff

(RT

L to G

DS

)

Synthesis (Genus)

Power Analysis (Joules)

Test (Modus)

Place and Route (Innovus)

Timing Analysis (Tempus)

Extraction (Quantus)

EM/IR Analysis (Voltus)

Physical Verification (PVS)

Litho Physical Analysis (DFM/LPA)

Litho Electrical Analysis (DFM/LEA)

Chemical Mechanical Polishing (DFM/CMP)

Custo

m a

nd A

nalo

g

Desig

n

Schematic Editing (Virtuoso VSE)

Analog Design Environment (Virtuoso ADE)

Layout System (Virtuoso VLS)

Circuit Simulation (Spectre APS/XLS)

Electrically Aware Design (EAD)

EM/IR Analysis (Voltus-Fi)


Certified

Enabled

12FDX: Cadence and GLOBALFOUNDRIES have

started collaborating to support 12FDX node


Enabling FD-SOI Process

Genus Design

ExplorationReleased in December 2016

Innovus Body-Bias

Interpolation September 2017

Tempus Body-Bias

Interpolation September 2017

Voltus Body-Bias

Interpolation Upcoming



Cadence Tensilica Processor IP For automotive applications

Front-collision warning

Automatic high beam

Traffic sign

detection/

recognition

Lane-departure warning

Digital radio receiver: HD Radio,

DAB, DAB+, DRM, T-DMB

Multi-channel audio decode and

advanced post-processing

Multi-microphone voice command and noise reduction

Embedded Signal Processing

ADAS Vision Processing

Digital Radio and Voice Command

Acoustic noise cancellation

Advanced Driver Assistance Systems

Built-in LTE modem and

Wi-Fi access point

Peer-to-peer smart car

networking for intelligent

vehicle highway control

GPS

Telematics Connectivity / Radar

Emergency services

Battery management

Regenerative power

management

Engine control

Cabin environmental control

Tensilica® HiFi DSPs Tensilica Fusion DSPs

Tensilica Vision DSPs Tensilica ConnX DSPs

Radar/Lidar

ISO 26262 Ready / ISO 9001 CertifiedMultiple rounds of experience delivering DIAs to automotive licensees


EDA Requirements for Foundry Technology NodeFor customer fast ramp and efficient usage

• Available PDK and tech files to enable EDA tool usage

– Custom analog design, digital design, physical verification decks, library characterization

• Specific tool features enabled

– Back-biasing, forward-biasing in placement, routing, timing, IR drop

• Reference flows available

– Custom, digital

• Mixed-signal support, full system design support

– Mixed-Signal Open Access (MSOA) PDK

– Packaging, signal integrity analysis for system-level

• Proof points

– High-performing industry-standard IP used in tapeout

• Working silicon and proven IP

– Signoff proven, Vision/DDR4, working boards running system and application software


Cadence Custom and Digital Tools Ready for FD-SOI

• Multi-year collaboration with foundry FD-SOI leaders

• PDK enablement, tool readiness, design flows in place

• Enables designers to take optimal advantage of FD-SOI features such as body-biasing


Thank You

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of

Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

http://www.cadence.com/go/trademarks

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