empirical nonlinear iv and capacitanceempirical...

I Angelov

Compact, Equivalent Circuit Models for GaN, SiC, GaAs and CMOS FET

I.Angelov

Empirical Nonlinear IV and CapacitanceEmpirical Nonlinear IV and Capacitance LS Models and Model Implementation:

Nonlinear IV ModelsNonlinear IV Models,Capacitance Models, Charge Conservation,

LS Model Implementation,pFET examples: High Power, Linear,

GaN,SiC,GaAs,CMOS SSummary.

Iltcho Angelov MEL, Chalmers Univ. Göteborg Sweden

MOS-AK Baltimore Dec9Compact, Equivalent Circuit Models for GaN, SiC,

GaAs and CMOS FET

[email protected]

I Angelov

2

I.Angelov

1Physical Models- important in the device design stage.2Table Based Models- very accurate in the measurement range!y gTyp. 1000 measurement points! We have X-parameters- now!Problems: 1Outside Measurement Range? Data set is large>20 mB->slow.2Change of working conditions? Temp, Rtherm,Ctherm etc. ? 3Manufacturing tolerances? Vpof Gm etc3Manufacturing tolerances? Vpof, Gm, etc. 4Scaling High Power Devices-> it is easier to measure smaller device and scale. 5Feedback for the device quality, EC. parameters etc.- important for foundries!3Empirical Equivalent Circuit Models. 100-200 measurements points 1Accurate enough for many applications-1-5%.Comparably easy to understand and extract, compact form- parameter list.2Extendable out of the Measurement Range> from 65GHz measurements designs for 220GHz [Ref:46-48].designs for 220GHz [Ref:46 48]. 3Possibility to tune& change,scale the model, production tolerances, Rtherm...4Provide feedback for device parameters change, quality of processing ..All model types have their place and we should use the right type for


GaAs and CMOS FET

ythe specific application. We can mix& integrate different type models-ETB.

I Angelov

3

Transistor modelling sequence:I.Angelov

1Measurements1.1 Transistor functionality.1 2 Select Representative Device!!! Statistical data!1.2 Select Representative Device!!! Statistical data!1.3.1 Measurements, Multi-bias:

a)DC-Ids vs. Vds , Vgs parameterb)DC-Ids vs. Vgs, Vds parameter

1.3.2- Multi-bias S-parameters- the same bias points used in DC measurements1.3.3-Power Spectrum (PS)- i.e. fixed RF, Vds, Pin, sweeping Vgs2. SS model extraction

f4.Model function selection5.Model implementation6.Model evaluation- a)Multi-bias DC and S-parameters.) pb).Large Signal evaluation- Power Spectrum (PS), Load-pull c)Waveform, Combined Load-pull &Waveform.


GaAs and CMOS FET

I AngelovMeasurement setup DC and S-par.

4

I.AngelovMeasurement setup DC and S par.Simulation setup should be similar tothe measurement set-up. Bias Tee

RR1R=0.8 Ohm

Do not forget to measureresistances in the bias lines!

S-PARAMETERS

TermTerm1

Z=50 OhmNum=1

TermTerm2

Z=50 OhmNum=2

V_DCSRC2Vdc=VDS

DC_BlockDC_Block2

DC_BlockDC_Block1

DC_FeedDC_Feed1

I_Probe

Common mistake-people forget to measure resistances in bias lines

Bias tee

S_ParamSP1

Step=0.2 GHzStop=20 GHzStart=0.4 GHz

S PARAMETERSZ=50 Ohm

DC_FeedDC_Feed2

RR2

id_oupt

FET05mm2X1I_Probe

ig_opt

resistances in bias lines.

1SS&Noise model>3-4 practical bias points:Id 5 10 15 A Vd 1 t 3 V

ParamSweepSweep2

SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="SP1"SweepVar="VDS"

PARAMETER SWEEP

ParamSweepSweep1

SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="Sweep2"SweepVar="VGS"

PARAMETER SWEEP

V_DCSRC1Vdc=VGS

R2R=0.7 Ohm

Ids=5,10,15 mA , Vds =1 to 3 V2LS model :Multibias DC and Spar10Vgs&10Vds, Typ. 100-200 bias points. Step=2

Stop=14Start=0SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=

Step=0.2Stop=1Start=-1SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=


GaAs and CMOS FET

I Angelov

1 Transistor functionality evaluation:Rds(Ron)=Rd+Rs+Rch

5

I.Angelovevaluation:Rds(Ron)=Rd+Rs+Rch.Meas. 1 Ids vs. Vgs for low Vds; Nonlinear Models are controlled by intrinsic voltages,so we need Rs,Rd to account for the voltage drop.Measurement Ids in the linear part of the IV sweeping Vgs, at fixed low Vds.->safe measurement, GaAs Vds=0.1v, GaN Vds=1v.

Rds=Vds/Ids: For gate in the middle S-D we can consider:

107

Rs=Rd=Rch=Rds/3 For MSEFET:More accurately-Rs,Rd,by fly-back method

30

Good device:Ron=3 oHm,Roff>3MOhmWorking device:Ron=6 oHm;Roff=10 kOhmGaN,Vds=1V Vds=1v;Ids vs Vgs

104

105

106

Vds=1

RdsRds2

Rds0.2

0.3

m

15

20

25

ids(vg)

ds(m

A)

GaN,Vds 1V

1

10

100

1000 Rds2=10kOhmRon=6 Ohm

R1 2 3 4 5 6 7 8 9 10 11 12 13 140 15

0.1

0.0

Idsm

0

5

10

0 6 0 4 0 2 0 0 2 0 4 0 6 0 8

Ids(mA)@Vd=0.2V

Id


GaAs and CMOS FET

1-2 -1,5 -1 -0,5 0 0,5Vgs

1 2 3 4 5 6 7 8 9 10 11 12 13 140 15

VDS

-0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

Vgs(V)

I Angelov

2Measurements Ids vs. Vds, Vgs param.6

I.Angelov

100

Ids(mA)@ Vg=0.6VIds(mA)@ Vg=0.4VIds(mA)@ Vg=0.2VIds(mA)@ Vg=0VIds(mA)@ Vg=-0.2VIds(mA)@ Vg= 0 4V

Imax(Isat) at Vknee

60

80

Ids(mA)@ Vg=-0.4V

αs

GaAs

Low Power devicePdc<100 mW:Pdc>100mW- self-heating should be accounted

40

60

Ids(

mA

) should be accounted

0

20

0 0,5 1 1,5 2 2,5

Vkneeλ

αr

, , ,Vds(V)

• αr: slope at Small currents, Low Vds • αs: slope High currents ,Low Vds λ: slope at high Vds & small currents.


GaAs and CMOS FET

s• I.e. we need 3 parameters to model the slope Ids vs. Vds(min.)

I Angelov

2b Measurements Ids vs. Vds, Vgs param7

I.Angelov

0.4

0.5

0.6

500

600

DS

.i, m

A

Ids3s Ids4s

HighPower FETCW Pulsed

0.1

0.2

0.3

0.0

Idsp

.i

100

200

300

400

0CF

ET

M16

exp.

.DC

.I

IdVd1 IdVd2

1 2 30 4

VDS

The negative slope at high dissipated power is due to selfheating!

IdVd1SIM1.VDS=DCFETM16exp..DC.IDS.i=0.151SIM1.VGS=-1.250000

2.000Ids3sSIM1.VDS=DCFETM16exp..DC.IDS.i=0.456SIM1 VGS=0 500000

2.000

1 2 3 40 5

0

SIM1.VDS

DC


2.000Ids3sSIM1.VDS=DCFETM16exp..DC.IDS.i=0.456SIM1 VGS=0 500000

2.000

p gThis effect should be modeled with a thermal network!Pulsed IV measurements, when

il bl P l 100 200 S id


3.000

SIM1.VGS 0.500000Ids4sSIM1.VDS=DCFETM16exp..DC.IDS.i=0.423SIM1.VGS=0.500000

3.000IdVd2SIM1.VDS=DCFETM16exp..DC.IDS.i=0.155SIM1.VGS=-1.250000

3.000

SIM1.VGS 0.500000Ids4sSIM1.VDS=DCFETM16exp..DC.IDS.i=0.423SIM1.VGS=0.500000

3.000

lambda1=0.027;IdsVd2=IdsVd1(1+lambda1) lambdaSelfHeat=-0.083;Ids4=Ids3s(1+lambda1)*(1+lambdaSelfHeat)

available. Pulse <100-200 nS, to avoid selfheating.Then, you might face, ringing, dispersion manifestation etc.

Slope=DI/(I*DV)Slope at low power is positive =+0.027

0 083


GaAs and CMOS FET

Slope at high power is negative=-0.083

I Angelov

Self-Heating: Models without Self-Heating>not suitable for Pdc>0 3W

8

I.Angelovnot suitable for Pdc>0.3WSelf-heating effects :1 Change of mobility: Reduced mobility at higher temperature ->smaller Gm : P1T =gm/Ipk; P1T=P1(1+TcP1*ΔTj) Linear function + 100C (TcP1= 0 003) negativeP1T =gm/Ipk; P1T=P1(1+TcP1 ΔTj) Linear function + -100C (TcP1=-0.003)-negative2 Change of carrier concentration:Ipk0T=Ipk0(1+TcIpk0*ΔTj) (TcIpk0=-0.003) negative3 Device speed: mobility change will influence capacitances : Cgs0T=Cgs0(1+TcCgs0*ΔTj); Cgd0T=Cgd0(1+TcCgd0*DTj) (TcCgs0=+0.003)4 RF and dispersion characteristics: influenced by traps (at higher temperature things worsen) Rc=f(T) (TcRc=-0.002); Crf =f(T) (TcCrf=+0.002)

For all FET, important temperature coefficients are similar:∼∼

For all FET, important temperature coefficients are similar: TcIpk0=-0.0025 to -0.0035;& negative:TcP1 =-0.0020 to -0.0035;& negative:TcCgs0=0.002 to 0.0035;&positive

0 0 . 0 0 31 0 . 0 0 3

T c I p kT c P

−

−g pThe Self-heating effect is a proportional to TcIpk0*Rtherm. Error in TcIpk0,TcP1 can be compensated with Rtherm.


GaAs and CMOS FET

I Angelov

Self-Heating: Models without Self-Heating not suitable for Pdc>0.3W. 1 Be careful if Rtherm is not listed in model parameters

9

I.Angelov

0 20

0.30

..Id

A 0,4

0,5

0,6 DPulsedIVEudinaMIdVg-2IdVg-1.6IdVg2IdVg1.6IdVg1.2IdVg08IdVg04IdVg0

CW Pulsed:The slope is positive

0.10

0.20

0.00

AS

iC1

id.i,

A

0,1

0,2

0,3

IdVg0IdVg-04IdVg-08IdVg-1.2Id

(A)

even at high Pdc!

10 20 300 40

ASiC1..Vdsvd

00 10 20 30 40 50

Vd(V)∼∼Self-heating is usually modelled with a single thermo-electrical circuit Rtherm*Ctherm.

With temperature coefficients TcIpk,TcP1 known, there is only one thermal parameter to find > Rtherm This is done in the CAD at high Pdc:Rtherm. This is done in the CAD, at high Pdc:1Fit accurately Ids at the knee(current parameters), 2Adjust Rtherm to fit the slope Ids vs. Vds.Accurately, thermal resistance can be found measuring junction temperature Tj with infrared microscope. Tj=Rtherm.Pd+TambTh th l it Cth d l th th l t itThe thermal capacitance Ctherm model the thermal storage capacity of the structure. We can have different Rtherm and Ctherm for the chip Rthermchip, Cthermchip and for package Rthermpackage ,Cthermpackage for high power devices.Rtherm is not constant with temperature. For high dissipated power>10W should


GaAs and CMOS FET

p g p pbe considered: Rtherm(T)=Rtherm(1+TcRtherm*DTj).

I Angelov3Measurements Ids vs. Vgs

10

I.Angelov

80

100

Ids(mA)@Vd=0.2VIds(mA)@Vd=1V

80

100

120 Gm:Vd=1Gm:Vd=02Ids(mA)@Vd=1V

G A

GmsMeas 3. IV - Ids=f(Vgs, Vds)1Vds>Vknee at Vpks &and

20

40

60 ids(vg)GaAs

Ids(

mA

)

40

60

80

ids(vg)

Gm

(mA

/V)

Vpk0

P1s=Gms/IpksGaAs

Ipks

corresponding Ipks, Gmmax ;P1s= Gms/Ipks2P10=Gm/Ipk0 at low Vds is larger P1s=Gms/Ipks

0

20

-0,6 -0,4 -0,2 0 0,2 0,4 0,6Vgs(V)

0

20

-0,6 -0,4 -0,2 0 0,2 0,4 0,6

G

Vgs(V)

VpksP10

DVpk

0,035

0,04GmCMOSGmVd02

GmVd06

is larger P1s=Gms/Ipks

0 015

0,02

0,025

0,03 GmVd08

GmVd04

GmVd1

GmVd12

Gm

(mA

/V)

Part of ΔVpk is due to voltage drop on Rs * IdsΔVpki~0.2V (GaAs,CMOS) ΔVpk~0.2-0.6V (GaN)

0

0,005

0,01

0,015

0 0 2 0 4 0 6 0 8 1

Gm shape for MESFET&CMOS are similar


GaAs and CMOS FET

0 0,2 0,4 0,6 0,8 1

Vgs(v)

MESFET&CMOS are similar

I Angelov

5 Variety of cases: Gm shape and P1s= Gms/Ipks Models should be able to handle this.

11

I.Angelov

0,025

0,03 GmVd02GmVd04GmVd06GmVd08

40

50MT3GaAs Linear

P1=1

GmVd01GmVd0.6GmVd1.1GmVd1.6GmVd2.1

50

60

70

80W50umGaAsHEMT

P1=2.7

0,005

0,01

0,015

0,02

Metamorphic 2x10um

Gm

10

20

30

Gm

10

20

30

40

50

GmVd1.1GmVd03GmVd0.7

Gm

P1s=2.7 (HEMT) P1s=1.1 (Linear HEMT) P1s=5.3 (High Gain HEMT)

0-0,1 0 0,1 0,2 0,3 0,4 0,5 0,6

Metamorphic 2x10umP1=5.3

Vgs0

-2 -1,5 -1 -0,5 0 0,5VGS

0,6

0-1 -0,8 -0,6 -0,4 -0,2 0 0,2 0,4 0,6

Vgs

0,015

0,02

0,025

G N100

Gm6VGm10V

Gm

0,3

0,4

0,5

GaN2mm Eudina

GmVd5GmVd10

Gm

0,015

0,02

0,025

0,03

DSiC1mmP1=0.15

GmVd10GmVd2.5

Gm

0

0,005

0,01

-6 -5 -4 -3 -2 -1 0 1 2

GaN100umP1=0.25

G

Vgs

0

0,1

0,2

-1,5 -1 -0,5 0

P1=1.5

Vgs

0

0,005

0,01

-14 -12 -10 -8 -6 -4 -2 0 2Vgs


GaAs and CMOS FET

Vgs

P1s=0.15;SiC P1s=0.25;GaN P1s=1.4;GaN Eudina

I Angelov

5 Variety of cases: Gm shape and P1s= Gms/Ipks 12

I.Angelov

It is important to find the reason for the specific effect, dependence etc. to model and implement this properly. p p p p yExample 1;Gm shape- doping profile (Ids dependence vs. Vgs)-Ids=f(Ψ(Vgs)),P2,P3Example 2; GaN FET -Rs is bias dependent, velocity saturation.Rs=f(Ids)Example 3 ;Rs,Rd temperature dependent-self-heating. Rs=f(T)Usually we have several effects on the top of each other. I.e. we need to doUsually we have several effects on the top of each other. I.e. we need to do several, properly designed measurements to distinguish between effects, like specific Ids measurements, Measurements at 3 equally spaced temperatures, pulsed IV, LSVNA etc...

0 200 230

Rs Temperature dependent

0.04

0.06

0.08

0.10

0.12

0.14

Gm

Ver

ilog2

Rs Bias dependent

0.05

0.10

0.15

0.20

Gm

Ver

ilog2

P2=0.16P3=0.31

0.046

0.092

0.138

0.184

0.230

Gm

SD

D

-3 -2 -1 0-4 1

0.02

0.00

VGS

-3 -2 -1 0-4 1

0.00

VGS

-3 -2 -1 0-4 1

0 0 6

0.000

VGS

Example 1:Parameters of the Example 2: Rs Bias dependent

Example 3:Rs,Rd


GaAs and CMOS FET

F=f(Ψ(Vgs)) function changed Bias dependent temperature dependent

I Angelov

13

High Power devices I.Angelov

Important for Large&High Power devices:1.The Gate Control is delayed and reduced at high frequency:

g

y g q yLarge&High Power Devices do not respond immediately at RF!

Cdel =2-3fF- is the capacitance of the gate footprint, Rdel=2kOhm(chan. resistance) 2 Current slump -In some cases at RF we do not reach the DC Ids values.3 (Back gate) voltage will change the effective Vgs at RF >dispersion3. (Back-gate) voltage will change the effective Vgs at RF ->dispersion4. Higher Rs and Rd/ mm for SiC and GaN FET in comparison with GaAs FET 5. Rd, Rs bias and temperature dependent! (A.Inoe et al., IMS2006 WE2F2, M. Thorsel)

6 Self heating model must! Mounting quality is critical 0 5 A L dLi6. Self-heating model-must! Mounting quality is critical. 7. Breakdown important for high power devices!8 Keep device safe<Pmax!Organize measurements properly 0 2

0.3

0.4

0.5

id.i

wvo

ltag

e..

id.i

Pm

ax

Pmax

A

B

LoadLine

Organize measurements properly.Dual region measurements& simulations:A)High Ids, Low Vds; B)Low Ids, High Vds

2 4 6 8 10 12 14 16 180 20

0.1

0.2

0.0

dD

CL

ow


GaAs and CMOS FET

B)Low Ids, High VdsCover the load line!

vdDCLowvoltage..vd

Vdsh

I AngelovHigh Power FET EC

14

I.Angelov

SimplifiedDispersionM d l C f R

Ri Cdel

Lg Rg LdRgd Cgd Rd

DrainGate IgdModel:Crf,RcCdel

Vgsc

Ctherm

Rtherm

RdelVbgate

Rc

Crf

E t lCds

IdsIgs

SiC FET

CdelCgsRs2

RsLs

Rc External

Source

Crs

CdsThermal subciruit.

Parasitic elements :Rg,Rgd,Rd,Rs,Ri, Cds,Lg,Ld,Ls, layout elements etc.New: Cdel, Rdel shunting the gate control node Vgsc> Frequency

SiC FET

dependent gate control and delay. b) Frequency dependent Rs for SiC

Nonlinear: Ids, Igs, Igd,Cgs,Cgd-> we need models.M d l t ll d b i t i i lt !


GaAs and CMOS FET

Models are controlled by intrinsic voltages!

I Angelov

15GS,GD Breakdown Measurements

We can use resistors to limit& define safe currents levels. I.Angelov

1.0

1.5 m1

Common Gate Device: we split the GS, GD Junctions: Rmeas=50 ohmRcoupl= 1 MOhm

Vdsi

ÿDrain

V_DCSRC2Vdc=vd

RR4R=50 Ohm

GateGroundedGSJunctionBrekdown

Drain

R

RR4R=1 MOhm

I P b

GD GS

m1indep(m1)=plot_vs((idsp.i), vd)=-0.003

40.000-0.003

-0.002

-0.001

0.000

0.001

0.002

(idsp

.i)

m1m1indep(m1)=plot_vs((idsp.i), vd)=-0.003

40.000

-18 -16 -14 -12 -10 -8 -6 -4 -2 0-20 2

-1.5

-1.0

-0.5

0.0

0.5

-2.0

vg

igp.

i, m

A

m1vg=igp.i=0.001

2.000

Rcoupl= 1 MOhmVsi

CommongateDG JunctionBreakdown

ÿ

Gate

Source

FET05mmDevDVerilogMX1

I_ProbeidspI_Probe

igp

DCDC1

DC

Var

RR5R=1 MOhm

VsiSource

FET05mmX1

RR5R=1 kOhm

I_Probeidsp

DCDC1

Start=-20SweepVar="vg"

DC

V_DCSRC2Vdc=vg

I_Probeigp

4 9 14 19 24 29 34-1 39

-0.004

vd

Gate -Drain breakdown measurement setup ; Gate -Source breakdown measurement setup.We can use resistors to limit& define safe currents levels. Compliance is not fast enough and difficult to model

Step=0.1Stop=40Start=-1SweepVar="vd"VAR

VAR1

vd = 0 Vvg = 1 V

EqnVar

Step=0.1Stop=2

difficult to model.Common Source Device, Source without via, using needles:

-1

0

1

2

ourc

e, m

AG

ate,

mA

m2 0 5

1.0

1.5

AFET05mmD

RR7R=1kOhm

V_DCSRC3Vdc=vd

I_Probeidsp

R

RR4R=1 MOhm

4 9 14 19 24 29 34-1 39

-3

-2

-4

vd

IdsC

So

m2IdsC

G m2vd=IdsCSource=-0.0030

40.0000

-18 -16 -14 -12 -10 -8 -6 -4 -2 0-20 2

-1.5

-1.0

-0.5

0.0

0.5

-2.0

vg

igp.

i, m

AIg

sCG

ate,

mA

SourceGrounded via 1MOhmBreakdownGD Junction

Gate

Source

drain

DCDC1

Step=0 1Stop=50Start=-1SweepVar="vd"

DC

FET05mmDX1

RR6R=1 MOhm

I_Probeigp

I_Probeidsp

BreakdownGS JunctionSource Grounded,Drain via1MOhm

Drain

Source

Gate

DCDC1

St 0 1Stop=2Start=-20SweepVar="vg"

DCFET05mmDeX1

R5R=1 kOhm

V_DCSRC2Vdc=vg

I_Probeigp


GaAs and CMOS FET

Gate -Drain breakdown measurement setup. Gate-Source breakdown measurement setup.OthStep=0.1 R 1 MOhm Step=0.1

I Angelov

Ids, Igs &Cap. Model Function Selection16

I.Angelov

1Physical !!!2.Single definition -∞+ ∞; Infinite & correct derivatives. 3.The model parameters should be responsible for specific things: Current, Voltage, Cap, Slope, etc. g , g , p, p ,4. Flags, conditions should be avoided!5. Directly extractable! Available in CAD tools!6. If possible, use inflection points to construct the model. This simplifies6. If possible, use inflection points to construct the model. This simplifies the extraction, improves accuracy and reduce model parameters. 7.The best solution is to split (if possible) the model Function on independent parts: F= f1[Ψ1(Vgs)]*f2[Ψ2 Vds]independent parts: F f1[Ψ1(Vgs)] f2[Ψ2.Vds] 8.If the guess for modeling function F is good, extracted argument will be linear function: Ψ =P1*Vgs; P1=derivative of F=f(Ψ(Vgs))


GaAs and CMOS FET

I Angelov2 Ids Model Function Selection

17

I.Angelov2 Ids Model Function Selection

FET Ids- solution of Schrodinger equation:Error type functionsypTypical for FET: f1(Vgs)=1+erf(Vgs)The error function is not always available in CAD tools and

simple& direct reverse extraction is not possiblesimple& direct reverse extraction is not possible.Replacement for error functions:a) GaAs: f1a(Vgs)=1+Tanh[P1.Vgs]a) GaAs: f1a(Vgs) 1 Tanh[P1.Vgs]

extraction :Ψ1a(Vgs)=ArcTanh[(Ids/Ipk0)-1]b) GaN and SiC: f1b(Vgs)=1+Tanh[Sinh(P1.Vgs)]

extraction: Ψ1b(Vgs)=ArcSinh [ArcTanh[(Ids/Ipk0)-1]]c)We need to fit different profiles i.e. Adjustment possibilities!d) try to use inflection points- this will make model compact and accurate at


GaAs and CMOS FET

) y p pcritical points.

I Angelov

3 Ids Model Function Selection FETΨ Examples:extracted GaN, SiC FET

18

I.AngelovΨ Examples:extracted GaN, SiC FET

0

1PsiVd10PsisinhVd10

1

2GaN FET

2

-1

SiCP1

ψ

0

GaN

P1

ψ

SiC FET

-3

-2

-2

-1PsiSinhVd10PsiVd=10 SiC FET

-4-15 -10 -5 0

Vgs-3

-6 -5 -4 -3 -2 -1 0 1 2Vgs

a) GaAs: f1a(Vgs)=1+Tanh[P1.Vgs]Ψ1a(Vgs)=ArcTanh[(Ids/Ipk0)-1]

b) GaN and SiC: f1b(Vgs)=1+Tanh[Sinh(P1.Vgs)]Ψ1b(Vgs)=ArcSinh[ArcTanh[(Ids/Ipk0)-1]]

c)Directly extractableH.Rohdin ED-33,N5,May1986 pp. 664ns(V )=n (α+(1 α)tanh[(V’ V )/V ]]


GaAs and CMOS FET

c)Directly extractable. ns(Vg)=ns0(α+(1-α)tanh[(V g-Vgm)/V1]]

I Angelov4 Model Function Selection Spectral content( derivatives)

19

I.AngelovSpectral content( derivatives)

ds 1

3 3 5 51 1 1

I ef=1+Erf[( )]/(2/Sqrt[ ]); ( )1* * ( * ) ( * )11.

gs pks

gs gs gsd k k k k

P V V

I ef I I P V I P V I P V

πΨ Ψ = −

= + − +

DC ,1-st equal

1

3 3 5 5

(1 tanh( ));

2

( );

1

gs pksds pkI I P V V GaAs= + Ψ Ψ = −

1 1 1( ) ( )1.103

gs gs gsds pk pk pk pkI ef I I P V I P V I P V+ +

5-th different

1 1(1 tanh( 1)); 1 ( ( )); ,sinh gs pksds pkI I P V V GaN SiC= + Ψ Ψ = −

3 3 5 51 1 1

22.15

1* * ( * ) ( * )3

gs gs gsds pk pk pk pkI I I P V I P V I P V= + − +

3 3 5 51 1 11 * * ( * ) ( * )1 13.

6 40gs gs gsds pk pk pk pkI I I P V I P V I P V= + − +


GaAs and CMOS FET

3-rd different

I Angelov

5 Model Function Selection – Ids Derivatives20

I.Angelov

3

4

5

HAmêvL

3

4

5

AmêvL

-8 -6 -4 -2 0Gate voltage , V

1

2mg,


1

2mg,H

m

GaAs Gm bell shaped. GaN ; SiC Gm:f1a(Vgs)=1+Tanh(P1.Vgs) b) f1b(Vgs)=1+Tanh(Sinh(P1.Vgs))Due to the term:(1/6)(Ipk0*P1)Vgs 3> Rectangular shape of Gm

Gate voltage , V

0.5

1

1.5

2

AmêvL

-0 5

0

0.5

1

1.5

2

2m,H

AmêvL3-rd order of Ids


-1.5

-1

-0.5

0

2mg,H

m


-1.5

-1

-0.52mg


GaAs and CMOS FET

GaAs Gm2:f1a(Vgs)=1+Tanh(P1.Vgs) GaN SiC Gm2: f1b(Vgs)=1+Tanh(Sinh(P1.Vgs))

I Angelov

21

Simple Ids model:5 Parameters: Ipks Vpks P1 α λ I.Angelov

5060

Idsgmpks 100

Ids(mA)@ Vg=0.6VIds(mA)@ Vg=0.4VIds(mA)@ Vg=0.2VIds(mA)@ Vg=0VIds(mA)@ Vg=-0.2VIds(mA)@ Vg=-0.4V

5 Parameters: Ipks,Vpks,P1, αs, λ

20304050

I

Ids

Ipks 60

80

mA

)

αs

-1 -0.5 0 0.5 1

G t lt (V)

010

Vpks 20

40Ids(

m

Vkneeλ

α rGate voltage, (V)

00 0,5 1 1,5 2 2,5

Vds(V)

5 Parameters: Ipks,Vpks,P1, αs, λ

(( )); /

(1 tanh( )). tanh( )(1 )p sds dspks ds

VP PV g I

I V VIψ

α λ= + Ψ +Ids, gm are exact at Vpk, typical, global error <10%.

0.04 0.25 ;1 0.15 0.3 ; 1 5 ;

Typical:0.001 0.02 ;

0.35 1 ;GaN

GaGaAs

P SiC GaN Asλ = −

= − −−−


GaAs and CMOS FET

11 (( )); / p m gs mpkp kks m pVP PV g Iψ = − = 0.3 0.7 3;0.5s Ga GaN Asα −= −

I Angelov

22

Ids: 10 Parameters Model: Ipks, Vpks, P1, αs, λ +ΔVpk, P2,P3, DP, αr I.Angelov

80

100

Ids(mA)@ Vg=0.6VIds(mA)@ Vg=0.4VIds(mA)@ Vg=0.2VIds(mA)@ Vg=0VIds(mA)@ Vg=-0.2VIds(mA)@ Vg=-0.4V

80

100

120 Gm:Vd=1Gm:Vd=02

)

P1s

+ΔVpk, P2,P3, DP, αr

Ipk0 Vpk0 P1=gm/Ipk0

40

60

80

Ids(

mA

)

αs

20

40

60

80DVpk=Vpks-Vpk0

Gm

(mA

/V)

P10

Ipk0,Vpk0,P1=gm/Ipk0DVpk- change for the Vpk vs. VdsP2,P3-adjust GM shapeαs- slope at high currentsαr slope at small currents

0

20

40I

Vkneeλ

αr

0

20

-0,6 -0,4 -0,2 0 0,2 0,4 0,6Vgs(V)

VpksVpk0αr-slope at small currentsλ-slope at high Vds, small currentsDP1-reduction of P1 for high Vds

10 parameters model : 5par. + DVpks,P2,P3,ar,DP1 00 0,5 1 1,5 2 2,5

Vds(V)

2 3

1 30 2

(1 tanh( )).tanh( . )(1 )

(( ) )( ) ( )pds ds ds

gs k

pksI V V

P V V gs pks gs pkm

I

P PV V V Vα λ

ψ

= + Ψ +

= − + +− −

r,

Typical, global 3%

1 11

1 30 2

( ) tanh( )

( ( ))[(1 )(1 tanh( ))] + * ( 1 + tanh( ))

(( ) )( ) ( )p

pk ds pks pks s ds

m s

pks

ds

gsm pk

V V V V V

P f T V

V

P P

P V V gs pks gs pkmP PV V V Vα

αα ψα α

ψ= − + Δ

= + +

Δ

Δ

+ + error <3%.


GaAs and CMOS FET

= + * ( 1 + tanh( ))R S pα ψα α

I Angelov

23

Connection with physical modelsI.Angelov

Ipks=0.5*Imax;Vpks=Vpoff+Vbi;P1=abs(Imax/Vpks); For example:I 0 8 V ff 1 2 Vbi 0 8 GaN FETImax=0.8;Vpoff=-1.2;Vbi=0.8;

dI V

Gm max at Imax/2 (for respective Vgs)

GaN FET

4 4

max

max ;Knee voltage .I max;

( ) 10 ( 0 5 ) 10

2(1 tanh( )).tanh(2. )(1 )

10

pds

ds dsVknee

Vknee R

Lsg Lgd Lg Lsg Lg

I VI V

q vsI

λ

σ=

+ + +

= + Ψ +

=

7

( ).10 ( 0.5. ).102 ; 2 ;

Pinch-off voltage:

.10 ;b c b bi cpoff

Lsg Lgd Lg Lsg LgR Rc Rs Rcq q

qE d V EV

σμ σμ

σφ φ

+ + ++ +

= − − = −

= =

.10 ;.

b c b bi co AG

c G

poff E d V E

E

V φ φε ε

χ χ= − ; ( ). (1 ) (1 )

AG AG G A G

AG A Gx x B x xχ

ε ε ε εχ χ χ

= + −= + − − −

[49}T Oishi H Otsuka K Yamanaka Y Hirano I Angelov “Semi-physical


GaAs and CMOS FET

[49}T. Oishi, H. Otsuka, K. Yamanaka, Y. Hirano, I. Angelov Semi physical nonlinear model for GaN HEMTs with simple equations “ INMMIC 2010 Göteborg

I Angelov

Ids Equations – Extended: Breakdown& Dispersion24

I.Angelov

2 3

.)(( )

(( ) ( ) ( )

(1 tanh( )) tanh( )(1 )

)

pds pk ds ds sbd trgVkb VTI I V V

P V V P V V P V V

eα λ λ −= + Ψ + +

Ψ = − + − + −

Breakdown parameters Important for Hi h P d i

2.

1

2

1 2 30(( ) ( ) ( )

- ( -( ) tanh( )).

)/

BGate dg tBGa

p

m mpk

spk ds pks pks pks sbds e rt

gs gs gsm pk pks pkm

pk

VK V VV V V V V V V

P V V P V V P V VP g I

α= − Δ + Δ +

Ψ = − + − + −

=High Power designs

Back-gate-Dispersion parameter

1 1 1

(( ) ( )

( )[(1 ) 1

)

(pk ds pks pks pks ds

mP P T P= + Δ

2 2 2

tanh( ))][(1 (1 tanh( ))] [(1 (1 t h( ))]

))

s ds

m S ds

VP P P

PV

P P V

ααΔ

Δ

+

= + +

+ +

Ipk=f (T); P1=f(T)self-heating 2-nd harmonic 3-rd harmonic vs. Vds

3 3 3

= + * ( 1 + tanh( )); = + * ( 1 + tanh( ))

[(1 (1 tanh( ))] )m S ds

p R S p n R S n

PP P Vψ ψ

αα α α α α α

Δ= + +

Ids parameters=14 (Ids-10 Breakdown param =4)Ids parameters=14 (Ids-10, Breakdown param.=4)7 important Ids parameters: Ipk,P1,Vpk,ΔVpk,αr,αs,λ are found directly from measurements and provide accuracy <5%CAD tool is used for the extraction and optimization


GaAs and CMOS FET

CAD tool is used for the extraction and optimization.

I Angelov

MEFET Igs Equations -These devices have Gates!!!25

I.Angelov

0.02

0.03

0.04

Igvs

Vde

xp..

ig.i

Gate parameters:Vjg;Ij;Pg

-0.00002

0.00000

0.00002

C1.

.Ig

g.iThe diode equation

-6 -5 -4 -3 -2 -1 0 1-7 2

0.00

0.01

-0.01

DCGaN200umIgvsVdexp..vg

DC

GaN

200u

m

vg

ig

-20 -15 -10 -5-25 0

-0.00006

-0.00004

-0.00008

BSiC1 V

BS

iCigshifted to Vjg at which we operate the device

. ))) exp( * )); , 0.8Simple: parameters Igs model - ; slope =1/(Vt* ):

(exp( tanh3

((Vjg, Ij Pg

gg gjj j PP V GaAs VjgVI VIη

− − == −

Igs-Vgs SiC MESFET

vg BSiC1..VgsvgIgs-Vgs AlGaN/GaN HEMT

. ))) exp( )); , 0.8(exp( tanh(((exp( .tanh(( ))) exp( * )); , 1.2jg

gg g

g g

jj jggs

g

s

j

g

d jggd

PP V GaAs VjgVP V V GaN

I VI V P

IVjgI = − − − =

0.00002

xp..

ig.i

Vds=10,20,40V;Vgd 70V

Breakdown model:3+4parameters

-0.00004

-0.00002

0.00000

-0.00006SiC

2x50

Igsv

sVgs

exig

.i, A

)))

)))

expexp

(1 . ( (((1 . ( ((

bdgate bdgate

bdgate bdgategd

bdgs

b

gsgsbd

gdbd g gd

gs

d d

I VI

K E VK E VV

II

= + −

= + −

3-simple Igs model + 4(Kbdgate,Ebdgate,Vbdgs, Vbdgd)


GaAs and CMOS FET

-25 -20 -15 -10 -5-30 0

vg

)))p( ( (( bgdbd g gdd d

I Angelov

5 b Model Function Selection26

I.Angelov

We can add part of Ψ2 working at other voltage Vpk2, and combine. We create large variety of Gm shapes with 2 extra parameters Vpk2, AA. Example: Vpk=-0 3; Vpk2=-2; AA=0 to 1

Ψ = P1p ((AA (Vgs - Vpk) + (1 - AA) (Vgs - Vpk2) + P2p (Vgs - Vpk)^2 + P3p (Vgs - Vpk)^3))

1 4

Example: Vpk=-0.3; Vpk2=-2; AA=0 to 1

0.12

GaAs

0.8

1.0

1.2

1.4

m,HA

êvL

0.04

0.06

0.08

0.10

ma

g(Y

(2,1

))

-3 -2 -1 0 10.0

0.2

0.4

0.6gm

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5-3.0 1.0

0.02

0.00

Vgs

V k2 2 0 V k 0 3V AA 0 1Gate voltage, V Vpk2=-2.0v; Vpk=-0.3V, AA=0.1;We can, but even for devices with complicated IV, we should Stop to increase parameters-> We can switch to Table B d(TB) E i i l T bl B d (ETB) !!!


GaAs and CMOS FET

Based(TB) or Empirical Table Based (ETB) !!!

I Angelov

Cap FET 1 From S-parameter measurements Small Signal extraction: Cappy; Berroth....

27

I.Angelov

600

800

1000

HFfL

300

400

500

FfL

Measured&Extracted SS capacitances should be verified for

-6 -4 -2 0Vgsc V

200

400sgC,H

-8 -6 -4 -2 0 2Vgsc V

100

200dgC,H

f

=∂ ∂∂ ∂

gs gdC CV V

should be verified for Charge Conservation!

0 *

1 2tanh tanh(1 [ ]) (1 [ ])gs gsp gsC C C

ψ ψ= +

+ +

Vgsc , V Vgsc , V∂ ∂gd gsV V

Usually, Capacitances are extracted from S-par

Cgs,Cgd vs. Vgs

1 2

10 111

20 212

tanh tanh(1 [ ]).(1 [ ])..

gs

ds

P P VP P V

ψ ψψψ

=

= +

+ ++

500

600

700

800

HFfL

300

400

500

FfL

measurements in 4-10 GHz range:

•Cgdpi-minimum cap; Cgs0,Cgd0: capacitances at the inflection point; P11 P21 l V Vd

5 10 15 20 25 30 35 40Vdsc , V

100

200

300

400

sgC,H

5 10 15 20 25 30 35 40Vdsc , V

100

200dgC,H

f


GaAs and CMOS FET

P11,P21:slope vs.Vgs,Vds Cgs,Cgd vs. Vds,

I Angelov

Gate Charge: Capacitance or Charge Implementation?

28

I.AngelovImplementation?1 Capacitance implementation >we don’t need transcapacitances! Cap directly from SS extraction!2 The Cap Functions should be well defined -∞+ ∞

1.5E-12

2.0E-12

2.5E-12

Cgs2 The Cap. Functions should be well defined + .

0 1 2

1 10 11111 2 20 21

0 3 4 111

. . ; .

.(1 [ ]).(1 [ ])

.(1 [ ]).(

: tanh tanh

tanh t1 [ ] 2anh )gs ds ds

gs gsp gs

gd gdp gd

P P V V P P V

S C C C

C C C P

SPψ ψ

ψ ψ

ψ ψ= = ++ +

= + + +

= + + + +

→

2 4 6 8 10 12 14 16 180 20

5.0E-13

1.0E-12

0.0

Vds

C

8E-13

_prj\

dat

30 31

g

113 4 4 140 1

High voltage effects for C

. . ; .ds dsgd PP P V P P V Vψ ψ= = +− −

s gd 111& cross-coupling from Vds -C

2; ; ;:

PVgs Vgd Vgs VgdIgsc Cgs Igdc CgdHB ∂ ∂ ∂ ∂

= =-4.0 -3.5 -3.0 -2.5-4.5 -2.0

2E-13

4E-13

6E-13

0

Vgs

Cgd

m1

elov

\AD

S\A

DS

files

\wp4

\wp4

n1_

2; ; ;: Igsc Cgs Igdc Cgdt t t t

HB∂ ∂ ∂ ∂

0. .( 1) 2

Charge Implementation :2

( , ) gsp gs gs gsgs gs gs gsds C V C V Lc ThQ C V V dV + +== ∫

∫

gsVgge

Integration vs. terminal voltage!Remote voltage parameter!We will always have difference in the

0

1 42 3

11 41

log[cosh[ ]] log[cosh[ ]]1 ; 2 tanh[ ]; 4 ; 3 tanh[ ];

. .( 4) 3( , ) gdp gd gd gdgd gd gs gdgd

Lc Th Lc ThP P

C V C V Lc ThQ C V V dVψ ψ

ψ ψ= = = =

+ +== ∫ simulated S-parameters using capacitance or charge implementation using the same coefficients!> S.Maas Nonlinear Microwave Circuits


GaAs and CMOS FET

Total Charge Implementation Qg Qgs Qgd= +> S.Maas Nonlinear Microwave Circuits

I Angelov

Cap Implementation 1-DC current phenomenon in HB.

29

I.AngelovDC current phenomenon in HB.1Cap implementation: DC current can be observed in HB for Cap.depending on Vt, Vr. If the voltage V across the capacitors terminal consists of a small and a large amplitude V0 and V1, the current I through that capacitor can be defined as:

1; ( .1)odVI C I I Eqdt

= = + 0 1; ( .2)dCoC C V EqdV

≈ + 0 010 1 1; ( .3)dC dV V

dV ddVC Id t

Eqt

+ = 0 00; ( .4)dC dV G

dV dtEq=

current I through that capacitor can be defined as:

whereas I0 and I1 are small and large amplitude current parts. Linearizing C yields Eq.2

2 2* ( .5)g gs gs gd gdQ aV bV V cV Eq= + + ; ( .6)g gs g gd

gs gd

dQ dV dQ dVig EqdV dt dV dt

= +

Inserting this C in Eq.1) and eliminating the second order terms yields Eq.3. The part Go from Eq.4 is a DC conductance (current) via capacitor which is unphysical.

gs gddV dt dV dt2 Charge implementation, will not produce DC Current via Cap.- we multiply with j ω, and for ω=0 ,Icap=0For example, if the total charge Qg is Eq.5(linear combination), the total gate current will be Eq.6.

C (V V ) ( ) ;( 8)gdQ V const Eq

g g ( ) gAssuming Vgs = e sin(wt) and Vgd = f cos(wt) (e and f are constants) yields Eq.7whereas ω is the radian frequency and A = a.e2-c.f 2 and B = b.e. f . The current is purely capacitive and does not have any DC component,at ω=0 ,Ig=0.

( sin(2 ) sin(2 )); ( 7)i A t B t Eqω ωω +


GaAs and CMOS FET

gs gs dsC (V ,V )= ( ) ;( .8)dsgs

Q V const EqdV

= ( sin(2 ) sin(2 )); ( .7)gi A t B t Eqω ωω= +

I Angelov

Comparison in ADS: Cap, Cgs,Cgd calculated from Charge and Cap implementations:

30

I.Angelov

0.0

2.0E-13

4.0E-13

6.0E-13

8.0E-13

1.0E-12

Cgs

1D

Cgs

Cgs

2

4.510E-13

9.520E-13

1.453E-12

Cg

d1

DC

gd

Cg

d2

-1.5E-14

-1.0E-14

-5.0E-15

0.0

DC

gs

m4

m4VGS=DCgs=-2.087E-16VDS=0.500000

-1.400-2E-28

-1E-28

0

1E-28

2E-28

DC

gd

m5

m5VGS=DCgd=1.010E-28VDS=1.000000

0.150

Magnified DCgs Magnified DCgd

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4-1.4 0.6

-2.0E-13

VGS-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4-1.4 0.6

-5.000E-14

VGS

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4-1.4 0.6-2.0E-14

VGS

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4-1.4 0.6

-3E-28

VGS

8.i), m

A

Cgs:Cap&Charge DCgs is small<3% Cgd:Charge&Cap DCgd<1% Idiodeindep(Idiode)=plot_vs(real(Igsp.i[::,0]), Vgs)=7.985E-6

-0.150 FORCED CHARGE CONSERVATION for Cap. Impl. DC t t i i f th i l ti f th

50 100 150 2000 250

-7

-2

3

-12

8

ts(I

gsp.

i), m

Ats

(HB

1PsV

d2P

0CA

P2.

.Igsp

-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2-1.6 0.0

0.000005

0.000010

0.000000

0.000015

real

(Igs

p.i[:

:,0]

)

Idiode

Igsc

ap

I=Cgs*dVgs/dt

Eqn1

PortGateNum=1

DC_BlockDC_Block1

DC current component arising from the violation of the charge conservation is blocked with DC block. But, DC current is generated, so HB calculation will be influenced. The inductor allows DC current to flow without disturbing the input circuit. Though, the DC current we hide will influence the PAD waveforms etc

15

20

Vlo

ad[::

,1])

5

load

[::,2

])

-8

ad[::

,3])

time, psec

Igs with Cap Implementation Waveforms for Charge&Cap similar, but not equal.Cap current is the same order as diode current. Harmonics are correct from the charge implmentation!

1.4 1.2 1.0 0.8 0.6 0.4 0.21.6 0.0

Vgs

current we hide, will influence the PAD, waveforms etc.

-1.3

-1.1

-0.9

-0.7

-0.5

-0.3

-0.1

-1.5

0.0

0

5

10

15

-5

Vgs

dBm

(Vlo

ad[::

,1])

dBm

(HB

1PsV

d2P

0CA

P2.

.V

Pin=3 dBm,RF=5GHz;Vd=3V;1-st Harmonic

-1.3

-1.1

-0.9

-0.7

-0.5

-0.3

-0.1

-1.5

0.0

-15

-10

-5

0

-20

dBm

(Vlo

ad[::

,2])

dBm

(HB

1PsV

d2P

0CA

P2.

.Vl

Pin=3 dBm,RF=5GHz;Vd=3V;2-nd Harmonic

-1.3

-1.1

-0.9

-0.7

-0.5

-0.3

-0.1

-1.5

0.0

-16

-14

-12

-10

-18

dBm

(Vlo

ad[::

,3])

dBm

(HB

1PsV

d2P

0CA

P2.

.Vlo

a

Pin=3 dBm,RF=5GHz;Vd=3V;3-rd Harmonic


GaAs and CMOS FET

VgsVgs

3 1 9 7 5 3 15

Vgs

d

1-st harmonic, Charge&cap, 2-nd harmonic Charge&Cap, 3-rd Charge&Cap

I Angelov

Mixed Charge-Current (MCC) Implmentation 31

I.Angelov

MCC- 1Charges are derived the usual way :Integrating the capacitance with terminal voltage, remote voltage parameter.

Qgs (Vds) (Vgs)* ; Qgd (Vds) (Vgd)* ;Qgd=f2r f3r f3r f* 44f11;f2r*gsQ =Cgs dVgs Cgd dVgd= ∫ = ∫Qgs (Vds). (Vgs) ; Qgd (Vds). (Vgd) ;Qgd=f2r f3r f3r f44f11;f2rgsQ =Cgs dVgs Cgd dVgd= ∫ = ∫

The constants of the integration are Qgs0 and Qgd0 .When terminal voltage is 0(short circuit), charge is 0.2-Calculate time derivative for Terminal charges: f11;f44; Eq.5a, 7a(multiplying with jω)

Qgs0=Cgs0( Log[Cosh[P10]]/P11)(1+Tanh[P20+P21 .Vds]);Qgst Qgs Qgs0; Cgs D[Qgst Vgs] ( 6)

f11=Cgs0( Vgs+ Log[Cosh[P10+P11 Vgs]]/P11)(Eq5af2r=(1+Tanh[P20+P21 Vd +Cgspi .Vgs;s]) (E

)q5b)

E

Qgd0=Cgd0( Log[Cosh[P40]]/P41)(1+Tanh[P30-P31 Vds]);Qgdt=Qgd-Qgd0;Cgd=D[Qgdt,Vgd] ( 8)

+Cgdpi Vgd44 Cgd0( Vgd+ Log[Cosh[P40+P41 Vgd]]/P41)

f3r=(1+Tanh[P30-P31 Vds]) (E* (Eq7

q7ba)

;)

Eq

f =

Qgst=Qgs-Qgs0; Cgs=D[Qgst,Vgs] ( 6)Eq

I( di di) <+ ddt(Q d)*( ) Q d0* ( 9)f3 f3 E

Qgdt Qgd Qgd0;Cgd D[Qgdt,Vgd] ( 8)Eq

3 Resulting terminal, cap. current is multiplied with remote voltage dependences f2,f3 f2-Eq.5b, f3-7b to get the node currents Eq.9, 10.

I(gdi,di) <+ ddt(Qgd)*( )-Qgd0* ;( 9)I(gsi,si) <+ ddt(Qgs)*( )-Qgs0*

f3r f3rf2r f ;( 0r 1 )2

EqEq

This procedure can be used to implement capacitances


GaAs and CMOS FET

dependent on several remote voltages.

I Angelov

Cap Implementation6- Comparison Cap,Charge,MCC32

I.Angelov

The ideal case:1 Small Signal analysis- results coincide with Capacitance type1 Small Signal analysis results coincide with Capacitance type Implementation.We should compare imaginary parts Y11,Y12,Y22.2 Large Signal Analysis -results coincide with the Charge type Implementation. We should look at the Output Power Harmonics PADImplementation. We should look at the Output Power, Harmonics,PAD etc.3 The DC current via capacitances is 0 or very small. The radical solution is to use charges but to make the CAD toolThe radical solution is to use charges, but to make the CAD tool calculate analytically partial derivative of the charge for SS.I.e. calculate capacitances and use Cap. in the SS analysis. F HB h d di tl t t t Thi i tFor HB charges are used directly to get currents. This is easy to arrange for default models- you provide equations for the charges and capacitances (ADS)


GaAs and CMOS FET

I Angelov

Cap Implementation6-Mixed Charge-Current: Results33

I.Angelov

-2 1 -1 6 -1 1 -0 6 -0 1 0 4-2 6 0 9

0.01

0.02

0.03

0.00

0.04

imag

(Y(1

,1))

imag

(Y(3

,3))

imag

(Y(5

,5))

imag

(Y(9

,9))

0.005

0.010

0.015

0.020

-im

ag

(Y(1

,2))

-im

ag

(Y(5

,6))

-im

ag

(Y(9

,10

))

DimagY12maxindep(DimagY12max)=plot_vs(DImagY12, VGS)=-0.099freq=4.000000GHz, VDS=12.000000

-0.200

DimahY11maxindep(DimahY11max)=plot_vs(DImagY11, VGS)=2.153freq=4.000000GHz, VDS=12.000000

-1.000

2

3DimahY11max

DimagY12maxindep(DimagY12max)=plot_vs(DImagY12, VGS)=-0.099freq=4.000000GHz, VDS=12.000000

-0.200

DimahY11maxindep(DimahY11max)=plot_vs(DImagY11, VGS)=2.153freq=4.000000GHz, VDS=12.000000

-1.000

0.005

0.010

0.015

0.020

-ima

g(Y

(1,2

))-im

ag

(Y(5

,6))

-im

ag

(Y(9

,10

)) Difference isvery small<2%

2.1 1.6 1.1 0.6 0.1 0.42.6 0.9

VGS-2.1 -1.6 -1.1 -0.6 -0.1 0.4-2.6 0.9

0.000

VGS

-2.1 -1.6 -1.1 -0.6 -0.1 0.4-2.6 0.9

-1

0

1

2

-2

VGS

DIm

agY

12

DimagY12max

DIm

agY

11

DI Y11 100*(i (Y(1 1)) i (Y(9 9)))/i (Y(1 1))

Eqn DImagY12=100*(imag(Y(1,2)) -imag(Y(9,10)))/imag(Y(1,2))

2 4 6 8 100 12

0.000

VDS

ImaginaryY11,Y12 vs. Vgs and Y12 vs. Vds fordifferent implementation Cap MCC-Verilog MCC SDD Eqn DImagY11=100*(imag(Y(1,1))-imag(Y(9,9)))/imag(Y(1,1))

30

])::,3

])::,

2])

])])::,1

])

IgcapdefVgs=mag(real(igcapdef.i[::,0]))=1.682E-4

-0.700

IgVerMCCVgs=real(igVcharge.i[::,0])=-4.941E-13

-0.700

different implementation, Cap,MCC Verilog,MCC SDD

Igcap=10 ^-4AIgMCC=10-14A

0

10

20

Bm

(Vlo

ad

VC

h[::

,3]

(Vlo

ad

Ch

arg

ed

ef[

(Vlo

ad

Ch

arg

ed

ef[

Bm

(Vlo

ad

VC

h[::

,2]

Bm

(Vlo

ad

VC

h[::

,1]

(Vlo

ad

Ch

arg

ed

ef[

0 00010

0.00015

0.00020

de

f.i[::

,0])

) Igcapdef

ap

.i[::,

0])

)g

e.i[

::,0

])3

.i[::,

0])

( g g [ , ])IgMCCSDDVgs=real(igSDD3.i[::,0])=-1.163E-14

-0.700

IgMCC 10 14AIgCharge=10-28A

-4 -3 -2 -1 0-5 1-10

Vgs

dB

dB

md

Bmd

Bd

Bd

Bm

-4 -3 -2 -1 0-5 1

0.00000

0.00005

0.00010

-0.00005

ma

g(r

ea

l(ig

cap

ma

g(r

ea

l(ig

Vca

rea

l(ig

Vch

arg

IgVerMCC

rea

l(ig

SD

D3

IgMCCSDD


GaAs and CMOS FET

Vgs

PS:Charge model,MCCVerilog,MCCSDD; Generated Ig for different implementatioons

I AngelovDispersion Modelling Implementation

34

I.Angelov

1 Simple> Rc,Crf at the ouput, usually implemented in CAD toolsRc is bias dependent! Rc1=Rcmin+Rc/(1+tanp)

2 Back-gate Approach: (J. Conger, A. Peczalski, M. Shur, SC,Vol. 29, No.1),ADS20093 Physical Approach: (K. Kunihiro, Y.Ohno, ED, Vol. 43, No. 9)4 Device is symmetric>input (Rcin,Crfin)-output dispersion, Rc,Crf

Inputpdispersion

Output DispersionRc,Crf,Rc1=Rcmin+Rc/(1+tanp)Backgate voltage

E tended EC for dispersion Modelling combined Rc and back gate 5 par


GaAs and CMOS FET

Extended EC for dispersion Modelling–combined Rc and back-gate:5 par.

I AngelovModel Parameters tot. 69

35

I.Angelov

GaN Ids parameters-12

Parasitics&package

FETGaN2FET1

Cap parameters-15Thermal parameters-8Breakdown-7I 3

FET1

Vbdgd=50 VVbdgs=10 VKbdgate=0.0001Vsb2=0 VEbd=0.3Vbdrain=60 VLsb0=0.05Cdel=2 fF

Ls=8.8 pHLd=100 pHLg=100 pHRdsleak=1 GOhmRgsleak=1 GOhmRgdleak=1 GOhmRgd=5 OhmRd2=0 Ohm

Tamb=25TcRtherm=0.005TcCrf=+0.002TcCgd0=+0.002TcCgs0=+0.002TcRs=+0.0002TcP1=-0.0025TcIpk0=-0.004

P21=0.21P20=0.03P11=0.25P10=0.48Cgdpe=8 fFCgd0=376 fFCgdpi=200 fFCgs0=3500 fF

Alphar=0.1P3=0.05P2=-0.03P1=0.62DVpks=0.5 VVpks=-2.4 VIpk0=0.61 AIdsmod=1

Igs-3

N i th G N d l i l t d i V il A ADS 2009

tau=2 psecPbdg=0.45Vbdgd 50 V

Rdel=2 kOhmRcin=500 kOhmCrfin=20 fFKbgate=0.01Crf=100 fFRc=10 kOhmRcmin=0.4 kOhmLs 8.8 pH

Rd=1.55 OhmRs=0.88 OhmRi=2.5 OhmRg=2.5 OhmVjg=0.9 VPg=15.2Ij=0.0005 ATamb 25

Ctherm=0.001 FRtherm=8.5 OhmP111=0.008P41=0.25P40=0.48P31=0.21P30=0.03P21 0.21

Cgspi=615 fFCds=800 fFB2=3.0B1=0.08Lvg=0.000lambda=0.02Alphas=0.7Alphar 0.1

New in the GaN model implemented in VerilogA , ADS 2009:1 f1(Ψ)=1+Tanh[Sinh(P1.Vgs)]2Rd and Rs are Bias( Rd2) and Temperature Dependent (TcRs),R bd R *(1 Rd2*(1 t h(Ψ))) Rdbd Rd*(1 Rd2*(1 t h(Ψ)))Rsbdep=Rs*(1+Rd2*(1+tanh(Ψ))); Rdbdep=Rd*(1+Rd2*(1+tanh(Ψ))); RsbdepT=Rsbdep*(1+TcRs*DTj); RdbdepT=Rdbdep*(1+TcRs*DTj);3Delay:Rdel,Cdel,4 Backgate dispersion-Kbgate5Breakdown for GS GD Junctions: Kbdgate Vbdgs Vbdgd Pbdg


GaAs and CMOS FET

5Breakdown for GS,GD Junctions: Kbdgate,Vbdgs,Vbdgd, Pbdg

I AngelovSpar. Measurements & FIT.

36

I.Angelov

))

S(1

,1)

S(3

,3)

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

-2.5

2.5

f (1 000GH t 30 00GH )

S(2

,1)

S(4

,3)

freq (50 00MHz to 14 05GHz)

S(3

,3)

S(1

,1)

-0.2 -0.1 0.0 0.1 0.2-0.3 0.3

freq (50 00MHz to 14 05GHz)

S(4

,3)

S(2

,1)

freq (1.000GHz to 30.00GHz) freq (1.000GHz to 30.00GHz)

- - - - 0 0 0 0 0- 0(1,2

)(3

,4)

(2,2

)(4

,4)

,4)

,2)

4,4)

2,2)

freq (50.00MHz to 14.05GHz) freq (50.00MHz to 14.05GHz)

0.20

0.15

0.10

0.05

0.00

0.05

0.10

0.15

0.20

0.25

0.25

freq (1.000GHz to 30.00GHz)

S(

S(

freq (1.000GHz to 30.00GHz)

S(

S( -0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

-0.20

0.20

freq (50.00MHz to 14.05GHz)

S(3

,S

(1,

freq (50.00MHz to 14.05GHz)

S(4

S(2

AlGaN/GaN HEMT SiC FET. Measured and modelled Spar. For LS model, it is important to look for the global fit.For harmonics DC and Spar fit is not enough!!!


GaAs and CMOS FET

For harmonics, DC and Spar fit is not enough!!!

I Angelov

Importance of Correct Derivatives37

I.Angelov

For LS & Harmonics modelling we need correct derivativesSelf-Heating, Dispersion, Memory effects, complicate the picture. DC data for Ids harmonics are often noisy! Solution:DC data for Ids harmonics are often noisy! Solution:1Power Spectrum evaluation (PS); 2Load Pull or LSNA or Combined Load Pull & LSNA Evaluation!!

-10

0

10

2025

P1s

P2s

P3sP1

P2

P30.10

0.15

0.20

Ids1Ids

DId

s1

Example: we change the shape of Ids at

-1.3 -0.8 -0.3-1.8 0.2

-20

10

-30

Vgs

-1.3 -0.8 -0.3-1.8 0.2

0.05

0.00

Vgs

6

8

0 002

0.004

shape of Ids at pinch-off, i.e. P3=0.2 toP3=0.5 in Ids

0

2

4

6

-2

DP

1D

P2

DP

3

-0.008

-0.006

-0.004

-0.002

0.000

0.002

-0 010

DId

s1

parameters. Change <2% for Ids, 4-7 dB in harmonics!


GaAs and CMOS FET

-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0-1.8 0.2

Vgs

-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0-1.8 0.2

0.010

Vgs

I Angelov

PS Measurements-Harmonics vs. Vgs38

I.Angelov

Pin,RF freq, Vds Constant. 1) RF Low Freq > current source1) RF- Low Freq.> current source2) RF-High Freq.> capacitancesSpectrum analyzer(SA) or ScalarNA(SNA) or Power meterwith diplexer filter.

1 C lib t th i t (Pi 10 dB f SiC d G N) t th d i t i l f f d d h i1 Calibrate the input power (Pin=10 dBm for SiC and GaN) at the device terminal for fund. and harmonics.2 Calibrate losses of output cables,diplexer, SA(orSNA);Keep attenuators directly at the bias tee, close to DUT!!!3 Measure 1,2,3 harmonics sweeping Vgs(10pts), for several Vds (Vds=0.2; 8V, 16V, 24V for GaN, SiC)

20

oa

d[::

,1])

oa

d[::

,2])

oa

d[::

,3])

Measured and modeled PS GaN 200 umf1b(Vgs)=1+Tanh(Sinh(P1.Vgs))

Pin=10dBm;RF=1GHz

-30

-10

10

HB

1P

Svs

Vg

s15

dB

m..V

loH

B1

PS

vsV

gs1

5d

Bm

..Vlo

HB

1P

Svs

Vg

s15

dB

m..V

lod

Bm

(Vlo

ad

[::,1

])d

Bm

(Vlo

ad

[::,2

])d

Bm

(Vlo

ad

[::,3

])


GaAs and CMOS FET

-5 -4 -3 -2 -1-6 0

-50

Vgs

dB

m(H

dB

m(H

dB

m(H

I Angelov

39Combined LSNA & Load-Pull Measurements-best approach for Device and LS evaluation!

I.Angelov

Voltages & Harmonics extracted from the waveforms at the device terminal!LSNA & Load Pull > better understanding of device behavior at high frequency!

(Ref: On the modeling of High Frequency& High Power Limitations of FET, INMMIC, Rome)( g g q y g , , )

Poutmeasindep(Poutmeas)=Poutmeas=26.598

9.942Poutmeasindep(Poutmeas)=Poutmeas=26.598

9.942

10

15

20

25

30

Po

utm

Poutmeas

Po

uts

2GHz Poutmeasindep(Poutmeas)=Poutmeas=16.476


10.150

10

15

20

25

30

Po

utm Poutmeas

Po

uts

12GHzPoutmeasindep(Poutmeas)=Poutmeas=14.013


10.296

10

15

20

25

30

Po

utm

Poutmeas

Po

uts

18GHz

72 12

10

5

Pinm

0 25

5 10 150 205

Pinm

10 15 205 255

Pinm

For the same input power 10 dBm: 2GHz >Pout=27 dBm 12GHz>Pout=16.4 dBm 18GHz>Pout=14 dBm

2GHz

0.00

0.05

0.10

0.15

0.20

0.25

i2m

tsi2

sts

i1m

tsi1

sts

0.00

0.05

0.10

0.15

0.20

i2m

tsi2

sts

i1m

tsi1

sts

12GHZ18GHz

0 00

0.05

0.10

0.15

i2m

tsi2

sts

i1m

tsi1

sts

2 4 6 8 10 12 140 16

-0.05

v2mtsv2sts

5 6 7 8 9 104 11

-0.05

-0.10

v2sts6.5 7.0 7.5 8.0 8.5 9.06.0 9.5

0.00

-0.05

v2sts

The reason for the power decrease: we do not reach at high frequency the DC (Low Frequency)Knee: 2GHz Vmin=0 8V(DCKnee GaAs) 12GHz Vmin=4 5V 18GHz Vmin=6 3V


GaAs and CMOS FET

Knee: 2GHz Vmin=0.8V(DCKnee GaAs) 12GHz Vmin=4.5V 18GHz Vmin=6.3VThe high freqency IV slump is modeled with the gate control network Rdel,Cdel

I Angelov

40Empirical &Table Based (ETB) LS Model

I.Angelov

ETB: Modeling Complicated IV & Cap shapes. Empirical model serves as spline function. Combine the best of Empirical and Table Based ModelsComplicated data (parts of the model) loaded using data set

ETB LSM FET

Complicated data (parts of the model) loaded using data set.High accuracy and good description of harmonics and good convergence. Significant reduction of required measured points(100-200 OK). Easy to extrapolate out of the measured range.

ETB LSM FETI =Ipk0.tanh(α table) (1+tanh(P1*ψ table)) (1+λtable)

1 Difficult to model parameters replaced with table data.2 G d d i fi it b f d i ti

DataAccessComponentDAC_psiFile="psi3.citi"

DAC

DataAccessComponentDAC_lambdaFile="lambda1 citi"

DAC

2. Good convergence and infinite number of derivatives.3. User access to technologically & mounting dependent parameters: Ipk0, Vpk, P1, Ron, Rtherm, Ctherm etc.

iVal2=_v7iVar2="VBE"iVal1=_v8iVar1="VCE"ExtrapMode=Interpolation ModeInterpDom=RectangularInterpMode=LinearType=CITIfile

p

iVal2= v7iVar2="VBE"iVal1=_v8iVar1="VCE"ExtrapMode=Interpolation ModeInterpDom=RectangularInterpMode=LinearType=CITIfileFile= lambda1.citi

1 ETB FET (MTTS 1999 pp. 2350)2 ETB HBT (EUMC 2004 pp. 229)3 ETB FET (Wiley Int. J. of RF and Microwave Computer-Aided Engineering Vol.14, No. 2, 2004, pp. 122, Johnson et al.)


GaAs and CMOS FET

_

Complicated Ids(Vgs) Complicated Ids(Vds)

I Angelov

It is Time to Integrate Circuit,Physical Models41

I.Angelov

It is Time to Integrate Circuit,Physical Models!It is Time to Integrate Circuit,Physical Models!Now, we can trust Physical, Circuit models and we can try to integrate them:

1Circuit designers can create the ideal transistor for their application.2Using Physical models, we can design the device for the2Using Physical models, we can design the device for the specific application.3 Measurements&Circuit models provide feedback to improve deviceimprove device.4. Everything made on Si ->GaN,GaAs?


GaAs and CMOS FET

I Angelov

CMOS Large Signal Model42

I.Angelov

0 025

0,03

0,035

0,04GmCMOSGmVd02

GmVd06

GmVd08

GmVd04

G Vd1)

Gmax

Ids, Gm shape similar for0,015

0,02

0,025IdsvsVgsCMOS

IdsVd02IdsVd04

IdsVd06)

0 005

0,01

0,015

0,02

0,025 GmVd1

GmVd12

Gm

(mA

/V)

DVpk

Ids, Gm shape similar for CMOS, GaAs MESFET.CMOS-Ids exponential for small currents0

0,005

0,01

IdsVd06

IdsVd08IdsVd1

IdsVd12

Ids(

A) Ipk0

Gm vs. Vgs0

0,005

0 0,2 0,4 0,6 0,8 1

Vgs(v) Vpks

0.025

small currents0 0,2 0,4 0,6 0,8 1

Vgs(v)

αs

Ids vs. Vgs

0,0001

0,001CMOSf201520

0 00

0.010

0.015

0.020

IDS

.i, A

MO

S2e

xp..

IDS

.i

λ

αs

10-6

10-5

0 0,5 1 1,5 2

Vg=0.1Vg=0.2Vg=0.3Vg=0.4Id

s(A

)

Vds

0.5 1.0 1.50.0 2.0

0.005

0.000

DC_FET2.VDSVDS

M

ar


GaAs and CMOS FET

Measured and modeled IV

I AngelovEC CMOS-Bulk influence:

43

I.Angelov

Simplified EC CMOSGaAs and CMOS EC similar

Equivalent Circuit includingS lf h i B lk &

CC10C=Cgbulk

LL1

R=0.001L=Ld

RR27R=Rgdleak

RR2R Rd

PortDrainNum=1

PortGate

RR1

LL2L=Lg

RR14R R d

CC6C=Cgdpe

Self-heating, Bulk &Bias dependent Dispersion

Rc1= Rcmin+Rc/(1+tanp)Different is:Bulk influence:

Vgdc

Vgsc

RR21R=Rgbulk kOhm

CC3C=Cds

R

R=Rd

CC8C=Crf

RR5R=Rdel

Num 1

CC11C=Cdbulk

RR20R=Rdbulk

GateNum=2

R

R=RgR=0.001L=Lg

CC7C=Ctherm1

RR3R=Ri

R=Rgd

Different is:Bulk influence:RC Branches: Gate-Bulk, Drain-Bulk, Source-Bulk.

Vds

Vrf

Vgs

PortS

RR24R=Rsbulk

CC13

RR9R=Rc1

RR28R=Rbg

LL3L L

PortBulkNum=4

CC5C=Cdel

CC9C=Crf in

RR15R=Rcin

RR7R=Rtherm+0.001

RR13R=Rbg

RR4R=Rs


GaAs and CMOS FET

SourceNum=3

C=CsbulkR=0.001L=Ls

I AngelovIds Equations CMOS- symmetric

44

I.Angelov

A symmetric equation for Ids for accurate modeling for positive and negative Vds. To obtain this: Ids =Idsp-Idsn; Vgs and Vgd control Ids :

(1 tanh( ))(1 tanh( ))

(1 ((( / ) 1)))

ds dsp dsn

dsp pk p p ds

I I I

I I V

V VV

ψ α

λ λ

= −

= + +

1

1

ex

(1 exp((( / ) 1)))

(1 tanh( ))(1 tanh( ))

(1 ((( ) 1)))p /

p ds p ds kn

dsn pk n n ds

n n ds kds n

V V

I

V V

V

I V

V λ

λ λ

ψ α

λ

+ + −

= + +

− − −This term providesexponential

2 31 2 3

2 31 2 3

( ) tanh( )

( ) ( ) ( )

( ) ( ) ( )

α

ψ

ψ

= − Δ + Δ

= − + − + −

= − + − + −

p m pkgs gs gs

gd gd gd

m pk m pk

n m pk pk pk

V V V V V V

P V P V P V

P V P V V

V V V

V PV V

exponential dependence

*

( ) tanh( )

tanh( )

tanh( )

α

α

λ λ λ ψ

= − Δ + Δ

= Δ

= − Δ

pk ds pks pks pks ds

im i i ds

i

s

s

V V V V V V

P P P V


GaAs and CMOS FET

[1 tanh( )]; [1 tanh( )]α α α ψ α α α ψ= + + = + +p r s p n r s n

I Angelov

Cap Equations CMOS45

I.Angelov

CMOS Cap shape & equations different from GaAs FET!Defined -∞+ ∞ ; Infinite numbers of derivatives!!!!

( )( )

( )( )

( )

0 1020 212

11 10

11 tanh

+ += + + +

+ −

gs gsgs gsp ds

gs

C V PC C P P V

P V PCap parameters:Cgsp,Cgs0;P10,P11,P20,P21Cgdp Cgd0;P40 P41 P30 P31( )

( )( )( )0 40

30 312

41 40

11 tanh

+ += + + −

+ −

∂∂

gd gsgd gdp ds

gd

d

C V PC C P P V

P V P

VV 2E-13

3E-13

4E-13

5E-13

6E-13

Cg

sg 2E-13

3E-13

4E-13

Cg

dg

Cgdp,Cgd0;P40,P41,P30,P31

; ∂∂

= =∂ ∂

gs gdgsc gs gdc gd

VVI C I C

t t

4E 13

5E-13

6E-13

3E-13

4E-13

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

-1.2

1.8

1E-13

2E-13

0

Vgs

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

-1.2

1.8

1E-13

0

Vgs

Implementation Cap:1 Calculated the capacitances

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.0 2.0

1E-13

2E-13

3E-13

4E-13

0

Vds

Cg

sg

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.0 2.0

1E-13

2E-13

0

Vds

Cg

d1 Calculated the capacitances2 Calculate DVgs/dt, DVgd/dt3 Calculate current via Cap.Forced charge conservation for


GaAs and CMOS FET

CMOS Capacitances implemented in ADSForced charge conservation forIdc=0 via cap ( use DCblock, Dcfeed)!

I Angelov

FET examples:FIN FET – LS model similar to CMOS46

I.Angelov

0 00

0.01

0.02

0.03

i, A

me

as

0 00

0.01

0.02

0.03

me

as

d.i

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0-0.6 1.2

-0.02

-0.01

0.00

-0.03

vds

id.i

Idsm

-0.2 0.0 0.2 0.4 0.6 0.8 1.0-0.4 1.2

-0.02

-0.01

0.00

-0.03

Vgsmeas

Idsmid

Measured and modelled IV (FINFET 36 um tot. gate size) ADSvdsVds

vgs

0.9

1.0

(1,1

))(3

,3))

1.5

2.0

2.5

(2,1

))(4

,3))

0.8

1.0

0.25

0.30

5 10 15 20 25 30 35 40 450 50

0.7

0.8

0.6

freq, GHz

mag

(S(

mag

(S(

20

0

5 10 15 20 25 30 35 40 450 50

0.5

1.0

0.0

freq, GHz

mag

(S(

mag

(S(

150

200

200

5 10 15 20 25 30 35 40 450 50

0.2

0.4

0.6

0.0

freq, GHz

ma

g(S

(2,2

))m

ag

(S(4

,4))

5 10 15 20 25 30 35 40 450 50

0.05

0.10

0.15

0.20

0.00

freq, GHz

ma

g(S

(1,2

))m

ag

(S(3

,4))

100

5 10 15 20 25 30 35 40 450 50

-60

-40

-20

-80

freq, GHz

phas

e(S

(1,1

))ph

ase(

S(3

,3))

5 10 15 20 25 30 35 40 450 50

50

100

150

0

freq, GHz

phas

e(S

(2,1

))ph

ase(

S(4

,3))

5 10 15 20 25 30 35 40 450 50

-100

0

100

-200

freq, GHz

ph

ase

(S(2

,2))

ph

ase

(S(4

,4))

5 10 15 20 25 30 35 40 450 50

40

60

80

20

freq, GHz

ph

ase

(S(1

,2))

ph

ase

(S(3

,4))


GaAs and CMOS FET

Measured and modeled S-parameters, ADS

I Angelov

RF & LF CMOS Noise Model 47

LS implementation of Pospiezalski Noise ModelMain Noise Contributor is high gate resistance!!! I.Angelov

T

Cgd

Cgdp

RgdRgLgGate DrainLdRd

Main Noise Contributor is high gate resistance!!!

Original SS Pospiezalski Noise model is accurate, because it is using directly derivatives Gm,Gds in th i l l ti d fit f SS i l tTg

Ri

Td

Ctherm

Rtherm

Vrf

Crf

Cgs CrfCds

CC10C=Cgs

m1indep(m1)=m1=4.709Vds=1.000000, freq=20.00000GHz

0.650

7

8

9

nf(2

)G

Hz.

.NF

4

5

6

7

8

eExp

..nfm

in.N

Fm

in

the noise calculations and fit for SS equivalent circuit is usually very good.

RinRFCinRF

SourceRs Ls0.55 0.60 0.65 0.70 0.750.50 0.80

5

6

7

4

SP1.SP.Vgs

SP

1.S

P.n

m1

vg

NF

CM

OS

20G

7 12 172 22

1

2

3

4

0

freq, GHz

f2x2

0HF

nois

SP2.SP.freq, GHz

SP

2.S

P

M d dNoise parameters: 4 RF+6 LFNTd, Tg, Td1, IdminLF noise: KLF1,KLF2,Ffe,fgr,Kf,Af

Id 1 b (Id ) b (I ) Tdi Td*(1 t h( b (Vd Vk )))

S S eq, G Measured and modelled NF at 20 GHz

Measured & modelled minimum NF vs. Freq.

Idn1=abs(Ids)+abs(Igs);Tdi=Td*(1+tanh(abs(Vds-Vkn)))PPout=Lw*4*Kb*TambK*abs(sqrt((Tdi/Tamb)*Idn1+Td1*(Idn1-Idnmin)^2)^2)*(1+KLFO)

KLFO=KLF1*(1/(1+freq^Ffe)+KLF2/(1+(freq/fgr)^2))Igs_NoiseSqrd=2*qe*Igs*deltaF+Kf*(Igs^Af)/(freq^Ffe*deltaF)Igd NoiseSqrd=2*qe*Igd*deltaF+Kf*(Igd^Af)/(freq^Ffe*deltaF)

Work to be done to reduce Rg to improve h i


GaAs and CMOS FET

g _ q q g ( g ) ( q )TgRi=Tg*(1+tanp)*tanh(alphap*Vds)*(1+lambda*Vds)the noise.

I AngelovConclusions42

48

I.Angelov

A general purpose large-signal modeling approach was proposed, implemented in CAD t l d i t ll l t d M d l h d d t bl b h i itools and experimentally evaluated. Models show good accuracy and stable behavior in HB simulations.

AcknowledgementsSSF S d•SSF, Sweden

Colleagues : C. Fager, K. Andersson, M. Ferndahl,, H. Zirath, N. Rorsman, D. Schreurs, M. Mierzwinski, A. Inoue, K. Kanaya, S. Maas, W. Curtice for the help and valuable discussions S D GLfor the help and valuable discussions. S.D.GL. Thank you for your attention!Meyer’s Law, part of Murphy’s LAW:It is a simple task to make things complex, but a complex task to make them simple.

Questions?


GaAs and CMOS FET

Questions?

I AngelovReferences

49

I.Angelov[1] S. Maas, Nonlinear Microwave and RF circuits, Artech House 2003.[2] R. Anholt, "Electrical and Thermal Characterization of MESFETs, HEMTs, and HBTs," Artech House, 1995.[3] L. D. Nguyen, L. Larson, U. Mishra “Ultra-High-Speed MODFET: A Tutorial Review”, Proceedings of the IEEE, Vol.80, N4, 1992, pp.494[4] H. Rohdin, P. Roblin,”A MODFET DC Model with Improved Pinch off and Saturation Characteristics” IEEE Trans ED, Vol. ED-33, N5, 1986, pp.664-672.[5] R. Johnoson, B. Johnsohn, A. Bjad,” A Unified Physical DC and AC MESFET Model for Circuit Simulation and Device Modeling” IEEE trans ED, Vol. ED-34,N9,1987, pp.1965-1971.[6] M. Weiss, D. Pavlidis, “The Influence of Device Physical Parameters on HEMT Large-Signal Characteristics”, IEEE Trans. MTT, Vol-36, N2, 1988, pp.239-244.[7] C. Rauscher, H. A. Willing, ”Simulation of Nonlinear Microwave FET Performance Using a Quasi-Static Model,” IEEE Trans. MTT., vol. MTT-27, no. 10, pp. 834-840, Oct. 1979.[8] W C i “A MESFET M d l f U i h D i f G A I d Ci i ” MTT l 28 448 4 1980[8] W. Curtice, “A MESFET Model for Use in the Design of GaAs Integrated Circuit,” MTT., vol. 28, no. 5, pp. 448-455, 1980.[9] A. Materka and T. Kacprzak, “Computer Calculation of Large-Signal GaAs FET Amplifiers Characteristics," IEEE Trans. MTT.", vol. 33, no. 2, pp. 129-135, 1985.[10] T. Brazil,"A universal Large-Signal Equivalent Circuit Model for the GaAs MESFET," Proc. 21st EuMC, pp. 921-926, 1991[11] G. Dambrine and A. Cappy,”A new Method for Determining the FET Small-Signal Equivalent Circuit”, IEEE Trans. MTT, vol. 36, pp. 1151-1159, July 1988.[12] Berroth, M.; Bosch, R.; High-frequency equivalent circuit of GaAs FETs for large-signal applications MTT Vol.39, Issue 2, Feb. 1991 pp: 224 - 229 [13] Berroth,M.; Bosch R.”Broad-band determination of the FET small-signal equivalent circuit” MTT, Vol.38, N7, July 1990 pp: 891 - 895 [14] M. Ferndahl at all, “A general statistical equivalent-circuit-based de-embedding procedure for high-frequency measurements,” IEEE Trans. MTT., vol56, n 12, 2008, pp.2962-2700[15]D. Root, B. Hughes, ”Principles of nonlinear active device modeling for circuit simulation”, #2 Automatic radio Frequency Technique Group Conf. ,Dec 1988[16] D. Root, S. Fan, J. Meyer,” Technology-Independent Large-Signal FET Models: A Measurement-Based Approach to Active Device Modeling, 15 ARMMS Conf, Bath UK Sept. 1991.[17]D Root “Measurement based mathematical active device modeling for high frequency circuit simulation ” IEICE Trans Electron vol E82 C no 6 pp 924 936 June 1999[17]D. Root, “Measurement-based mathematical active device modeling for high frequency circuit simulation,” IEICE Trans. Electron., vol. E82-C, no. 6, pp. 924-936, June 1999[18]D. Root ; Nonlinear charge modeling for FET large-signal simulation and its importance for IP3 and ACPR in communication Circuits and Systems, MWSCAS 2001. Proc.4th IEEE Midwest Symp.Vol. 2, 14-17 pp.768 - 772 [19] R. B. Hallgren "TOM3 Capacitance Model: Linking Large- and Small-signal MESFET Models in SPICE," MTT, vol.47, n5, pp. 556 (May, 1999).[20] R. J. Trew, "MESFET Models for Microwave CAD Applications," Microwave and Millimeter-Wave CAE, vol. 1, no. 2, pp. 143-158, April 1991.[21] J. P. Teyssier at all, ”A new Nonlinear I(V) Model for FET Devices Including Breakdown Effects,” IEEE Microwave and Guided Wave Letters, vol. 4, no.4, pp.104-107, April 1994.[22] K. Kunihiro, Y. Ohno, ”A Large-Signal Equivalent Circuit Model for Substrate-Induced Drain-Lag Phenomena in HJFET’s” IEEE Trans. ED,Vol.43, N9,1996, pp.1336-1342.[23] J. Conger, A. Peczalski, M. Shur,” Modeling Frequency Dependence of GaAs MESFET Characteristics” IEEE Journal of Solid State Circuits, Vol. 29, N1, 1994 pp. 71-76[24]. Scheinberg, N.; Bayruns ” A low-frequency GaAs MESFET circuit model”, Solid-State Circuits, IEEE Journal of ,Volume: 23 , Issue: 2 , April 1988,pp. 605 - 608 [25]Canfield, P. Modelling of frequency and temperature effects in GaAs MESFETs”; Solid-State Circuits, IEEE Journal of, Volume: 25, Issue: 1, Feb. 1990, pp. 299 – 306 [26] M Lee at all “A Self-back-gating GaAs MESFET model for Low-Frequency anomalies” IEEE Trans on ED Vol 37 N 10 Oct pp 2148-2157[26] M. Lee at all A Self-back-gating GaAs MESFET model for Low-Frequency anomalies , IEEE Trans. on ED, Vol.37, N.10 Oct., pp.2148-2157. [27] C. Camacho-Penalosa and C. Aitchison, ”Modeling Frequency Dependence of Output Impedance of a Microwave MESFET at Low Frequencies,” Electronics Letters, Vol. 21, N 12, pp. 528-529, June 1985[28] J. Reynoso-Hernandez and J. Graffeuil,”Output Conductance Frequency Dispersion and Low-Frequency Noise in HEMT's and MESFET's,” MTT-37, n. 9, pp. 1478-1481, Sept. 1989.[29] P. Ladbrooke, S. Blight, ”Low-Field Low-Frequency Dispersion of Transconductance in GaAs MESFETs with Implication for Other Rate-Dependent Anomalies,” IEEE Trans. ED-35, no. 3, pp. 257, March 1988.[30] G. Kompa, ”Modeling of Dispersive Microwave FET Devices Using a Quasi-Static Approach,” Int. Journal of Microwave and Millimeter-Wave Computer-Aided Engineering, vol. 5, No 3, pp.173-194, 1995[31] M. Paggi at all”Nonlinear GaAs MESFET Modeling Using Pulsed Gate Measurements, ”IEEE Trans. MTT-36, no. 12, pp. 1593-1597, Dec.,1988.[32] J. P. Teyssier at all "A Pulsed S-parameter Measurement set-up for the nonlinear characterization of FETs and Bipolar Transistors," Proc. 23rd EuMC, pp. 489, Madrid, 1993.[33] J. M. Lopez at al., Design Optimization of AlInAs-GaInAs HEMTs for High Frequency Applications!”, IEEE Trans. ED, vol 51, n 4, April 2004, pp. 521-528 [34] J. Bandler at all ”Efficient Large-Signal FET Parameter Extraction Using Harmonics,” MTT-37, no. 12, pp. 2099-2108, Dec. 1989.[35] Angelov at all.Extensions of the Chalmers Nonlinear HEMT and MESFET model, MTT, Vol. 46,N 11, Oct. 1996, pp.1664-1674.[35] Angelov at all.Extensions of the Chalmers Nonlinear HEMT and MESFET model, MTT, Vol. 46,N 11, Oct. 1996, pp.1664 1674. [36] Angelov, H. Zirath, N. Rorsman, "Validation of a nonlinear HEMT model by Power Spectrum Characteristics," IEEE MTTS Digest, pp.1571-1574, 1994.[37] Angelov A. Inoue, T. Hirayama, D. Schreurs, J. Verspecht “On the Modelling of High Frequency& High Power Limitations of FETs INMMIC Rome 2004[38] Angelov at all “ On the large-signal modelling of AlGaN/GaN HEMTs and SiC MESFETs, EGAAS 2005 pp.309 - 312 [39] Angelov at all “Large-signal modelling and comparison of AlGaN/GaN HEMTs and SiC MESFETs”, 2006. APMC 2006 pp:279 - 282 [40] ADS,MO, Ansoft Designer user manuals[41] Angelov at all “An empirical table-based FET model” MTT, Vol. 47, N12, Dec.1999 pp:2350 - 2357[42] Angelov at all “An Empirical Table Based HBT large signal model”;EUMC, 2004. 34 Vol. 1, 11-15 Pp:229 – 232[43] Angelov at all “CMOS large signal model for CAD,.; Microwave Symposium Digest, 2003 Vol. 2, 8-13 June 2003 pp:643 - 646[44] Angelov at all “CMOS Large Signal and RF Noise Model for CAD, EUMC, 2006. Sept. 2006 Pp.217 - 220 [45] Johnson at all ”Generalized nonlinear FET/HEMT modeling (p 122-133) Wiley International Journal of RF and Microwave Computer-Aided EngineeringVol.14, No. 2, 2004, pp. 122[46] S G t ll” 220 GH (G B d) Mi t i MMIC Si l E d d R i ti Mi Mi d Wi l C t L tt IEEE V l 18 I 3 M h 2008 215 217


GaAs and CMOS FET

[46] S.Gunnarsson at all” 220 GHz (G-Band) Microstrip MMIC Single-Ended Resistive Mixer ; Microwave and Wireless Components Letters, IEEE Volume 18, Issue 3, March 2008 pp.215 - 217 [47] S.Gunnarsson at all A 220 GHz Single-Chip Receiver MMIC With Integrated Antenna ;Microwave and Wireless Components Letters, IEEE Volume 18, Issue 4, April 2008 pp:284 – 286[48] S.Gunnarsson at all; A G-band (140 – 220 GHz) microstrip MMIC mixer operating in both resistive and drain-pumped mode , IEEE MTT-S 2008 pp 407 – 410[49]T. Oishi, H. Otsuka, K. Yamanaka, Y. Hirano, I. Angelov Semi-physical nonlinear model for HEMTs with simple equations INMMIC 2010 Göteborg

I Angelov

Linear Scaling CMOS50

I.Angelov

Rgbulk=Rgbulkw*WtotIj=Ijw*WtotLs=2 pH+Lsw

Cgspi=Cgspiw*(Wtot+0.01)Cds=Cdsw*(Wtot+0.05)Ipk0=Ipk0w*Wtot

Scaling Parameters:Nfing Wfing Lfing Gcont Lgate

Wtot=Nfing*Wfing*1000Rcmin=Rcminw*WtotRsbulk=Rsbulkw*WtotRdbulk=Rdbulkw*Wtot

g g

Cgdpe=Cgdpew*(Wtot+0.01)Cgd0=Cgd0w*(Wtot+0.01)Cgdpi=Cgdpiw*(Wtot+0.01)Cgs0=Cgs0w*(Wtot +0.01)

g p g p ( ) Nfing,Wfing,Lfing,Gcont.LgateTot. number of model parameters, including self-heating, dispersion and

Wtot1=Nfing*Wfing*Lfing

Rd=0.01+Rdw/WtotRs=0.01+Rsw/WtotRi=0.01+Riw/WtotRg=0.01+Rgw/Wtot

self heating, dispersion and scaling: 70

MOS l d2 20 1

Ld=2 pH+LdwLg=2 pH+ LgwRtherm=0.01+Rthermw/WtotRgd=0.01+Rgdw/Wtot MOSscaled2x20n1

CMOS1

Lfing=0 12 umWfing=10 umNfing=2Rc=5 kOhmRcminw=200 OhmRsbulkw=1.7 kOhm

TcP1=-0 001TcIpk0=0.001Ctherm=0.01 FRthermw=1.0 OhmLdw=28 pHLsw=15 pH

P111=0 0001P41=1.45P40=0.02P31=0.32P30=0P21=0.32

Vsb2=0 VVtr=3.0 VLsb0=0B2=3.7B1=0.1Lvg2=-0.00015

P2=+0 07P1=2.14DVpks=0.052 VVpks=0.955 VIpk0w=1.1 AIdsmod=1

Crfin=15 fFRcin=300 kOhmCrf=1 pFtaum=0.39 psecGcont=1Lfing=0.12 um

Csbulk=15 fFCdbulk=5 fFCgbulk=5 fFTamb=25TcLsb0=0.001TcCgd0=0.001TcCgs0=0.001TcP1= 0.001

Rdw=0.1 OhmRsw=0.05 OhmRiw=0.1 OhmRgw=0.5 OhmPg=2Ijw=0.5e-8 AVjg=0.90 VP111=0.0001

P10=0.02Cgdpew=50 fFCgd0w=500 fFCgdpiw=50 fFCgs0w=500 fFCgspiw=50 fFCdsw=100 fFVsb2=0 V

lambda=0.051Vk=0.758alphaV=2.68alphas=2.68alphar=0.40P5=0P3=0.40P2=+0.07

ADS Implmentation


GaAs and CMOS FET

Rdbulkw=1.2 kOhmRgbulkw=2.3 kOhm

Lgw=16 pHRgdw=0.1 Ohm

P20=0P11=1.45

Lvg=0.0015lambda2=0.0003

I Angelov

Circuit <>FET model<>Physical models<>Device DesignExample: 1mm FET: Pout & Harmonics

51

I.Angelovp

Examples :Application oriented P1=Gm/Ipk:a) High Gm/Ipk;P1>4 high gain, but non- linearb) Low P1<1 Low gain but Linear 20

30

1])

P1

2])

3])

P1indep(P1)=plot vs(dBm(Vload[:: 1]) Vgs)=28 874

-0.600

Triquint HEMT;P1=29dBm P2=10dBm;P3=10 dBmVds=9V,Rffreq=1GHz;Pin=12 dBm

a) High Gain HEMT P1=5Vpk=0.21; Ipk0=0.3A; Ichan=0.6A;

b) Low P1<1 Low gain, but Linear

0

10

10

dB

m(V

loa

d[:

:,d

Bm

(Vlo

ad

[::,

dB

m(V

loa

d[:

:, plot_vs(dBm(Vload[::,1]), Vgs)=28.874

for Ids=10mA, gm=50ms!!Very good for Small Signal, Low Noise & High Gain!P1out= 29 dBm; but strong harmonics-

V G d f M lti li !

-2.2

-2.0

-1.8

-1.6

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-2.4

-0.2

-10

VgsWIN HEMT;P1rf=30dBm P2rf=-10dBm;P3rf=0 dBmVds=3V,Rffreq=1GHz;Pin=5 dBm

P2h=10 dBm , Very Good for Multipliers!

b) Typical HEMT: P1=2 50

20

40

m(V

load

[::,

1])

P1

m(V

load

[::,

2])

(Vlo

ad[:

:,3]

)

P1indep(P1)=plot vs(dBm(Vload[:: 1]) Vgs)=20 381

-1.000b) Typical HEMT: P1 2.5- Vpk=-0.5V; Ipk0=0.24A; Ichan=0.48A;P1out= 30 dBm; P2h= -10 dBm> Medium Power &Linear

-2.2

-2.0

-1.8

-1.6

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-2.4

-0.2

-20

-40

Vgs

dBm

dBm

dB

plot_vs(dBm(Vload[::,1]), Vgs) 20.381


GaAs and CMOS FET

Vgs

empirical nonlinear iv and capacitanceempirical...

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