Embedded Architecture Description Language

Qiang LiuSchool of Software, Tshinghua University

Joint work withJuncao Li, Nick Pilkington, and Fei Xie

Dept. of Computer Science, Portland State Univ.

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Agenda

• Problems• Unified Component Model• EADL• EADL in Embedded System Dev.• Conclusions and Future Work

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Problems

• Lack of architectural specification support for co-design – Hardware (or software) only – HW and SW in the same language

• Little consideration of verification and verification reuse– Not considered when defining

embedded system architectures– Very limited verification reuse

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Our Contributions

• Embedded Architecture Description Language– Component-based architectures of both hardware

and software– Flexible platform-oriented semantics instantiation– Design reuse and verification reuse

• Apply EADL to – Co-design– Co-verificaition– Co-simulation

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Agenda

• Problems• Unified Component Model• EADL• EADL in Embedded System Dev.• Conclusions and Future Work

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• Unifying hardware and software component models

• Component = (Design, Interface, Properties)• HW, SW, and bridge components

– Different design and interface specification languages – Same property specification language

• Verified properties are associated with components

Unified Component Model

SoftwareComponent

SoftwareComponent

SoftwareComponent

BridgeComponent

BridgeComponent

HardwareComponent

HardwareComponent

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Bridge Components: Filling Semantics Gap

• Dual interfaces: hardware and software• Bridge design

– Abstracts processor, bus model, and embedded OS– Maps between HW and SW events– Is fully synthesizable– Supports both co-simulation and co-verification

SoftwareComponent

BridgeComponent

HardwareComponent

Interactions follow software semantics

Interactions follow hardware semantics

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Transactional Bridge Spec Language

• Event mappings implemented by transactorsinterrupt ADC.INTR -> InterruptHPLADCC.IntrHPLADCC() 1;

void outpadc (unsigned int val, unsigned int address) {ADC.PSEL=1;ADC.PADDR=address;ADC.PWDATA=val;ADC.PWRITE=1;@ (posedge

ADC.PCLK);ADC.PENABLE=1;@ (posedge

ADC.PCLK);ADC.PSEL=0;ADC.PENABLE=0;

}

unsigned int inpadc (unsigned int address){

ADC.PSEL=1;ADC.PADDR=address;ADC.PWRITE=0;@ (posedge ADC.PCLK);ADC.PENABLE=1;@ (posedge ADC.PCLK);ADC.PSEL=0;ADC.PENABLE=0;

return ADC.PRDATA;}

• Transactor spec inherits from HW and SW languages

C

Verilog

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Environment of C(Components interacting with

C )

Component Property

• A property of a component C is a pair (p, A(p))– p is a temporal assertion– A(p) is a set of assumptions on environment of

C– p is verified assuming A(p) holds.

Cp

A(p) p holds on C

A(p)

Assumptions = Assumed Properties

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Agenda

• Problems• Unified Component Model• EADL• EADL in Embedded System Dev.• Conclusions and Future Work

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• Component-based semantics overlay– Complete architectural semantics– Incomplete execution and interface semantics

• Platform-oriented instantiation – Platform provides HW, SW, and BSL semantics– EADL supplies architectural semantics

SW Semantics(NesC)

Bridge Semantics(BSL)

HW Semantics(Verilog)

Embedded Architecture Description Language

Embedded Architecture Description Lang.

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Key EADL Language Features

Entities Templates

Port• Service-oriented grouping of

events• Service provides-uses

relationship

Port Type• Event co-relation similarity

Component• Unit of reuse• Component interface based on

ports

Component Template• Component external similarity

Architecture• Sub-components• Sub-component inter-

connections

Architectural Pattern• Component internal similarity

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VisualEADL: Tool Support for EADL

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An Architectural Pattern Example

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Entities – Properties Templates – Property Templates

Port• Service-oriented grouping of

events• Service provides-uses

relationship• Port-level properties

Port Type• Event co-relation similarity• Port-level property templates

Component• Units of reuse• Component interface based on

ports• Component-level properties

Component Template• Component external similarity• Component-level property

templates

Architecture• Sub-components• Sub-component inter-

connections • Architecture-level properties

Architectural Pattern• Component internal similarity• Architecture-level property

templates

Architecture-Aware Property Specification

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Property Specification Tool Support

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Agenda

• Problems• Unified Component Model• EADL• EADL in Embedded System Dev.• Conclusions and Future Work

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Component-Based Co-Design

Platform initialization(1) Analyze application domain(2) Define bridge spec. language(3) Identify architectural patterns (4) Identify reusable components(5) Verify components bottom-up

Platform-oriented pattern-guided component-based co-design(1) Select architectural patterns(2) Partition system into comps.(3) Reuse components(4) Develop new components (5) Verify system top-down

Platform extension(1) Identify new architectural

patterns (2) Identify new reusable comps.(3) Create and verify larger

reusable comps. bottom-up(4) Extend pattern and comp. libs

A platform for embedded systems:• Processors and buses • Embedded OS• HW, SW, and bridge spec. languages• Library of reusable components• Libraries of ports, component templates and architectural patterns

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Embedded System IDE (ESIDE)

Component-BasedCo-Design

(VisualEADL)

Component-BasedCo-Verification

Component-BasedCo-Simulation

PlatformLibraries

Port Lib.Template Lib.Pattern Lib.

Component Lib.

EADL Spec and

Source Code

Component-BasedSystem Synthesis

Deployment Images

Data Feedback

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HDL Source Code NesC Source Code

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Component-Based Co-Simulation

SW Application Components

Bridge Components(BSL)

BSL Compiler

SW Executable

C Compiler

C Code

NesC Compiler

SW Platform Components

HW Application Components

HW Platform Components

GianoHW Executable

HDL Compiler

ModelSimPLI

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Tool Support for Transactional BSL

SW Components(NesC)

Bridge Components(BSL)

HW Components(Verilog)

Configuration

BSL Compiler

SW Executable

C Compiler

C Code

NesC Compiler

HW Executable

Verilog Compiler

Verilog Code

Pre-Processor

• For verification – Direct compilation to formal languages• For simulation and deployment – Indirect compilation

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• Property formulation problems– What are the system properties to verify– What are the component properties

needed– What are the environment assumptions

• Architecture-based property formulation and Reuse– Port– Component template– Architectural pattern

Component-Based Co-Verification

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3-Tier Architectural Reuse in Co-Design

Component

Port

Properties from Port

Port

PortVisibleVariables

Component Template

Properties fromComponent template

Properties fromArchitectural pattern;Decomposition strategies

Sub-Component

Sub-Component

Sub-Component

Architectural Pattern

Problem addressed: property formulation and decomposition

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Co-Verification Tool Support

Component-BasedCo-Verification Frontend

Primitive Component Verification

Composite Component Verification

PlatformLibraries

Port Lib.Template Lib.Pattern Lib.

Component Lib.

EADL Spec and

Source Code

Verification QueryVerification Query;

User Guidance

Hardware Engine

Software Engine

BSL Engine

Component-Based

Abstraction

MechanizedRefinementAssistant

VerificationEngine

Verification Query

Verification Result Verification Result; User Hint

Verification Result

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Agenda

• Problems• Unified Component Model• EADL• EADL in Embedded System Dev.• Conclusions and Future Work

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Conclusions and Future Work

• Developed EADL– Component-based architectures of both hardware

and software– Flexible platform-oriented semantics instantiation– Design reuse and verification reuse

• Demonstrated effectiveness in support to – Co-design, co-simulation and co-verification

• Future work – Other component properties rather than temporal

correctness

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Further Information

• Website: – http://www.cs.pdx.edu/~xie/co-ver/co-ver-home.

htm

• Email: – juncao@cs.pdx.edu

Questions?