ELEN0040 - Electronique numerique

Patricia ROUSSEAUX

Annee academique 2014-2015

CHAPITRE 6

Registers and Counters

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Design of a modulo-8 binary counter using JK Flip-flopsI 3 bits are required = 3 flip-flopsI State table

Present State Next State Flip-flop inputsQ2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0 X 0 X 1 X0 0 1 0 1 0 0 X 1 X X 10 1 0 0 1 1 0 X X 0 1 X0 1 1 1 0 0 1 X X 1 X 11 0 0 1 0 1 X 0 0 X 1 X1 0 1 1 1 0 X 0 1 X X 11 1 0 1 1 1 X 0 X 0 1 X1 1 1 0 0 0 X 1 X 1 X 1

I Flip-flop inputs are derived from the excitation tableQ(t) Q(t + 1) J K

0 0 0 X0 1 1 X1 0 X 11 1 X 0

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Flip-flop input equations

J2 = Q1Q0

J1 = Q0

J0 = 1

Ki = Ji , i = 0, 1, 2

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Initialization

I The counter has to be initialized

I This has to be done synchronously

I A general counter can be used, using the Load mode

I For incomplete state sequence (e.g. BCD counter), the system hasto be initialized at a valid state

I Never use the asynchronous flip-flop inputs to initialize the counterin normal operation

I This should be done only at power-up or reset conditions

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A very bad practice

I We want to build a modulo-7 counter

I We use a general 4-bit counter :

I detect state “7” : 0111

I and after detection use the clearinput of the counter to go back tostate 0000

I But, the clear input acts directlyon the asynchronous reset inputsof the flip-flops

I state “7” is transitory

I and the transition to 0000 will nothappen at a clock edge

I Existence of state 7 may not be long enough to reliably reset allflip-flops to 0. Referred to as a “suicide” counter !

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A better solution

I Detect state “6” : 0110 with Q2Q1

I This set load to 1

I The 0000 present on the inputs D3 toD1 are loaded

I The counter switches synchronously tostate 0000 as required

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1 Registers1.1 Storage registers1.2 Shift registers1.3 General purpose register

2 Counters2.1 Asynchronous counter2.2 Synchronous counter2.3 Serial and parallel counters

3 Register transfers3.1 Datapath, control unit and microoperations3.2 Register transfer operations and RTL language3.3 Microoperations3.4 Register transfers design3.5 Bus-based transfers3.6 Serial operations

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Datapath, control unit and microoperationsI The information stored in a digital system can be classified as data

or control informationI The system is accordingly split into two parts :

I the datapath which performs data processing operationsI the control unit which determines the sequence of operations

I The datapath is defined by its registers and the operationsperformed on the data stored in the registers

I An elementary operation is called a microoperation : e.g. loading ofdata into one register, transferring data between two registers,adding the contents of two registers,...

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Datapath and control unit communication

I Control and status signals allow the communication between the twoparts :

I the control unit feeds the datapath with the control signals thatcharacterize the operation to be performed

I the control unit receives status signals from the datapathI the status signals inform the control unit about the state of the

datapathI this information is used by the control unit to determine the values

of the control signals

I Additional signals, control inputs and control outputs, interact withother parts of the whole system

I Data can also be interchanged through data inputs and data outputs

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Microoperations

I A microoperation is an elementary operation acting identically on allbits of the register and lasting a clock cycle at most.

I Microoperations can be classified into 4 categories :I transfer : copy the data from one register to anotherI arithmetic : perform arithmetic operation on data in registers

(+,-,1’s complement,...)I logic : manipulate data or use bitwise operation (and,or, ...)I shift : shift data in registers

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Transfer operation and Register Transfer Language (RTL)I Manipulation of registers use a particular notation denoted by

Register Transfer Language

I letters and numbers denote a register : R2, PC, ...I parentheses are used to limit a range of register bits : R1(3),

R2(1 : 4), PC(L)

I A data transfer is denoted by an arrow : R2←R1 :I the contents of R1 is copied into R2I the contents of R1 is unchangedI the transfer should be done in one clock cycle (microoperation)

I A transfer assumes that datapath circuits from outputs to inputs ofregisters are available (see bus)

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Conditional transferI A conditional transfer occurs when a given condition is satisfied

if (K1 = 1) then (R2← R1)

This is denoted by :K1 : (R2← R1)

I K1 is a control variable which acts on the load input of the registerI signal K1 has to be synchronized to the clock

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Arithmetic microoperationsRTL microoperation DescriptionR0← R1 + R2 additionR0← R1 1’s complementR0← R1 + 1 2’s complementR0← R2 + R1 + 1 subtraction (2’s compl.)R0← R1 + 1 incrementR0← R1− 1 decrement

Example :XK1 : R1← R1 + R2

XK1 : R1← R1 + R2 + 1

I in the transfer operation, R1← R1 + R2, ‘+’ means arithmeticaddition

I the variable K1 enables the operationI when K1 = 1 the result is placed in R1 and replace the previous

contentsI when K1 = 0 no operation occurs, the contents of R1 is unchangedI the variable X selects between addition and subtraction

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Logical microoperations

RTL microoperation Description

R0← R1 bitwise NOTR0← R1 ∨ R2 bitwise OR (set bits)R0← R1 ∧ R2 bitwise AND (clear bits)R0← R1⊕ R2 bitwise XOR (complement bits)

Example :(K1 + K2) : R1← R1 ∨ R3

I in the expression K1 + K2, ‘+’ means logical OR

I in the transfer operation R1← R1 ∨ R3, ‘∨’ means bitwise logicalOR

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Logical microoperations (continued)

Let R1 = 10101010

I The OR microoperation can be used to set bits to 1 in thedestination register when an appropriate mask is applied : forexample, set 4 most significant bits to 1

1010 1010 R1 (data)1111 0000 R2 (mask)1111 1010 R1← R1 ∨ R2

I The AND microoperation is used to reset bits to 0 :

1010 1010 R1 (data)0000 1111 R2 (mask)0000 1010 R1← R1 ∧ R2

I the XOR microoperation can be used to complement bits :

1010 1010 R1 (data)1111 0000 R2 (mask)0101 1010 R1← R1⊕ R2

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Shift microoperations

I Registers can be shifted to the left or to the right, letR2 = 11001001

I left shift :R1← slR2 R1 = 10010010

a zero is entered at the least significant bitI right shift :

R1← srR2 R1 = 01100100

a zero is entered at the most significant bitI sometimes, a separate flip-flop is used to provide the data shifted in

or to memorize the data shifted outI other shifts may be considered (rotate bits, ...)

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Microoperations on a single registerI Using control signals, several microoperations can be associated to a

register. Examples :1. general register with shift, parallel load and hold modes2. K1 : R0← R1, K1K2 : R0← R23. CX : A ∨ B, CY : A⊕ B

I These operations correspond to register transfersI The source register or/and the microoperation has to be selected

through a combinational circuitI As already seen for example 1, the selection can be made using a

multiplexerI An alternative approach consists in designing the n-bit register with

its combinational logic as the association of n identical register cells.A conventional approach is used for the design of the register cell

I If the same logic is used for each operation and/or source =dedicated logic

I If the combinational circuit can be shared by several sources ormicrooperations : shared logic

I The case of possible multiple destination registers will be consideredlater

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Register transfers : selection through a multiplexerI Consider example 2, where the source register has to be selected

according to control variables K1, K2

I A n-bit 2-to-1 multiplexer is usedI The selection input S is simply given by K1

I When :I K1 = 1, the value in register R1

is transferred into register R0I K1 = 0 and K2 = 1, the value in

register R2 is transferred intoregister R0

I in both cases, the Load input ofthe register is high and transferis activated

I otherwise (K1 = 0, K2 = 0) :I the Load input of the register is

lowI the previous value in register R0

remains unchanged (hold mode)

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Register transfers : Selection through a multiplexerI The procedure can be generalized to n sources : outputs of

dedicated logic blocks, registers or shared logic blocks

I the control signals are K0, · · · ,Kn−1

I only one control signal is equal to one at any timeI the control signals are encoded to provide the selection inputs of the

multiplexer

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Register transfers design

I Specifications : one has to define for example 3

I the destination register

I the data inputs to the register

I the control inputs and theiruseful combinations

I the set of register functions,i.e. the register transfers

I the hold mode : hold thecurrent register state

A

B

(CX , CY ), with combinations(0,0),(0,1),(1,0)

CX : A ∨ B , (1,0)CY : A⊕ B, (0,1)

(0,0)

I Design procedure :I using a multiplexerI using an individual cell design

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Example 3, selection through a multiplexerI The register transfers to be implemented are :

CX : A ∨ B, CY : A⊕ B

I when CX = 0, CY = 0 : hold mode

I an encoder is not required, CX , CY are directly applied to theselecting inputs of the multiplexer

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Example 3, selection through a multiplexer (continued)

I Consider the circuit cell for one bit of the register

I the decoder can be shared by all cells

I gate input cost :I decoder : 8I non-shared logic : 2+8+9=19, for each bitI for the whole circuit : 8 + 19n + 2 (shared logic, non-shared logic,

one 2-OR gate)

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Example 3, individual cell designUse the procedure defined in Chapter 5 for cell i

I State tablePresent state Next state

Ai (t) Ai (t + 1) for CX CY Bi (t) =000 001 010 011 100 101

0 0 0 0 1 0 11 1 1 1 0 1 1

I flip-flop input equation :

Ai (t + 1) = CX Bi + Ai (CY Bi ) + AiCY + Ai Bi

= CX Bi + Ai (CY Bi ) + Ai (CY + Bi )

= CX Bi + Ai (CY .Bi ) + AiCY .Bi

= CX Bi + Ai ⊕ CY Bi

I gate input cost :I for one cell : 2 (CX .Bi ) + 2 (CY .Bi ) + 8(XOR) + 2(OR) = 14I for the whole circuit = 14n !

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Register transfers with multiple destination registers

I Digital systems have many registers

I Paths must be provided to transfer data from one register to theother

I A particular destination register has to be selected for eachmicrooperation

I A possible solution is to use a multiplexer dedicated to eachdestination register

I Better solution : use a bus, i.e. a communication path shared by allregister, and a single multiplexer to select the source

I Buses can be implemented using :I multiplexersI three state buffers

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Dedicated MUX-Based transfers

A very flexible transfer structure

I selection signals Si select the sourceregister(s)

I control signals Li select the destinationregister(s)

Possible transfers

Select LoadRegister transfer S2 S1 S0 L2 L1 L0

R0← R2 1 0 0 0 0 1R0← R1, R2← R1 0 1 0 1 0 1R0← R1, R1← R0 0 1 1 0 1 1...

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Multiplexer Bus

I The multiplexer selects the sourceregister

I The control signals Li select thedestination register(s)

I Possible transfers

Select LoadRegister transfer S1 S0 L2 L1 L0

R0← R2 1 0 0 0 1R0← R1, R2← R1 0 1 1 0 1R0← R1, R1← R0 impossible...

I A single bus driven by a multiplexer lowers the cost (lesscommunication links, a single multiplexer) but limits the availabletransfers

I Simultaneous transfers with different sources in a single clock cycleare impossible

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Buffer and Three-state bufferI A buffer :

I simply copies the input variable : F = XI is used to improve circuit voltage levels and increase the speed

I A three-state bufferI presents a high-impedance output, giving three states : 0, 1 and

High-ZI the High-Z value behaves as an open circuitI X is the data input and E is a control input

I Outputs of several 3-state buffers can be connected togetherprovided that all outputs but one are in High-Z state

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Selection circuit using 3-state logic

I Performing data selection with 3-state buffers

I 2 buffer outputs are connected together

I Data Selection Function : if S = 0, OL = IN0, else OL = IN1

I Since EN0 = S and EN1 = S , one of the two buffer outputs isalways High-Z

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Three-state bus

I The multiplexer is replaced by 3-statebuffers

I A three-state buffer is connected at theoutput of each flip-flop composing theregister

I The enable signal EN is identical for allbits

I The inputs of the flip-flops areconnected to the bus, most generallythrough a buffer (not represented inthe figure)

I This provides a bi-directional bus

I The transfer capabilities are identicalto those of the multiplexer-bus

3-state register withbidirectional lines

3-state bus

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Serial transfersI A system operates in serial mode if the information is transferred or

manipulated (microoperation) one bit at a timeI The bits are shifted out of one register and into a second registerI This is done with shift registers, the serial output of the first register

is connected to the serial input of the second registerI Example : the transfer of one binary word of 4 bits takes 4 clock

cyclesI The operation is controlled by the clock-gated Shift variable

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Serial microoperation example : 4bit-additionI Two shift registers with parallel load capability are used for operands

of the operation : A, BI The two operands are loaded in parallel in the registersI The operands are shifted at each clock cycleI A full adder is used to compute the sumI One additional flip-flop is used to store the carryI Register A is also used to store the final result which is entered

seriallyI The final carry is stored in the flip-flop

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References

I Logic and Computer Design Fundamentals, 4/E, M. Morris ManoCharles Kime , Course materialhttp ://writphotec.com/mano4/

I Cours d’electronique numerique, Aurelie Gensbittel, BertrandGranado, Universite Pierre et Marie Curiehttp ://bertrand.granado.free.fr/Licence/ue201/coursbeameranime.pdf

I Lecture notes, Course CSE370 - Introduction to Digital Design,Spring 2006, University of Washington,https ://courses.cs.washington.edu/courses/cse370/06sp/pdfs/

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