elen 468 lecture 61 elen 468 advanced logic design lecture 6 delay models
TRANSCRIPT
ELEN 468 Lecture 6 1
ELEN 468Advanced Logic Design
Lecture 6Delay Models
ELEN 468 Lecture 6 2
Delay Models
ELEN 468 Lecture 6 3
Propagation Delay
Xin Xout
Tpd_1_0
Xin
Xout
t
t
50%Vdd
50%Vdd
ELEN 468 Lecture 6 4
Delay Models
Gate delay Intrinsic delay Layout-induced delay due to capacitive load Waveform slope-induced delay
Net delay/transport delay Signal propagation delay along interconnect
wires
Module path delay Delay between input port and output port
ELEN 468 Lecture 6 5
Signal Transitions
Rising 0->1, x->1, z->1
Falling 1->0, x->0, z->0
Turnoff 0->z, 1->z, x->z
ELEN 468 Lecture 6 6
Model Delay Uncertainties:Min, Typical and Max Delays
Process variations Defects, etching errors, photomask
misalignment …
Power-ground noise Power supply level lower than ideal
level Ground voltage level greater than zero
Crosstalk noise Signal switching in neighboring wires
causes extra net delay
ELEN 468 Lecture 6 7
Gate Delay
and (yout, x1, x2); // default, zero gate delayand #3 (yout, x1, x2); // 3 units delay for all transitionsand #(2,3) G1(yout, x1, x2); // rising, falling delayand #(2,3) G1(yout, x1, x2), G2(yout2, x3, x4);
// Multiple instancesa_buffer #(3,5,2) (yout, x); // UDP, rise, fall, turnoffbufif1 #(3:4:5, 6:7:9, 5:7:8) (yout, xin, enable);
// min:typ:max / rise, fall, turnoff
and (yout, x1, x2); // default, zero gate delayand #3 (yout, x1, x2); // 3 units delay for all transitionsand #(2,3) G1(yout, x1, x2); // rising, falling delayand #(2,3) G1(yout, x1, x2), G2(yout2, x3, x4);
// Multiple instancesa_buffer #(3,5,2) (yout, x); // UDP, rise, fall, turnoffbufif1 #(3:4:5, 6:7:9, 5:7:8) (yout, xin, enable);
// min:typ:max / rise, fall, turnoff
•Simulators simulate with only one of min, typ and max delay values
•Selection is made through compiler directives or user interfaces
•Default delay is typ delay
ELEN 468 Lecture 6 8
Options for Delay Specifications
dr = rising delay, df = falling delay, dz = turnoff delayIf 2 delays are specified
d* = d** = min ( dr, df )If 3 delays are specified
d* = min( dr, df, dz ), d** = dz
Logic value before transition
Logic value after transition
0 1 x z
0 dr d* dz
1 df d* dz
x df dr d**
z df dr d*
ELEN 468 Lecture 6 9
Time ScalesTime scale directive: ‘ timescale <time_unit>/<time_precision> time_unit -> physical unit of measure, time scale of delay time_precision -> time resolution/minimum step size during simulation time_unit time_precision
Unit/precision Delay specification
Simulator time step
Delay value in simulation
1ns / 100ps #4 0.1ns 4.0ns
100ns / ns #4 1ns 400ns
10ns / 100ps #4.629 0.1ns 46.3ns
ELEN 468 Lecture 6 10
Example of Time Scale`timescale 1 ns / 10 psmodule modA( y, x1, x2 ); input x1, x2; output y; nand #(3.225, 4.237) ( y, x1, x2 );endmodule`timescale 10 ns / 10 nsmodule modB(); reg x1, x2; wire y; modA M1(y, x1, x2); initial begin $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1,
x2, y ); end initial begin
#5 x1 = 0; x2 = 0;#5 x2 = 1;#5 x1 = 1;#5 x2 = 0;
endendmodule
ELEN 468 Lecture 6 11
Example of Time Scale`timescale 1 ns / 10 psmodule modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1, x2
);endmodule`timescale 10 ns / 10 nsmodule modB(); … … modA M1(y, x1, x2); initial begin $monitor ( $time, “%f x1= %b x2= %b y=
%b”, $realtime, x1, x2, y ); end initial begin
#5 x1 = 0; x2 = 0;#5 x2 = 1;#5 x1 = 1;#5 x2 = 0;
endendmodule
`timescale 1 ns / 10 psmodule modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1, x2
);endmodule`timescale 10 ns / 10 nsmodule modB(); … … modA M1(y, x1, x2); initial begin $monitor ( $time, “%f x1= %b x2= %b y=
%b”, $realtime, x1, x2, y ); end initial begin
#5 x1 = 0; x2 = 0;#5 x2 = 1;#5 x1 = 1;#5 x2 = 0;
endendmodule
$t $real_t x1 x2 y
-------------------------------------------------
0 0.000000 x1=x x2=x y=x
5 5.000000 x1=0 x2=0 y=x
5 5.323000 x1=0 x2=0 y=1
10 10.000000 x1=0 x2=1 y=1
15 15.000000 x1=1 x2=1 y=1
15 15.424000 x1=1 x2=1 y=0
20 20.000000 x1=1 x2=0 y=0
20 20.323000 x1=1 x2=0 y=1
ELEN 468 Lecture 6 12
Time Display Format`timescale 1 ns / 1 psmodule modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1,
x2 );endmodule`timescale 10 ns / 10 nsmodule modB(); … … modA M1(y, x1, x2); initial begin $timeformat (-12, 1, “ ps”,
10); $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1, x2, y ); end initial begin
#5 x1 = 0; x2 = 0;#5 x2 = 1;#5 x1 = 1;#5 x2 = 0;
endendmodule
`timescale 1 ns / 1 psmodule modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1,
x2 );endmodule`timescale 10 ns / 10 nsmodule modB(); … … modA M1(y, x1, x2); initial begin $timeformat (-12, 1, “ ps”,
10); $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1, x2, y ); end initial begin
#5 x1 = 0; x2 = 0;#5 x2 = 1;#5 x1 = 1;#5 x2 = 0;
endendmodule
$t $real_t x1 x2 y-------------------------------------------------50000. 0ps 0.000000 x1=x x2=x
y=x50000. 0ps 5.000000 x1=0 x2=0
y=x53225. 0ps 5.322500 x1=0 x2=0
y=1100000. 0ps 10.000000 x1=0 x2=1
y=1150000. 0ps 15.000000 x1=1 x2=1
y=1154237. 0ps 15.423700 x1=1 x2=1
y=0200000. 0ps 20.000000 x1=1 x2=0
y=0203225. 0ps 20.322500 x1=1 x2=0
y=1
$timeformat ( units_number, precision_number, suffix_string, min_field_width );
ELEN 468 Lecture 6 13
Unit Number in Time Format
Unit_number
Time unit Unit_number
Time unit
0 1s -8 10ns
-1 100ms -9 1ns
-2 10ms -10 100ps
-3 1ms -11 10ps
-4 100us -12 1ps
-5 10us -13 100fs
-6 1us -14 10fs
-7 100ns -15 1fs
ELEN 468 Lecture 6 14
Net Delay… …wire #2 y_tran;and #3 (y_tran, x1, x2);buf #1 (buf_out, y_tran);and #3 (y_inertial, x1,
x2);… …
… …wire #2 y_tran;and #3 (y_tran, x1, x2);buf #1 (buf_out, y_tran);and #3 (y_inertial, x1,
x2);… …
x1
x2y_tran
y_inertial
buf_out
2 4 6 8 10
2 4 6 8 10
2 4 6 8 10
2 4 6 8 10
2 4 6 8 10
x1
x2
y_inertial
y_tran
buf_out
ELEN 468 Lecture 6 15
Examples of Net Delaymodule xor1( y, a, b );
input a, b;output y;parameter delay = 5;
assign #delay y = a ^ b;endmodule
module xor1( y, a, b );input a, b;output y;parameter delay = 5;
assign #delay y = a ^ b;endmodule
module xor2( y, a, b );input a, b;output y;wire #5 y;
assign y = a ^ b;endmodule
module xor2( y, a, b );input a, b;output y;wire #5 y;
assign y = a ^ b;endmodule
module xor3( y, a, b );input a, b;output y;parameter wire_delay = 5;parameter gate_delay =3;wire #wire_delay y;
assign #gate_delay y = a ^ b;
endmodule
module xor3( y, a, b );input a, b;output y;parameter wire_delay = 5;parameter gate_delay =3;wire #wire_delay y;
assign #gate_delay y = a ^ b;
endmodule
ELEN 468 Lecture 6 16
Module Delays and Paths
In structural description, module delays can be obtained by tracing gate and net delays In behavioral description, module paths can be described separately to allow delay descriptions
ELEN 468 Lecture 6 17
Module Paths
Simple module paths Unconditional direct input to output path
State-dependent paths Exists when certain condition is satisfied Describe transparent latch
Edge-dependent paths Exists for a synchronizing signal Describe edge-triggered flip-flop
ELEN 468 Lecture 6 18
Simple Module Path
Source of path must be a net declared as input or outputDestination of path must be a net or reg declared as output or inout
Parallel paths, “=>”
Full connection paths, “*>”
ELEN 468 Lecture 6 19
Example of Simple Module Path Delay
module nand1( out, A, B );output out;input A, B;nand ( out, A, B );
specify ( A,B *> out ) = ( 15, 14, 11, 10, 16,15 );// 0->1, 1->0, 0->z, z->1, 1->z, z->0endspecify
endmodule
module nand1( out, A, B );output out;input A, B;nand ( out, A, B );
specify ( A,B *> out ) = ( 15, 14, 11, 10, 16,15 );// 0->1, 1->0, 0->z, z->1, 1->z, z->0endspecify
endmodule
A
B
out
•Specify blocks declare paths
•Its path can override structural delays
ELEN 468 Lecture 6 20
Edge-Sensitive Pathsmodule edge_FF ( clock, data, clear, preset, q );
input clock, data, clear, preset;output q;specify specparam
t_rise_clk_q = 100;t_fall_clk_q = 120;t_rise_ctl_q = 50;t_fall_ctl_q = 60;
( posedge clock *> (q:data) ) = ( t_rise_clk_q, t_fall_clk_q ); ( clear, preset *> q ) = ( t_rise_ctl_q, t_fall_ctl_q );endspecify… …
endmodule
module edge_FF ( clock, data, clear, preset, q );input clock, data, clear, preset;output q;specify specparam
t_rise_clk_q = 100;t_fall_clk_q = 120;t_rise_ctl_q = 50;t_fall_ctl_q = 60;
( posedge clock *> (q:data) ) = ( t_rise_clk_q, t_fall_clk_q ); ( clear, preset *> q ) = ( t_rise_ctl_q, t_fall_ctl_q );endspecify… …
endmodule
ELEN 468 Lecture 6 21
State-Dependent Paths
specifyif ( enable ) ( data *> q ) = ( t_rise_clk_q, t_fall_clk_q );
endspecify
specify
if ( !set && !clear ) ( posedge clock *> ( q:data )) =( t_rise_clk_q, t_fall_clk_q );
endspecify
specifyif ( enable ) ( data *> q ) = ( t_rise_clk_q, t_fall_clk_q );
endspecify
specifyif ( !set && !clear ) ( posedge clock *> ( q:data )) =
( t_rise_clk_q, t_fall_clk_q );endspecify
ELEN 468 Lecture 6 22
Path Polarity
( siga +*> q1 ) = delay_to_q1; // positive path polarity( sigb -*> q2 ) = delay_to_q2; // negative path polarity( sigc *> q3 ) = delay_to_q3; // unknown polarity
( siga +*> q1 ) = delay_to_q1; // positive path polarity( sigb -*> q2 ) = delay_to_q2; // negative path polarity( sigc *> q3 ) = delay_to_q3; // unknown polarity
Specify whether a transition at output of a path has the same direction (rising or falling) as the input
ELEN 468 Lecture 6 23
Specify Block Parametersmodule nand1 ( O, A, B );
input A, B;output O;nand ( O, A, B );specify specparam
T01 = 1.13:3.09:7.75;T10 = 0.93:2.50:7.34;( A=>O ) = ( T01,
T10 );( B=>O ) = ( T01,
T10 );endspecify
endmodule
module nand1 ( O, A, B );input A, B;output O;nand ( O, A, B );specify specparam
T01 = 1.13:3.09:7.75;T10 = 0.93:2.50:7.34;( A=>O ) = ( T01,
T10 );( B=>O ) = ( T01,
T10 );endspecify
endmodule
Local to specify block
ELEN 468 Lecture 6 24
Specify Pulse Widthmodule nand1 ( O, A, B );
input A, B;output O;nand ( O, A, B );specify specparam
T01 = 1.13:3.09:7.75;T10 = 0.93:2.50:7.34;( A=>O ) = ( T01, T10 );( B=>O ) = ( T01, T10 );pathpulse$ (0.0011 : 0.0024 :
0.0057 );endspecify
endmodule
module nand1 ( O, A, B );input A, B;output O;nand ( O, A, B );specify specparam
T01 = 1.13:3.09:7.75;T10 = 0.93:2.50:7.34;( A=>O ) = ( T01, T10 );( B=>O ) = ( T01, T10 );pathpulse$ (0.0011 : 0.0024 :
0.0057 );endspecify
endmodule
Specify inertial delays
ELEN 468 Lecture 6 25
Pulse Reject Limit and Error Limit
specify( clk => q ) = 10;( data => q ) = 7;( clr, preset *> q ) = 3;specparam pathpulse$ clk$q = ( 3, 8 ); pathpulse$ clr$q = ( 0, 5 ); pathpulse$ = 4;
endspecify
specify( clk => q ) = 10;( data => q ) = 7;( clr, preset *> q ) = 3;specparam pathpulse$ clk$q = ( 3, 8 ); pathpulse$ clr$q = ( 0, 5 ); pathpulse$ = 4;
endspecify
Reject limit
Error limit
• If pulse_width < reject_limit, pulse is rejected
• If reject_limit < pulse_width < error_limit, ‘x’ is at output
• If error_limit < pulse_width, signal is transported to output
Single value for both reject and errorFor any other paths not specified