elektrotechnik und informationstechnik, stiftungsprofessur ...folie nr. 3 reminder: project work...

Elektrotechnik und Informationstechnik, Stiftungsprofessur hochparallele VLSI Systeme und Neuromikroelektronik

Oberseminar Informationstechnik

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Reminder: Project Work

Project Work

▪ ONE system ACCOUNT for ALL lab courses(e.g. Schaltkreis- und Systementwurf, Prozessorentwurf, this seminar)

▪ Please REGISTER yourself for EACH LAB COURSE

Website (Home)https://tu-dresden.de/ing/elektrotechnik/iee/hpsn

Website (Information, Links, Anmeldung)https://

tu-dresden.de/ing/elektrotechnik/iee/hpsn/studium/materialien

Login via IDM (ZIH-Login) required. Typical Login ID: e.g. s1234567

Register for `OSM´

Room: TOE 201

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Reminder: Project Work

Single-Person projects. One student – one project work.

Topics

▪ Choice of topics presented in the lecture

▪ You can also make your own project proposal

Structure

▪ Self-study your topic

▪ Give a presentation to the course: Elaborate the problem andpresent approaches to the solution.

▪ Develop and implement the solution in VHDL, simulate it.

▪ Hand in a report.

Presentation and Report are evaluated to yield your credits.

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Project Work – Typical Structure of VHDL Work

Digital Parte.g. FSMor digital filter

Behavioral ModelAnalog, Mixed-Signalor Physical

Test BenchSimulation Control

Stimulus

Digital Controle.g. clock, reset, enable

data to be processed

Control Parameterse.g. temperature, voltage,simulated real-word input

Digital Interface:Control lines operating real stuff represented by the model.Feedback lines providing digital information on the model state

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Project Work – Typical Structure of VHDL Work




Stimulus

abstract simplified modelexplicitly calculates states ofanalog and physical quantities

synchronuous digital logiccombinational + sequentialsynthesizable RTL description

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Project Work Topics

Project Work Digital Controller Mixed Signal Behavioural Model

Analog PLL PFD, Divider, Binary Search Loop Filter, Oscillator

Digital PLL PID controller Oscillator with temperature and voltage dependencies

Digital DLL PID controller Digitally adjustable Delay Line, extenal Delay

SAR ADC SAR register / FSM SC charge redistribution network

SD-ADC Decimation filter implementation SD-modulator

Class D PA Digital FIR design + implementation analog RLC network

Step-Down DCDC voltage mode regulation PID controller + digital PWM analog RLC network, simple ADC

Step-Down DCDC current mode regulation PID controller + digital PWM analog RLC network, simple ADC

Step-Down DCDC discontinuous mode pwm control PID controller + digital PWM analog RLC network, simple ADC

DCDC Current Mode / controlled LED supply digital controller, PWM, interface analog RLC network, simple ADC

Polychronuous Spinking Neural Network AER busses and arbiters Neurons, Synapses, Axons

Leaky IAF neurons configuration registers, spike decoders Neurons, Synapses

Time Division Multiplexed Perceptron Multiplexers, Counters, FSM Current mode MDAC, simple non-linear neuron core

Brushless DC Motor Sequencer, controller Electro-mechanical motor model

Your Own Idea ? ?

ADC/DAC

PLL

Power

Neuro

Other

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Parallel Statements

Hierachical Design

top_level

subsystem another subsystem

building block A

subblock

block B block C block C

block D block E block F

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Parallel Statements

RTL Example

-- signal declarations go here

S <= A B Ci;

(A, B)

AB <= A B;

;

OR3_i : OR3

(I1 => AB, I2 => AC, I3 => BC, O => Co);

RTL;

Hierarchy corresponds to the Instatiation

Parallel Statement Inside the Architecture:

instantiation

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VHDL Hierarchy

STRUCTURE FOO

FULL_ADDER

( A : std_logic;

B : std_logic;

Ci: std_logic;

S : std_logic;

Co: std_logic);

FULL_ADDER;

ADD_BIT1_i : FULL_ADDER

(A => OP_A(1),

B => OP_B(1),

Ci => CARRY(0),

S => RES(1),

Co => CARRY(1)

);

STRUCTURE;

FULL_ADDER

( A : std_logic;

B : std_logic;

Ci: std_logic;

S : std_logic;

Co: std_logic);

FULL_ADDER;

subblock

instance of subblock

port of is connected tobit 1 of signal in block

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configuration – optionally select particular architectures

VHDL Hierarchy: Configurations

STRUCTURE_CFG FOO

STRUCTURE


work.FULL_ADDER(NET);

STRUCTURE_CFG;

configuration name entity

select architecture for FOO

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STRUCTURE_CFG FOO

STRUCTURE


work.FULL_ADDER(NET);

STRUCTURE_CFG;

in architecure of entity

… instance …

… is an instance ofentityarchitecture

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• for an entity: select the architecture

• for an instance:

o use particular architecture

o use specific configuration

o can replace the component with different entity

o can map ports, even interchange ports

• configuration specification also within architecture

• no config -> default binding, last architecture


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➢ Very wide range of means to select between choices in the hierarchy

➢ Most features not supported by synthesis tools

➢ Restrict yourself to one top-level configuration or no configurations at all


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Arithmetic

Binary Arithmetic

▪ IEEE 1164 logic is the most prominent enumeration type

std_logic single-bit digital signals

std_logic_vector multi-bit digital busses

signed, unsigned std_logic_vector in numerics

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Arithmetic

Binary Arithmetic

▪ IEEE 1164 logic is the most prominent enumeration type

std_logic single-bit digital signals

std_logic_vector multi-bit digital busses

signed, unsigned std_logic_vector in numerics

no numerical interpretation

2´s complement numerics

IEEE;

IEEE.std_logic_1164. ;

IEEE.numeric_std. ;

BAR

FOO BAR

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Binary Arithmetic

IEEE;

IEEE.std_logic_1164. ;

IEEE.numeric_std. ;

BAR

FOO BAR

std_logic_vector 0)

unsigned(15 0)

signed(15 0)

U <= unsigned(L);

S <= signed(L);

L <= U X=´1´ S;

U <= to_unsigned( 173, 16);

S <= to_signed( -212, 16);

X <= A( to_integer(U(3 downto 0)));

library and use statements

assignment to subtype with cast

direct assignment to base type

conversion functions

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Parallel Statements

RTL Example

-- signal declarations go here

S <= A B Ci;

(A, B)

AB <= A B;

;

OR3_i : OR3

(I1 => AB, I2 => AC, I3 => BC, O => Co);

RTL;

… back toParallel Statements Inside Architectures

processstatement

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Process Statement

A, B, C)

A ”010”

S1 <= B;

S1 <= C;

;

;

label: ( A)

S2 <= A(1) A(0);

label;

Process Statement

sensitivity list

inside the process:sequential statements

all processes run in parallelall processes run in parallel

a process can benamed with a label

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Sequential Statements

condition

sequential_statements;

condition



Sequential Statement: if-then-else

expression yielding a Boolean value

optional ELSIF branch.

optional ELSE branch.

required END IF;

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expression

choice equential_statements;



Sequential Statement: case

expression of arbitrary type

choice value of same type as expression

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SEL

"01" Z A

"10" Z B

Z 'X'


As of the VHDL standard,all possible choices must be included, …

… unless the others clause is used as the last choice

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SEL

"01" Z A

"10" Z B


null statement – explicitly do nothing in this branch

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INT

0 Z A

1 to 3 Z B

4|6|8 Z A


range

selection: List of values

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INT

Z B

|4|6 Z A

others Z ’X’

VEC

”000” Z A

Z B

others Z ’X’

Not allowed in case statement:

ranges and selections must not overlap

ranges are not allowed for vectors / arrays

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Z "0000";

I 0 3

A I Z(I) '1'

Sequential Statement: for loop

Loop Variable takes type of loop range

Z <= "0000"; for I in o to 3 loop if (A = I) then Z(I) <= '1'; end if; end loop;

Loop variable implicitly declared with type of loop range

Example for combinational 1-hot decoder

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Z "0000";

I 0 3

A I

Z(I) ‘1’



End the loop with exit

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Z "0000";

I 0 3

when A I

Z(I) ‘1’



Skip to next loop iteration with

and also work with labels

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std_logic_vector(N-1 0

unsigned(K

A

M to_unsigned( 0, K)

I A’LOW A’HIGH

A(I) ’1’

M to_unsigned( I, K)

for loop example: determine highest bit


Attributes as loop bounds

default assignment

last sequential assignment wins

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unsigned(K

A

M to_unsigned( 0, K)

I A’HIGH A’LOW

A(I) ’1’

M to_unsigned( I, K)

another for loop example: determine highest bit


Look for highest bit first

End the loop if bit is found.

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unsigned(K

A

unsigned(K

tmp to_unsigned( 0, K)

I A’LOW A’HIGH

A(I) ’1’

tmp tmp + 1

M <= tmp;

Variable example: count ’1’ bits


variable assignment takes effect immediately

variables – explicit intermediate values in processes

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10 ns;

A, B;

clk = '1'

clk'event clk = '1';

clk'stable clk = '1';

A B='1';

Sequential Statement: wait

wait for a fixed time

wait for a condition tobecome true

wait for either signal to change

combinations allowed

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Digital Logic = Synthesizable RTL code




Stimulus

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Synthesizable RTL Code

Digital logic is subdivided in two principal classes:

1) Combinational Logic 2) Sequential Logic

Computing Elements Storage Elements

02.11.2018

clk

QDAB

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Digital logic is subdivided in two principal classes:

1) Combinational Logic 2) Sequential Logic

Computing Elements Storage Elements

Nothing else. Nothing in between.

Of course, elements from both classes can be assembled togetherto form entities with storage and computing capabilities.

02.11.2018

clk

QDAB

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1) Combinational Logic

• some inputs, some ouputs

• each change of logic level at any input immediatly followedby change at some output

• in the physical world delayed by path delay

02.11.2018

DABC E

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1) RTL for Combinational Logic

02.11.2018

DABC E

std_logic

´1´

E <= B;

E <= C;

;

;

std_logic

´1´

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02.11.2018

DABC E

std_logic

´1´

E <= B;

E <= C;

;

;

std_logic

´1´

ALL right-hand side signalsMUST be in the sensitivity list

Any signal, that gets a value assigned, is said to be an output of the process.A combinational process MUST ASSIGN values to ALL its OUTPUT SIGNALS under any condition.

ALL right-hand side signalsMUST be in the sensitivity listALL right-hand side signalsMUST be in the sensitivity listALL right-hand side signalsMUST be in the sensitivity listALL right-hand side signalsMUST be in the sensitivity list

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02.11.2018

DABC E

std_logic

´1´

E <= B;

E <= C;

;

;

std_logic

´1´

concurrent assignments

alternatively:

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02.11.2018

DABC E

no delay in RTL

std_logic

´1´

E <= B;

E <= C;

;

;

std_logic

´1´

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Operators for Digital Logic / RTL code

• bit-wise logic and Boolean logic, result type = argument typeand, or, nand, nor, xor, xnor, not

• comparisons, result type: Boolean= /= < > <= / >=

equal not equal less than greater than less/greater or equal

• numeric, result type: numeric+, - addition, subtraction, unary sign

*, / multiplication, divisionmod,rem modulo division, sign of right (mod) or left (rem) operand** exponentiationabs absolute value

O.K.

need 3rd party IP

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2) Sequential Logic

• clock signal and significant clock edge(e.g. rising_edge(clk))

• input data is capturedat the time of the clock edgeand presented at the outputuntil different data will have beencaptured at a subsequent clock edge

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clk

QD

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Process Statement

clk, reset_n)

reset_n ’0’

Q <= ’0’;

clk

Q <= D;

;

;

Process Statement for Sequential Logic

Exacty one top-level if-then-else clause.Active reset state in thehighest-priority branch

EXACTLY clock and reset in the sensitivity list

Active clock edge in thesecond branch.

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2) RTL for Sequential Logic

04.11.2018

clk

QD

clk, reset_n)

reset_n ’0’

Q <= ’0’;

clk

Q <= D;

;

;

no delay in RTL

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Example: Incrementer

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4

INC

clk std_logic

reset_n std_logic

Q unsigned(3 0

INC

RTL INC

D : unsigned(3 0

clk, reset_n)

reset_n ’0’

Q <= (others => ’0’);

clk

Q <= D;

;

;

D <= Q + to_unsigned( 1, 4);

RTL;

clk

QD+

”0001”

4

reset_n

4

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Example: Incrementer

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4

INC

clk std_logic

reset_n std_logic

Q unsigned(3 0

INC

RTL INC

D : unsigned(3 0

clk, reset_n)

reset_n ’0’

Q <= (others => ’0’);

clk

Q <= D;

;

;

D <= Q + to_unsigned( 1, 4);

RTL;

clk

QD+

”0001”

4

reset_n

4

numeric constants

32 -- decimal, integer3.1416 -- real, decimal

16#FF# -- integer, base 16 (i.e. hexadecimal)2#0001# -- integer, base 2 (i.e. binary)

better readability:16#1A_DEAD_BEEF# -- integer, hex1_000_000.0 --

elektrotechnik und informationstechnik, stiftungsprofessur ...folie nr. 3 reminder: project work...

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