electronics ii lecture 5(a): field effect transistor fet · summary there are three regions in the...
TRANSCRIPT
Summary
© 2008 Pearson Education, Inc.All rights reserved
Electronics IILecture 5(a): Field Effect Transistor FET
A/Lectr. Khalid ShakirDept. Of Electrical Engineering
College of EngineeringMaysan University
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 1-18
p p
–VG G
+
Summary
is no
V
© 2008 Pearson Education, Inc.All rights reserved
Gp p
RD
D
n+
– DD
n
S
The FET
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 2-18
His ideas were later refined anddeveloped into the FET. Materialswere not available at the time tobuild his device. A practical FETwas not constructed until the1950’s. Today FETs are the mostwidely used components inintegrated circuits.
The idea for a field-effect transistor (FET) was first proposedby Julius Lilienthal, a physicist and inventor. In 1930 he wasgranted a U.S. patent for the device.
p p
–VG G
+
Summary
The JFET (or Junction Field Effect Transistor) is a normallyON device. For the n-channel device illustrated, when thedrain is positive with respect to the source and there is nogate-source voltage, there is current in the channel.
When a negative gate voltage isapplied to the FET, the electricfield causes the channel tonarrow, which in turn causescurrent to decrease.
V
© 2008 Pearson Education, Inc.All rights reserved
Gp p
The JFET
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 3-18
RD
D
n+
– DD
n
S
Summary
As in the base of bipolar transistors, there are two types ofJFETs: n-channel and p-channel. Theopposite polarities for each type.
dc voltages are
The symbol for an n-channel JFET isshown, along with the proper polarities ofthe applied dc voltages. For an n-channeldevice, the gate is always operated with anegative (or zero) voltage with respect tothe source.
+
© 2008 Pearson Education, Inc.All rights reserved
+
RD
Drain
Gate VDD
––
VGGSource
The JFET
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 4-18
Summary
There are three regions in the characteristic curve for a JFETas illustrated for the case when VGS = 0 V.Between A and B is the Ohmicregion, where current and voltageare related by Ohm’s law.
From B to C is the active (orconstant-current) region wherecurrent is essentially independentof VDS.
Beyond C is the breakdownregion. Operation here candamage the FET.
DSS
P (pinch-off voltage)
© 2008 Pearson Education, Inc.All rights reserved
ID
own
VDS
I
Ohmic region
B VGS = 0 C
Breakd
A
Active region(constant current)
0 V
The JFET
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 5-18
Summary
When VGS is set to different values, the relationship betweenVDS and ID develops a family of characteristic curves for thedevice.An n-channelcharacteristic isillustrated here.Notice that Vp is
positive and hasthe samemagnitude asVGS(off).
5 V
P
© 2008 Pearson Education, Inc.All rights reserved
VGS = VGS(of f) = –
ID
IDSS VGS = 0
VGS = –1 V
VGS = –2 V
VGS = –3 V
VGS = –4 V
V = +5 V VDS
The JFET
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 6-18
Summary
A plot of VGS to ID is called the transfer or transconductance
curve. The transfer curve is a is(ID) to the input voltage (VGS).The transfer curve is based on theequation
a plot of the output current
2翫1
VGSI ID DSS VGS(off) DSS
By substitution, you can find otherpoints on the curveuniversal curve.
for plotting the
-0.3 V(off)
-0.5 VGS(off)
© 2008 Pearson Education, Inc.All rights reserved
VGS 0
ID
IDSS
I2
IDSS
4
–VGS
GS(off)
The JFET
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 7-18
Summary
A certain 2N5458 JFET has
(a) Show the values of thethese end points on thetransfer curve.
(b) Show the point for thecase when ID = 3.0 mA.
IDSS = 6.0 mA and VGS(off) = – 3.5 V.
(b) When ID = ½ IDSS, VGS
= 0.3 VGS(off). Therefore,VGS(off) -1.05 V= -3.5 V
VGS = -1.05 V
© 2008 Pearson Education, Inc.All rights reserved
0
ID
IDSS = 6.0 mA
3.0 mA
–VGS
The JFET
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 8-18
Summary
The transconductance is the ratio of a change in outputcurrent ( ID) to a change in the
I D
input voltage ( VGS).
This definition is gm VGS
The following approximate formulais useful for calculating gm if youknow gm0.
翫1
VGSg gm m0 VGS(off)
can be foundThe value of gm0
2I DSSfrom gm0 VGS(off)
© 2008 Pearson Education, Inc.All rights reserved
D
GS
ID
IDSS
I
V
–VGSVGS(off)
0
The JFET
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 9-18
Summary
Because the slope changes at every point along the curve,the transconductance is not constant, but depends on whereit is measured.
D
What is the transconductance forthe JFET at the point shown?
5.7
I DgmVGS
=2.0 mA
0.7 V - ( 1.3 V)
=3.33 mS0.6 V
© 2008 Pearson Education, Inc.All rights reserved
I (mA)
10 mA
8.0
6.0
4.0 3.7
2.0
–VGS-4 - 3 -2 -1 0
- 1.3 - 0.7
The JFET
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 10-18
=5.7 mA 3.7 mA
Summary
VGSThe input resistance of a JFET is given by: RIN IGSS
where IGSS is the current into the reverse biased gate.JFETs have very high input resistance, but it drops when the temperatureincreases.
Compare the input resistance of a 2N5485 at 25 oC and at 100 oC.The specification sheet shows that for VGS = 20 V, IGSS – 1 nA at25 oC and 0.2 A at 100 oC.
VGS 20 VRAt 25 oC, 20 GΩ!IN IGSS 1 nA
VGS 20 VAt 100 oC, R 100 MΩIN IGSS 0.2 μA
© 2008 Pearson Education, Inc.All rights reserved
JFET Input Resistance
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 11-18
=
= =
=
=
= =
Summary
Self-bias is simple and effective, so it is the most commonbiasing method for JFETs. With self bias, the gate isessentially at 0 V.An n-channel JFET is illustrated. The currentin RS develops the necessary reverse bias that
forces the gate to be less than the source. 1.5 k
Assume the resistors are as shown and thedrain current is 3.0 mA. What is VGS?
RG RS 330
VG = 0 V; VS = (3.0 mA)(330 Ω ) = 0.99 V
- 0.99 VVGS = 0 – 0.99 V =© 2008 Pearson Education, Inc.All rights reserved
+VDD = +12 V
RD
VG = 0 V
+ IS
1.0 M –
JFET Biasing
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 12-18
Summary
You can use the transfer curve to obtain a reasonable valuefor the source resistor in a self-biased circuit.
What value of RS should you useto set the Q point as shown?
The Q point is approximately atID = 4.0 mA and
1.25 V
VGS = - 1.25V.
VGS
ID
R 375 ΩS 3.0 mA
© 2008 Pearson Education, Inc.All rights reserved
ID (mA)
10 mA
8.0
6.0
Q 4.0
2.0
–VGS-4 - 3 -2 -1 0
JFET Biasing
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 13-18
==
Summary
Voltage-divider biasing is a combination of a voltage-dividerand a source resistor to keep the source more positive thanthe gate.
VG is set by the voltage-divider and is independent
of V . V must be larger than V in order toS S G
maintain the gate at a negative voltage withrespect to the source.
Voltage-divider bias helps stabilize the biasvariations between transistors.
for
© 2008 Pearson Education, Inc.All rights reserved
+VDD
RD
R1 ID
VG
VS IS
R2 RS
JFET Biasing
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 14-18
Summary
A graphical analysis of voltage-divider biasing is illustrated.A typical transconductance curve for the 2N5485 is shownwith IDSS = 6.5 mA and VGS(off) = - 2.2 V.
+12 VStart with VG: ID (mA)The Q-point
VG = 2.79 Vis read fromthe plot. It is
8.0V /R = 2.79 mA D
G S6.0Connect the 3.3 mA and
points to -0.7V.Q 4.0establish the
2.0load line. 1.0 k
–VGS VGS0-3 -2 -1 1 2 3
© 2008 Pearson Education, Inc.All rights reserved
1
1.0 M
+VDD
R R3.3 M 820
2.79 V 2N5485
R2 RS
JFET Biasing
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 15-18
Summary
An even more stable form of bias is +15 V
current-sourcecan be either acurrent-source
bias. The current-sourceBJT or another FET. Withbiasing, the drain current
1
G
is essentially independent of VGS.
In this circuit Q2 serves as a current source forQ1. An advantage to this particular circuit isthat the output can be adjusted (using RS2) for
0 V DC.
control
© 2008 Pearson Education, Inc.All rights reserved
out
2
+VDD
Q2N5458
R RS1
1.0 M 470
RS2
Offset 1.0 k V
Q2N5458
RS3
1.0 k
VSS
15 V
JFET Biasing
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 16-18
Summary
As described before, the ohmic region is between theorigin and the active region. A JFET operated in thisregion can act as a variable resistor.
Data from an actual FET isshown. The slopes (whichrepresent conductance) ofsuccessive VGS lines are
VG = Vdifferent in the ohmic region.This difference is exploitedfor use as a voltagecontrolled resistance.
0 1 2 3 4 5 6 7 8
© 2008 Pearson Education, Inc.All rights reserved
7
Ohmic6 VG = 0 V
region5
VG = - 0.5 VID 4
(mA)3
2 VG = -1.5 V
1
0
VDS (V)
JFET Ohmic Region
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 17-18
= −1 v
Summary
Here is a circuit in which the JFET is used as a variableresistor. Notice that that the drain is connected through acapacitor, whichorigin.
The gain of theBJT depends onthe dc voltagesetting of VGG.
means the JFET’s Q-point is at the
+15 V
RC
1 out
1 Q1
400 mV p 39 kE
© 2008 Pearson Education, Inc.All rights reserved
p R Q2
VCC
R 3.9 k V
C 56 k
1.0 µF2N3904 C2
Vs = R2 10 µF R3
1.0 kHz 6.2 k 2N5458 100 k ff VGG
JFET Ohmic Region
Copyright @2013 by Dept. of Electrical Engineering, Electronics II- Lecture 5(a)/1st Semester 013/014College of Engineering, Maysan University
Page 18-18