electronics design lab manual – vlsi prog-v3
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Electronics Design Lab Manual – VLSI Programming
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1. Finite State Machine Modeling – MOORE FSM Design
Electronics Design Lab Manual – VLSI Programming
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VHDL Code for MOORE FSM:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MOORE_FSM is
port (CLOCK, STR: in STD_LOGIC; --STR=>ST_RESULT
Z:out STD_LOGIC);
end MOORE_FSM;
architecture FSM_ARCH of MOORE_FSM is
type STATE_TYPE is (ST0, ST1, ST2, ST3);
signal MOORE_STATE: STATE_TYPE;
begin
process (CLOCK)
begin
if CLOCK='0' and CLOCK'EVENT then
case MOORE_STATE is
when ST0 =>
Z<='1';
if STR='0' then
MOORE_STATE<=ST0;
else
MOORE_STATE<=ST1;
end if;
when ST1 =>
Z<='0';
if STR='0' then
MOORE_STATE<=ST1;
else
MOORE_STATE<=ST2;
end if;
when ST2 =>
Z<='1';
if STR='0' then
MOORE_STATE<=ST2;
else
MOORE_STATE<=ST3;
end if;
when ST3 =>
Z<='0';
if STR='0' then
MOORE_STATE<=ST1;
else
MOORE_STATE<=ST0;
end if;
end case;
end if;
end process;
end FSM_ARCH;
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2. Finite State Machine Modeling – MEALY FSM Design
VHDL Code for MEALY FSM:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MEALY_FSM is
port (CLOCK, DATAIN, STR: in STD_LOGIC; --STR=> ST_RESULT
Z:out STD_LOGIC); --Z=> Dummy output.
end MEALY_FSM;
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architecture FSM_ARCH of MEALY_FSM is
type MEALY_TYPE is (ST0, ST1, ST2, ST3);
signal CUR_ST, NEW_ST: MEALY_TYPE;
begin
process(CLOCK) –- Synchronous process
begin
if CLOCK='0' and CLOCK'EVENT then
CUR_ST<=NEW_ST;
end if;
end process;
process(DATAIN, STR, CUR_ST)—Asynchronous process
begin
case CUR_ST is
when ST0 =>
Z<='1';
if (DATAIN='0' and STR='0') then
NEW_ST<=ST0;
elsif (DATAIN='0' and STR='1') then
NEW_ST<=ST1;
elsif (DATAIN='1' and STR='0') then
NEW_ST<=ST2;
elsif (DATAIN='1' and STR='1') then
NEW_ST<=ST3;
end if;
when ST1 =>
Z<='0';
if (DATAIN='0' and STR='0') then
NEW_ST<=ST1;
elsif (DATAIN='0' and STR='1') then
NEW_ST<=ST2;
end if;
when ST2 =>
Z<='1';
if (DATAIN='0' and STR='0') then
NEW_ST<=ST2;
elsif (DATAIN='0' and STR='1') then
NEW_ST<=ST3;
end if
when ST3 =>
Z<='0';
if (DATAIN='0' and STR='0') then
NEW_ST<=ST3;
elsif (DATAIN='0' and STR='1') then
NEW_ST<=ST0;
end if;
end case;
end process;
end FSM_ARCH;
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3. 8-Bit ALU Designing
ALU Process Table with Opcode and Status
S. No Operation Opcode Status@Process_Reg
1 Addition 00h 80h
2 Subtraction 01h 40h
3 Comparison 02h 20h
4 Logical AND 03h 10h
5 Logical OR 04h 08h
6 Compliment 05h 04h
7 Increment 06h 02h
8 Decrement 07h 01h
ALU Register Details
S. No Registers Used Vector Size I/O Status
1 A_REG (ARG) 8-Bit Input Register
2 B_REG (BRG) 8-Bit Input Register
3 RESULT_REG (RRG) 8-Bit Output Resister
4 FLAG_REG (FRG) 8-Bit Status Resister (O/P)
5 PRCS_REG (PRG) 8-Bit Process Register (O/P)
Register Format
Register MSB LSB Remarks
A_REG ARG(7) ARG(6) ARG(5) ARG(4) ARG(3) ARG(2) ARG(1) ARG(0) NIL
B_REG BRG(7) BRG(6) BRG(5) BRG(4) BRG(3) BRG(2) BRG(1) BRG(0) NIL
RESULT_REG RRG(7) RRG(6) RRG(5) RRG(4) RRG(3) RRG(2) RRG(1) RRG(0) NIL
FLAG_REG
(Active High)
FRG(7) FRG(6) FRG(5) FRG(4) FRG(3) FRG(2) FRG(1) FRG(0) [VECTOR MAP]
RST CY BR EQ A>B A<B PKH PKL [USER READ]
PRCS_REG
(Active High)
PRG(7) PRG(6) PRG(5) PRG(4) PRG(3) PRG(2) PRG(1) PRG(0) [VECTOR MAP]
ADD SUB CMPR L-AND L-OR CMPL INCR DECR [USER READ]
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Flag Register Description
S.
N0
FLAG Register
Bit Description (Active High)
1 FRG(7) => RST Reset Status
2 FRG(6) => CY Carry During Addition
3 FRG(5) => BR Borrow During Subtraction
4 FRG(4) => EQ A=B when Comparison
5 FRG(3) => A>B A>B when Comparison
6 FRG(2) => A<B A<B when Comparison
7 FRG(1) => PKH Peak High Trip during Increment
8 FRG(0) => PKL Peak Low Trip during Decrement
VHDL Code for 8-Bit ALU:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_8BIT is
port ( RESET, CLK : in STD_LOGIC;
OPCODE : in STD_LOGIC_VECTOR (2 downto 0);
ARG, BRG: in STD_LOGIC_VECTOR (7 downto 0);
RRG, FRG, PRG : out STD_LOGIC_VECTOR (7 downto 0));
end ALU_8BIT;
architecture ALU_ARCH of ALU_8BIT is
signal ATemp, BTemp, TEMP : STD_LOGIC_VECTOR(8 downto 0):="000000000"; --Temporary Register for ARG, BRG
and Internal
begin
process(RESET, OPCODE, ARG, BRG, CLK)
begin
if(RESET='0' and CLK='0') then
RRG<=X"00"; --RRG<="000000000";
FRG<=X"80"; --FRG<="100000000";
PRG<=X"00"; --PRG<="000000000";
else
FRG<=X"00";
ATemp <= ('0' & ARG);
BTemp <= ('0' & BRG);
case OPCODE is
when "000" => -- ADDITION Operation
PRG <= X"80"; --PRG <= "10000000";
TEMP<=(ATemp + BTemp);
FRG(6) <= TEMP(8);
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when "001" => -- SUBTRACTION Operation
PRG <= X"40"; --PRG <= "01000000";
TEMP<=(ATemp - BTemp);
FRG(5) <= TEMP(8);
when "010" => -- COMPARISON Operation
PRG <= X"20"; --PRG <= "00100000";
TEMP <= "XXXXXXXXX"; --Forced don't care for the RRG.
if (ATemp = BTemp) then
FRG(4 downto 2) <= "100";
elsif (ATemp > BTemp) then
FRG(4 downto 2) <= "010";
elsif (ATemp < BTemp) then
FRG(4 downto 2) <= "001";
end if;
when "011" => -- LOGICAL AND Operation
PRG <= X"10"; --PRG <= "00010000";
TEMP<=(ATemp and BTemp);
when "100" => -- LOGICAL OR Operation
PRG <= X"08"; --PRG <= "00001000";
TEMP<=(ATemp or BTemp);
when "101" => -- COMPLEMENT Operation
PRG <= X"04"; --PRG <= "00000100";
TEMP<= not(ATemp);
when "110" => -- INCREMENT Operation
PRG <= X"02"; --PRG <= "00000010";
TEMP<= (ATemp + 1);
FRG(1) <= TEMP(8);
when "111" => -- DECREMENT Operation
PRG <= X"01"; --PRG <= "00000001";
TEMP<= (ATemp - 1);
FRG(0) <= TEMP(8);
when others=>
RRG<=X"00"; --RRG<="000000000";
FRG<=X"80"; --FRG<="100000000";
PRG<=X"00"; --PRG<="000000000";
end case;
RRG<=TEMP(7 downto 0);
end if;
end process;
end ALU_ARCH;
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4. Universal Shift Register (4-Bit) Designing
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VHDL Code for Universal Shift Register (4-Bit):
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UNIV_SHIFT_REG is
port (RESET, CLOCK, LD_SHIFT, OE : in STD_LOGIC;
DATA_IN : in STD_LOGIC_VECTOR(3 downto 0);
Q_OUT : out STD_LOGIC_VECTOR(3 downto 0));
end UNIV_SHIFT_REG;
architecture USR_ARCH of UNIV_SHIFT_REG is
--Component Declaration
component MUX_2BIT
port(IN1, IN2, SEL: in STD_LOGIC; MUXOUT : out STD_LOGIC);
end component;
component TRI_BUF
port (A_IN, ENB, T_RESET: in STD_LOGIC; Z_OUT: out STD_LOGIC);
end component;
component D_FF
port (D, CLK, RST: in STD_LOGIC; Q, Q_BAR: out STD_LOGIC);
end component;
signal QTemp0, QTemp1, QTemp2: STD_LOGIC;
signal DTemp1, DTemp2, DTemp3: STD_LOGIC;
begin
--Component Instantiation
MUX_BLOCK1: MUX_2BIT
PORT MAP ( DATA_IN(1), QTemp0, LD_SHIFT, DTemp1);
MUX_BLOCK2: MUX_2BIT
PORT MAP ( DATA_IN(2), QTemp1, LD_SHIFT, DTemp2);
MUX_BLOCK3: MUX_2BIT
PORT MAP ( DATA_IN(3), QTemp2, LD_SHIFT, DTemp3);
TRIBUF_BLOCK1: TRI_BUF
PORT MAP ( QTemp0, OE, RESET, Q_OUT(0));
TRIBUF_BLOCK2: TRI_BUF
PORT MAP ( QTemp1, OE, RESET, Q_OUT(1));
TRIBUF_BLOCK3: TRI_BUF
PORT MAP ( QTemp2, OE, RESET, Q_OUT(2));
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DFF_BLOCK1: D_FF
PORT MAP ( DATA_IN(0), CLOCK, RESET, QTemp0);
DFF_BLOCK2: D_FF
PORT MAP ( DTemp1, CLOCK, RESET, QTemp1);
DFF_BLOCK3: D_FF
PORT MAP ( DTemp2, CLOCK, RESET, QTemp2);
DFF_BLOCK4: D_FF
PORT MAP ( DTemp3, CLOCK, RESET, Q_OUT(3));
end USR_ARCH;
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VHDL Code for 2-Bit Multiplexer:
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity MUX_2BIT is
port(IN1, IN2, SEL: in STD_LOGIC; MUXOUT : out STD_LOGIC);
end MUX_2BIT;
architecture MUX_ARCH of MUX_2BIT is
begin
process(IN1, IN2, SEL)
begin
case SEL is
when '0' => MUXOUT <= IN1;
when '1' => MUXOUT <= IN2;
when others => MUXOUT <= 'Z';
end case;
end process;
end MUX_ARCH;
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VHDL Code for Tri State Buffer:
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TRI_BUF is
port (A_IN, ENB, T_RESET: in STD_LOGIC; Z_OUT: out STD_LOGIC);
end TRI_BUF;
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architecture TSB_ARCH of TRI_BUF is
begin
process(A_IN,ENB,T_RESET)
begin
if (T_RESET ='1' and ENB='1') then
Z_OUT <= A_IN;
elsif (T_RESET ='1' and ENB='0') then
Z_OUT <= 'Z';
else
Z_OUT <= '0';
end if;
end process;
end TSB_ARCH;
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VHDL Code for D-Flip Flop:
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D_FF is
port (D, CLK, RST: in STD_LOGIC; Q, Q_BAR: out STD_LOGIC);
end D_FF;
architecture DFF_ARCH of D_FF is
signal QTemp : STD_LOGIC;
begin
process(D,CLK, RST)
begin
if RST='0' then QTemp <='0';
elsif (CLK='1' and CLK'EVENT) then QTemp <= D;
end if;
Q<=QTemp;
Q_BAR<=not(QTemp);
end process;
end DFF_ARCH;
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