CS 150 - Fall 2005 – Lec. #12: Course Project - 1

Electronic Etch-a-Sketch Project

Project Concept and Background Checkpoint Structure Bells and Whistles

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Objectives

Broad “brush” overview of the project

Details will be covered in the lab lectures

NOTE: anything discussed in the lab lectures and project checkpoint write-ups supercedes what I describe here! The TAs know the project better than I do!

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Etch-a-Sketch

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Electronic Etch-a-Sketch

AKA an electronic “paint” machine …

Recent CS 150 projects: network streaming audio, network digital “telephone”, pong, video image processing, … audio and/or video a common theme

This is a good CS 150 project because … It is NOT a processor architecture (take CS 152 for that!) Vast majority of digital designs involve interfacing with the real

world, with real world timing constraints! Hardware Systems: Input, Processing, Output

Pen/brush position/size (and special effects) inputs State of the screen in frame buffer in SDRAM Modified by drawing semantics Refresh LCD screen from frame buffer in SDRAM

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Etch-a-Sketch One possible way to do it …

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Electronic Etch-a-Sketch

Implement this … with this …

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Flash Card & Micro-drive Port

Video Encoder & Decoder

AC ’97 Codec & Power Amp

Video & Audio Ports Four 100 Mb Ethernet Ports

8 Meg x 32SDRAM

Quad Ethernet Transceiver

XilinxVirtex 2000ESeven Segment

LED Displays

Prototype Area

Calinx Board

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Calinx Board

Etch-a-Sketch Block Architecture

Checkpoint #1:N64 Game Controller

Interface

Checkpoint #2:NTSC Video

Checkpoint #3:SDRAM

ControllerArbiter

Checkpoint #4:Paint Engine

Cursor PositionCursor SizeBrush Color P

ain

t E

ngin

e-

SD

RA

M Inte

rface

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Checkpoint #1: N64 Interface

This week in lab! Continually poll N64 and report state of buttons and analog

joystick Issue 8-bit command Receive 32-bit response

Each button response is 32 bit value containing button state and 8-bit signed horizontal and vertical velocities

Serial interface protocol Multiple cycles to perform each transaction

Bits obtained serially--UART-like functionality Framing (packet start/stop) Bit encoding

start | data | data | stop

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Checkpoint #2: Video Encoding Pixel Array:

Digital image represented by matrix of values, where each is a function of the information surrounding it in the image; single element in image matrix: picture element or pixel (includes info for all color components)

Array size varies for different apps and costs: some common sizes shown

Frames: Illusion of motion created

by successively flashing still pictures called frames

High-Definition Television (HDTV), 2 Mpx

Workstation, 1 Mpx

PC/Mac, 1‡2 Mpx

Video, 300 Kpx

SIF,82 Kpx

High-Definition Television (HDTV), 1 Mpx

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Checkpoint #2: Video Encoding

Video details fairly complex and involve many choices: NTSC vs. PAL, HDTV, … Interleaved even-odd frames (TV) vs. progress scan (computer

and digital displays) Frame size, frame rate Pixel encodings: RGB, YUV/YCB (Luminance, Chrominance --

brightness plus color difference signals) Subsampling to reduce data demands (compression trick) Inputs: ITU-R BT.601 Format (Digital Broadcast NTSC) Outputs: Component video, S-video to drive LCDs in lab Fortunately, Calinx board has a chip on-board that deals with

much of the grungy details …

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ITU-R BT.656 Details Interfacing details for ITU-601

Pixels per line 858Lines per frame 525Frames/sec 29.97Pixels/sec 13.5 MViewable pixels/line 720Viewable lines/frame 487

With 4:2:2 chroma sub-sampling, send 2 words/pixel (Cr/Y/Cb/Y)

Words/sec = 27MEncoder runs off a 27MHz clock

Control info (horizontal & vertical synch) is multiplexed on data lines

Encoder data stream show to right

See video tutorial documents on course documentation web page!

718 719 720 721 0 1 2

359 360 0 1

359 360 0 1

736732( )

368366( )

368366( )

857863)(

Y 718

Y 719

C 360

B Y 720

C 360

RY 721

C 359

BC 359

RY 736(732)

C 368(366)

BC 368(366)

RY 855(861)

C 428(431)

BY 856(862)

Y 857(863)

C 0B

Y 0

C 0R

Y 1

C 428(431)

R

C 0B

Y 0

Y 1

C 0R

C 359

BY 718

Y 719

C 359

R

Last sampleof digital active line

Sample datafor O instant

First sampleof digital active lineH

Luminancedata, Y

Chrominancedata, CR

Chrominancedata, CB

Replaced bytiming reference

signal

Replaced bydigital blanking data

Replaced bytiming reference

signal

End ofactive video

Start ofactive video

Timing reference signals

Note 1 – Sample identification numbers in parentheses are for 625-line systems where these differ from those for 525-line systems. (See also Recommendation ITU-R BT.803.)

FIGURE 1

Composition of interface data stream

D01

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Checkpoint #2: Video Encoder

Paint engine processes pixels within frame buffer Drive ADV7194 video encoder device to output correct NTSC video Gain lots of experience reading data sheets Dictates the 27 MHz operation rate

Used throughout graphics subsystem

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Calinx On-Board Video Encoder Analog Devices ADV7194: ITU 601/656 in, Composite Video

Out

Supports: Multiple input formats and outputs Operational modes, slave/master Used in default mode: ITU-601 as slave

s-video output

Digital input side connected to Virtex pins

Analog output side wired to on board connectors or headers

I2C interface for initialization: Wired to Virtex

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Checkpoint #3: SDRAM Interface

Memory protocols Bus arbitration Address phase Data phase

DRAM is large, but few address lines and slow Row & col address Wait states

Synchronous DRAM provides fast synchronous access current block Little like a cache in the DRAM Fast burst of data

Arbitration for shared resource

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SDRAM READ Burst Timing

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Checkpoint #4: Paint Engine

Fed a series of “brush” strokes and effects Defined by color (including erase), brush shape (height, width),

etc. Current brush positions All from N64 Controller interface NOTE: lots of buttons, and lots of opportunity for extra credit

brush effects

Renders “paint” into frame buffer within range of pixels at current cursor position

Must arbitrate for SDRAM and carry out bus protocol Paint engine overlaps writing SDRAM with video interfacing

reading SDRAM to drive LCD display Continuously feeding video interface from SDRAM subject to

timing specifications

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Checkpoint Structure and Schedule

Checkpoint #1: Game Controller Interface (Week 7)

Checkpoint #2: LCD Interface (Week 8)

Checkpoint #3: Memory Interface (Week 9, 10 -- Spans Midterm II)

Checkpoint #4: Paint Engine/Integration (Week 11, 12, 13+)

Early Check-off: Wednesday before Thanksgivings (November 23)

Standard Check-off: Wednesday, November 30

Project Final Report: December 7

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Possible Bells and Whistles

Still thinking about this but here are some ideas;These are mostly implemented in the paint engine … Brush sound effects Brush effects, like spray paint, splashes, etc. Brush shapes, like square, oval, triangle Brush physics, soft vs. hard brush, brush angle, etc. (e.g.,

Japanese caligraphy) Color mixing rather than overwrite Your good idea here NOTE: We don’t necessary know how to implement these

ourselves! NOTE: extra credit will be limited to 20% extra points and no

extra credit unless the standard functionality works

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