electronic devices in mtl annual report 1998

8/2/2019 Electronic Devices in MTL Annual Report 1998

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CMOS Technology for 25 nm Channel Length

SponsorshipDARPA and ONR

PersonnelA. Lochtefeld and I. Sokolinski(D. A. Antoniadis, J. Chung, and H. I. Smith)

The scaling of CMOS transistors into the sub-100 nmregion is extremely challenging because of short-channeleffects. We are pursuing two distinct approaches thatshould permit scaling to 25 nm channel lengths. Both can

be considered 3-dimensional-gate CMOS (3DG-CMOS)technologies. One is a planar twin-gate configuration,with either joint or independent control of the two gatesper MOSFET; the other features a gate that surrounds apillar-like vertical channel.

Monte-Carlo modelling predicts that twin-gated devicesthat are scaled to Leff = 25 nm will havetransconductances Gm in excess of 2000 mS/um, whilemaintaining almost perfect sub-threshold slope. How-

ever, models also predict that the tolerance in aligningfront and back gates has to be within Lg/4 in order toavoid performance deterioration due to overlap capaci-tance. The Lg/4 requirement translates into 6 nm align-ment tolerance for a 25 nm channel. In order to meet thisalignment challenge we will use the IBBI alignmenttechnique which achieves sub-nanometer misalignmentdetectivity. The planar twin-gate devices will be fabri-cated starting with a SIMOX wafer. First the gate stackfor the back-gate will be deposited and patterned by x-ray lithography. The structure will then be covered by alayer of CVD oxide, planarized, and bonded to ahandle wafer. The bulk of the SIMOX wafer will then

be chemically etched using the back-oxide of the SIMOXwafer as the etch-stop. The fabrication will then follow aconventional SOI process, with front gate preciselyaligned to back-gate layer using the IBBI alignmentscheme. The final structure is depicted in Figure 1.

The second approach to 3DG-CMOS utilizes epitaxiallygrown vertical pillars of Si. Such a structure addressestwo major problems in ultra-short-channel MOS fabrica-tion. First, a surround-gate has maximum possiblecontrol of the channel potential, improving sub-thresh-old slope and reducing short-channel effects to allowscaling of the effective channel length (L

eff) down to

25 nm for pillar MOS device 40 - 50 nm in diameter.Second, epitaxial definition of a vertical channel allowsalmost arbitrarily short Leff with tighter control than ispossible with current lithography technologies. Inplanar MOS devices, gate length is limited by lithogra-phy; the inherent variability in the lithography and etchprocesses can lead to unacceptable variation in Leff fromdevice to device and wafer to wafer. This is especiallycritical in ultra-short-channel devices, where the thresh-old voltage is extremely sensitive to gate length.

50 nm

Selectivelygrown Si contacts

WSi2

Silicon

TEOS

Substrate

n+

Gate and back-gateoxides are 2 nm thick

10-20 nm

SiN

LTO

Locos

/ U s e r s

/ i l i

a / F i g

s / A

r c h i v

e / r e p o r t s

/ R L E 9 7 / d

g a

t e . e

p s

n+/p+poly ormidband gatematerial

XSi

bonded interface

continued

Fig. 1: Dual gate n-MOS transistor with 25 nmeffective channel length.


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Previously demonstrated processes for epitaxially-defined vertical MOS structures generally start with theetching of a pillar from the epi wafer, and suffer fromsevere difficulties in the subsequent contact and isolation

of gate and source/drain regions. These problems areavoided in our proposed vertical-MOS process, illus-trated in Figure 2, where the gate electrode material anddielectrics for source/drain isolation are deposited priorto hole-definition and epitaxial growth.

We are currently experimenting with selective epitaxialgrowth in features down to 100 nm in diameter patternedin oxide on silicon, a key technology for our novelvertical-MOS process. t

Fig. 2: Process for Fabricating Surrond-GateVertical MOS Devices.

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Design and Fabrication of Single-Mask 50 nm MOSFETs

SponsorshipDARPA, ONR, and NSF Graduate Fellowship

PersonnelK. M. Jackson and Z. Lee(D. A. Antoniadis and H. I. Smith)

As MOSFET dimensions are scaled to lengths below100 nm, significant challenges arise in controlling fabrica-tion processes. Rapid turnaround between processchanges and device results, and an ability to extract the

exact structure and doping of the fabricated device aretools critical to this development. The first requires ashort-flow process that focuses only on the fabricationsteps that critically define device performance in aminimum number of steps. The second tool, known asinverse modeling, couples a device simulator with anoptimizing routine that shifts the doping in the simu-lated device until the current-voltage and capacitancecharacteristics of the simulated device match those of thereal device. This project focuses on creating a short-flowprocess for 50 nm channel-length MOSFETs and cou-pling it with currently exisiting inverse modeling capa-bilities.

The short-flow process we have conceived will allowworking MOSFETs to be fabricated in one mask step. It isshortened from a normal full-length MOSFET process byeliminating the need for oxide isolation around the

devices and by eliminating the need for the passivationand metal layers at the end of the process. Two types ofstructures will allow devices to be operational MOSFETswithout field-oxide isolation. The first structure is anannular device where the source is completely enclosedinside of a gate and the drain is outside of the annulargate. The second structure is a figure-eight configura-tion (Figure 3) where the parasitic out-of-channel (i.e.field region) source-to-drain current is less than 0.02times the in-channel current under the gate in the centerof the structure. By using a self-aligned cobalt-silicideprocess (salicide) the source and drain will be low

Fig. 3: Gate mask layout of a figure-eight geometry MOSFET. The inner two white square areas are the source and drain probe pads that willbe salicided. The dark wide ring is the gate pad with the active gate being the fine line in the center. The outer ring is a guard ring.


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continued

continued

enough in resitivity that they can be contacted directly byprobes. Even though two significant steps of the conven-tional fabrication process are left out, the steps thatdefine the device operation - the gate stack, implantation,

and critical high temperature steps - are all contained inthe short-flow process.

The gate-level lithography (the only lithography step) forthe short-flow process will be done using X-ray lithogra-phy, easily allowing linewidths down to 50 nm. Themask will be fabricated with a mix of optical steps for thelarge features and e-beam writing for the fine gates.Using optically placed e-beam registration marks, the e-beam tool can match the in-plane scale and distortion ofthe optical projection tool to achieve good patternplacement.

The key elements in the fabrication of sub-100 nm devicesare the placement of dopants and the use of very thingate oxides. A process to grow 20 oxides in N2O hasbeen developed. With such thin oxides, etching the poly-silicon gate and stopping on the gate oxide will be themajor challenge. The placement of the dopants calls for acombination of implantation and diffusion. We areinvestigating very-low-energy implants for the sourceand drain of these devices. Dopant diffusion will becarefully controlled by a few high temperature, rapidthermal anneals. Building on our previous successes infabricating robust 100 nm NMOS, we will explore theoptimization of source and drain design.

Once devices are fabricated using the short-flow process,their doping and structural components can be evaluatedvia inverse-modeling, using current-voltage and capaci-tance measurments. Understanding what dopingprofiles were achieved versus the original design thenwill allow us to go back and adjust the process and to seehow changes affect the doping profiles in the device.This approach should facilitate the optimization of devicefabrication for deep-sub-100 nm MOSFETs. t

Device Design to Minimize HystereticEffects in SOI MOSFETs

PersonnelA. Wei and A. Ritenour(D. A. Antoniadis)

SponsorshipSRC

SOI MOSFETs offer many performance benefits overbulk MOSFETs including reduced junction capacitanceand reduction of the negative back-bias effect in pass-gates and stacked transistors. However, floating-body

operation of partially-depleted SOI MOSFETs leads toswitching-history-dependent body charge, and hencehysteretic device threshold voltage. This is of seriousconcern in SOI-CMOS circuit design because floating-body-induced threshold-voltage variation, VT, contrib-utes to propagation delay variation, particularly as thesupply voltage is reduced. It is important to develop adevice design methodology which minimizes this thresh-old-voltage variation.

Body charge in a SOI MOSFET with the body floating isswitching-history dependent because on the timescaletypical of digital switching, body charge typically re-

moved and replenished by a body contact cannot becompletely removed or replenished by the diodes andimpact ionization schematically shown in Figure 4; thebias voltage on the body is determined by the capacitivenetwork shown in Figure 5. Thus it takes many switch-ing cycles to establish a switching-steady-state per a

Buried Oxide

S D

G

VB

III

Fig. 4


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particular switching waveform, and a long time to relaxto initial conditions. Also, starting from these initialconditions, there is already an initial imbalance in bodycharge between devices in different logic states. This

difference in initial body charge and the history depen-dence of body charge leads to an initial VT, which thenchanges during subsequent device switching.

It is possible to minimize VT by design of the devicefilm thickness, such that body charge is unchanged in thetwo different logic states OUT-HI and OUT-LO. Designof the device for decreased gate-body capacitive cou-pling and non-ideal body-source/drain diode behavioralso tends to minimize VT. Both of these designs are inaccordance with bulk MOSFET scaling trends, withshrinking gate length and increased peak channeldoping. However, minimization of hysteresis by re-

duced gate-body capacitive coupling and non-idealbody-source/drain diode behavior tends to negate someperformance advantages by reducing capacitivelycoupled on-current overshoot and by introducing a highinitial body voltage which leads to increased off-stateleakage and poor subthreshold slope. t

Cgs Cgb

Cbs Cbd

Cgd

CdsubCssub

BS D

G

SUB

Cbsub

Fig. 5

Self-Aligned Dual-Gate VariableThreshold Voltage (VT)CMOSTechnology

PersonnelA. Wei and A. Ritenour(D. A. Antoniadis)

SponsorshipSRC

Continued power supply scaling in CMOS technologyrequires scaling of device threshold voltage to maintaincircuit performance. However, reduced device thresholdvoltage leads to unacceptably high off-state leakage

current, particularly as device dimensions are reduced.A variable threshold-voltage CMOS technology allowsfor reduced threshold voltage during periods of highcircuit activity and an increased threshold voltage whenthe circuit is idle for long periods of time.

Silicon-On-Insulator with Active Substrate (SOIAS) hasbeen demonstrated in which a buried back gate is usedto modulate the front gate threshold voltage of a fully-depleted SOI MOSFET. Fully-depleted SOI MOSFETsare ideal for variable threshold voltage technology due totheir inherently low threshold voltage, and the additionof the backgate facilitates fully-depleted SOI MOSFET

scaling into extreme submicron regimes. Alignment ofthe front and back gates is difficult, however, and SOIAStechnology used an oversized backgate, formed in buriedunpatterned polysilicon. Oversize of the backgate leadsto a large drain-to-backgate overlap capacitance resultingin degraded performance.

Shown below in Figure 6 is a representational cross-section of a self-aligned dual-gate variable thresholdvoltage CMOS. The structure is a fully optimizedversion of SOIAS technology featuring self-alignment offront and back gates, silicided front and back gates, andsilicided raised source/drain to minimize series resis-tance in the fully-depleted MOSFET. It is fabricated byforming the backgate stack on an SOI wafer. Thebackgate stack is silicided, patterned, filled with dielec-tric, chemical-mechanical-polished flat, flipped, andbonded to a handle wafer. The substrate of the SOIwafer, now on top, is removed in a chemical etch, andthe buried oxide of the SOI wafer is removed leaving theSOI film on which to build devices. Devices are alignedto the prepatterned backgates. The prepatternedbackgates are oversized relative to the front gate in order

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to meet alignment tolerances. Full self-alignment isachieved by counterdoping of the backgate through thefrontgate in order to form regions with low doping. Thisshould significantly reduce overlap capacitance. A

raised source/drain is then formed by selective epitaxyand the top device is silicided and contacted.

continued

n- n-

n+

p++

p++ p++n

n+

p- p-

p+

n++

n++ n++p

p+

Substrate

Oxide

The feasibility of this technology will be evaluatedrelative to device design requirements dictated by devicescaling. t

Fig. 6


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RF SOI LDMOS Power Devices

PersonnelJ. G. Fiorenza(J. A. del Alamo and D. A. Antoniadis)

SponsorshipSRC

Our project involves the design and fabrication of RF(Radio Frequency) SOI (Silicon-On-Insulator) LDMOS(Laterally Diffused MOS) power devices. SOI-LDMOS iswell suited for the development of devices for the high-

frequency, high efficiency power amplifiers that arerequired by portable wireless communication handsets.It is also a technology that could potentially enable theintegration of analog, digital and RF circuits onto a singlesubstrate and provide an avenue for the realization of asingle-chip wireless communication system.

A cross-section of the RF SOI LDMOS device that wehave designed is shown in Figure 7. The device is aMOSFET with several enhancements to give it superiorRF power performance. The laterally doped body is

designed to increase the devices gain at high frequency,while the lightly doped N-type drift region combinedwith a body tie under the source increases the devicespower handling capability. Silicide on the source, gate,and drain improves the devices power efficiency. Theinsulating buried oxide layer reduces the parasitic draincapacitance and improves the isolation between differentdevices on the same substrate. The device fabricationprocess has been designed to avoid exotic processingtechniques so that it will ultimately be possible tointegrate the power device process into a standarddigital SOI CMOS process. Microwave and DC teststructures are being fabricated to measure the power

device performance, the isolation properties of the SOIsubstrate, and to understand how the SOI substrateaffects the LDMOS fabrication process. t

Fig. 7: RF SOI LDMOS Power Device.


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Correlation of Silicon Microroughness on Electrical Parametersof SOIAS (Silicon-On-Insulator with Active Substrate)

PersonnelH. Nayfeh(D. A. Antoniadis)

SponsorshipDARPA

The SOIAS process previously developed at MIT allowsthe transfer of a thin single-crystalline layer of device-quality silicon from a SIMOX (Separation by Implanta-tion of Oxygen) wafer to a bulk carry wafer. As the carry

wafer can potentially have pre-fabricated layers ofinterconnects and gates, this technology holds promisefor future 3D integration. We have studied the surfacequality of this transferred silicon layer, and have devel-oped a chemical-mechanical polishing process to im-prove this surface.

The single-crystalline silicon layer is flipped in theprocess of bonding to the carry wafer. Thus, the topsurface of the SOIAS wafer, to be used for subsequentdevice fabrication, is the poorer quality buried siliconinterface from the initial SIMOX wafer. This calls for aproper investigation and optimization of the surface

properties of SOIAS. Novel Chemical MechanicalPolishing (CMP) techniques were used to achieveminimum surface roughness. Electrical parameters arebeing determined by measuring the interface statedensity (Dit) using charge pumping, the dielectricbreakdown using Time-Zero Dielectric Breakdown(TZDB), and the effective mobility (

ff)as a function of

vertical electric field. The surface has been characterizedusing Atomic Force Microscopy (AFM) as can be seen inFigures 8 and 9. The relationship between surfaceroughness and these parameters is being determined by

measuring the above electrical parameters on fabricatedgated P-i-N diodes and NMOS transistors with differentinitial surface roughness.

Surface roughness on the atomic scale is expected tocontribute to interface trap states. These sites can then beoccupied by carriers resulting in more scattering eventsthat lead to lower values of mobility. It has also beenshown that smoother surfaces have a better couplingbetween gate voltage and surface potential leading tohigher mobilities. In addition, as the scaling down oftransistor dimensions becomes a viable thrust in thetechnology industry to achieve larger density of inte-

grated circuits, reduction of the oxide thickness becomesmandatory. This poses a serious challenge to avoiddielectric breakdown. It has been reported that rough-ness reduces the intrinsic breakdown field strength byfield enhancement at pointed bumps at the irregular Si-SiO2 interface. Therefore, the quality of the Si-SiO2 willbe crucial in achieving this goal. t

Fig. 8: SOIASWafer - 3.96 nm RMS. Fig. 9: SOIAS Wafer After Touch Polish - .123 nm RMS.


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On-State Breakdown in Power HEMTs: Measurements and Modeling

PersonnelM. Somerville(J. del Alamo in collaboration with G. Duh and P. C. Chao - Sanders)

SponsorshipJSEP

Although great strides have been made in understandingand improving off-state breakdown (BVoff) in HighElectron Mobility Transistors (HEMTs), work on the on-state breakdown voltage (BVon) has been limited due to

difficulties in defining and measuring this figure ofmerit. This is problematic, as BVon is now recognized asthe crucial parameter limiting HEMT power perfor-mance. We have recently proposed a simple, unambigu-ous, reproducible, and non-destructivegate currentextraction measurement for BVon. This method, inconjunction with detailed temperature-dependentmeasurements and sidegate measurements, has revealedthe roles of impact ionization and tunneling plus Thermi-onic Field Emission (TFE) in BVon and BVoff. It has also

allowed us to develop a simple model for BVon. Ourfindings suggest that depending on device design, eitherBVoffor BVon can limit the maximum power density of aHEMT.

The inset of Figure 10 depicts the measurement tech-nique for BVon. IG is held constant at a desired value (atypical condition is 1 mA/mm), and ID is ramped fromIG to some reasonable value (typically 1/5 IDmax). Thistechnique traces a locus of VDS versus ID for constant IG;we define this locus as BVon. This definition is sensiblein several respects: (1) it ramps from BVoff which isusually defined as IG = ID; (2) it defines a locus ofsignificant gate conductance; (3) it is a reasonablepredictor for device burnout.

Fig. 10: BVon versus ID for 0.1 m InAlAs/InGaAs HEMT for different values of IG. The data are superimposed on the output characteristics.The constant IG criteria additionally tracks the sudden rise of drain conductance often associated with BVon. The inset shows the biasingcondition for the gate current extraction measurement. A constant current (typically 1 mA/mm) is extracted from the gate while ID is sweptfrom the off-state (1 mA/mm) to the on state (200 mA/mm). The technique traces a breakdown locus of VDS versus ID.

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The technique is illustrated on a state-of-the-art 0.1 mInAlAs/InGaAs HEMT in Figure 10, where BVon loci forseveral values of IG are superimposed on the outputcharacteristics. As the device is turned on, BVon drops

from 4.2V (BVoff) to less than 2.5 V. For VDS > BVon, thedrain conductance begins to rise, indicating that thedevice is approaching a dangerous bias region. Burnoutmeasurements show that this analysis is correct wehave found that once the device is turned on, burnoutoccurs at an approximately constant value of IG.

Because the technique is safe and reproducible, we havebeen able to perform temperature dependent measure-ments of BVon and BVoff. These measurements, inconjunction with sidegate measurements, have allowedus to create a comprehensive picture of off-state and on-state breakdown. In the off-state, IG is almost purely

thermionic field emission. However, as ID rises, impactionization starts to produce holes which escape to thegate. To maintain constant IG, VDG must drop. Once thedevice is fully on, BVon is dominated by impact ioniza-tion. Due to the exponential dependence of impactionization on field, the locus of BVon of becomes almostvertical.

Our simple picture of BVon has lead to a phenomenologi-cal model that can assist device and circuit designers.The model accurately predicts the behavior of BVon, for avariety of devices, and makes it clear that the shape of thetransition from BV

off to BV

on is crucial to a devices

power potential.

In summary, we have developed an unambiguousdefinition and a simple, non-destructive measurementfor BVon in HEMTs. Both BVoff and BVon must beconsidered when designing a power device. t

Drain Resistance Degradation inInAlAs/InGaAs Power HEMTs

PersonnelS. D. Mertens and T. Payakapan(J. A. del Alamo in collaboration with L. Studebaker andD. DAvanzo - HP)

SponsorshipHP

InAlAs/InGaAs High Electron Mobility Transistors(HEMT) hold promise for power-millimeter waveapplications. A major reliability concern in some of thesedevices is the degradation of the drain resistance that is

at times observed when the device is stressed for a longtime at bias conditions necessary for power applications.The goal of this project is to find the physical origin ofthis reliability problem and to provide a solution to it.

State-of-the-art InAlAs/InGaAs power HEMTs, pro-vided by our sponsor, Hewlett Packard, were stressedunder different biasing schemes. One of these methodsconsists of forcing constant gate and drain currentsthrough the device of a magnitude that corresponds to atypical bias point for power operation. As can be seen onthe example shown in Figure 11, under the selectedconditions the drain resistance degrades quickly. There

are four noticeable regimes to Rd degradation in thisdevice. First, a small but immediate degradation ofabout 2%. This is followed by a linear degradation forabout 150 minutes. After this, the degradation ratedecreases, but seems to be linear for another 300 minutes.For longer time, the degradation rate slows downconsiderably.

A whole suite of device measurements is taken atfrequent time intervals during stressing. In addition todrain resistance degradation we have found that thesource resistance initially improves about 5% until acertain saturation value is reached. The off-state break-down voltage improves about 10%, at first, but after along period it decreases quickly by as much as 50%. Thepeak transconductance decreases approximately linearlyby about 9%, but the intrinsic transconductance increasesby about 2%. The threshold voltages increases initiallyby about 2%, but after 500 minutes it starts to decrease.Dependent on the stressing conditions, some devices fail(burnout) after a certain stressing time.

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The combination of results that we have obtained suggestthat major changes are occurring at the drain side of thedevice as a result of the bias stressing. However, itappears that some changes are also taking place at the

source and in the intrinsic portion of the device. Muchmore work is needed before the physical origin of thisreliability concern is identified. t

0 100 200 300 400 500 600 700 800 900 10001.0

1.1

1.2

1.3

1.4

1.5

1.6

PSM 453S036 4 m S-Dc5

RD/RD(0) vs time stressed at I D=367 mA/mm and I G=-0.275 mA/mm

RD(0)=0.822 .mm

Rd/Rd

(0)

time [min]

Fig. 11: Time evolution of the drain resistance of a InAlAs/InGaAspower HEMT stressed at ID = 392 mA/mm and IG = -0.275 mA/mm.

GaN Solar Blind UV Photodetectors

PersonnelA. Sampath - Boston University(A. I. Akinwande and T. D. Moustakas -Boston University)

SponsorshipDARPA

There is considerable interest in fabrication of solar-blind UV photodiodes for a number of applications,including early missile detection system. The AlxGa1-xNmaterial system is ideal for these applications since this

system consists of direct band gap semiconductorstunable between 3.4 eV (364 nm) for GaN and 6.2 eV(200 nm) for AlN. However, significant problems existin this material system due to the relatively high disloca-tion densities (108-1010 cm-2), the difficulty in growinghigh carrier concentration p- doped material, and thelack of good low resistance p-ohmic contacts. The goalof this collaboration between the Molecular BeamEpitaxy (MBE) laboratory at Boston University and MTLat Massachusetts Institute of Technology is to fabricate p-i-n photodiodes using the AlxGa1-xN system which showhigh responsivity, sharp absorption cutoff above 364 nmand low dark currents.

continued

Fig. 12: IV Characteristics of .0401 mm2 area devicein the dark and under 365 nm illumination.

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The p-i-n GaN films are grown by MBE on either c-planesapphire, or 25 m thick n-type GaN substrates grownby hydride vapor phase epitaxy. Fabrication of thedevice consists of a three-mask process to create a mesa

and to deposit ohmic contacts. The device is fullypassivated using a SiNx layer. Fabricated devices on asingle wafer have varying geometries so that darkcurrent can be studied as a function of both deviceperimeter and area. Presently, our studies on fabricateddevices show that dark currents scale with area, suggest-ing that our leakage currents are primarily due to a bulkrather than a surface effect. Figure 12 shows the IVcharacteristics of a p-i-n device both in the dark andunder illumination by 365 nm light. An additionalmasking step is being explored to introduce a dielectricpad upon which a large area p-ohmic contact can beplaced. This contact pad isolation would reduce the

overall electrical area of the device so that dark currentcan be minimized.

The ultimate objective of this project is to fabricate anarray of Avalanche photodetectors that are sensitive inthe UV solar blind regime. The reverse leakage currenthave to be significantly reduced in order to obtaininternal gain by avalanche multiplication. Our effortsare being focused on reducing the defect density to alevel that will lower the dark currents at the high volt-ages required for avalanche multiplication. t

Fig. 13: Photo p-i-n GaN photodetector.

Linearity of GaAs HBTs

PersonnelR. Chatterjee(J. A. del Alamo)

SponsorshipNone

AlGaAs/GaAs Heterostructure Bipolar Transistors(HBT) are important for high-performance RF PowerAmplifiers (PA) and are especially attractive because oftheir superior linearity properties. There are several

performance figures of merit that an HBT must bedesigned for in RF power applications. These includethe Gain (G), power output (POUT), Power AddedEfficiency (PAE), and third order IntermodulationDistortion (IMD3) which is a measure of linearity. Ahigh G is desired so that the PA can be constructed witha minimum number of stages. A high PAE is necessaryfor long operation times on battery operated systems.The POUT is a system requirement. A low IMD3 isneeded so that signal spillover to an adjacent channel isminimized. Currently there is a good understanding ofthe aspects of device design that impact POUT, G, andPAE. Much of the work directed towards designing for

linearity relies on crude models with poor fundamentalbasis. A solid understanding of the relation between thestructural parameters and the linearity of HBTs is crucialfor successful RF power device design. Contributing thisunderstanding is the goal of this project.

IMD3 is a figure of merit for linearity that is based ontwo-tone intermodulation distortion measurements. Inthis technique, two different sinusoidal signals offrequencies f1 and f 2 are input to a PA. Since the HBT isnot perfectly linear, these two frequencies produceseveral harmonics on the output. The power of theoutput signal at a frequency of f = 2f

1 f

2 is the low-

frequency third-order intermodulation distortion(IMDL) and the power at the frequency f = 2f2 f 1 is thehigh-frequency third order intermodulation distortion(IMDH). The IMD3 figure of merit is derived whenIMDL is normalized by Pout(f1) which is fairly close tothe result of normalizing IMDH by Pout(f2). The units ofIMDL and IMDH are dBm and the unit of IMD3 is dBc.If f 1 and f 2 are not very different, these two spuriousfrequencies, (2f1 f 2) and (2f2 f 1) could fall in anadjacent channel producing undesirable interference.

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This is relevant because while the PA is being used, itwill have inputs of many frequencies within somebandwidth. The IMD3 figure of merit attempts toaccount for potential interference among frequency

components in this bandwidth by examining only theinterplay of two frequencies as a representation of theintermodulation of any of the other frequencies in thatbandwidth.

To assess the linearity, an adequate simulation environ-ment must be used. HBTs operating in the large signalregime are typically modeled with the Gummel-PoonBipolar Transistor Model (GP). The GP model is used inmany commercial CAD systems such as HP-Libra.Figure 14 shows measured and simulated data for PAEand G from single tone simulation and measurement.

Figure 15 shows measured and simulated data for IMD3in the HP-Libra simulation environment. Two signalswith different frequencies (f1 = 837 MHz and f 2 = 837.1MHz) are input into a state-of-the-art AlGaAs/GaAsHBT in a common-emitter configuration. As can be seenfrom these plots, the simulation is very good at predict-ing the measured results. This excellent agreementbetween simulation and measurement are a good basisto understand what aspects of device design impactIMD3.

From the GP model, several sources of non-linearity areseen. Some of the most significant ones are: the expo-nential relationship between VBE and IC, the exponentialrelationship between VBE and IB, the VBC dependence ofbase to collector capacitance (CBC), and the VBE depen-dence of base to emitter capacitance (CBE). The next stepis to develop analytical models of each of the devicenonlinearities that would help us identify the dominantsources of intermodulation distortion. t

Fig. 14: Measured and Simulated G and PAE vs. POUTfor a state of the art AlGaAs/GaAs HBTs.

Fig. 15: Measured and Simulated IMD3 vs. POUTfor a state of the art AlGaAs/GaAs HBTs.


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Physical Mechanisms Limiting the Manufacturing Yield of Millimeter-WavePower InP HEMTs

PersonnelS. Krupenin(J. A. del Alamo)

SponsorshipMAFET Program (through Sanders Lockheed Martin)

Despite the improving prospects for InP High ElectronMobility Transistors (HEMTs) in millimeter-wave powerapplications, an understanding of the factors affectingthe manufacturing yield of these devices has been

hampered by the considerable amount of work that ittakes to evaluate millimeter-wave power figures ofmerit. Manufacturing yield improvement is criticalbecause high cost represents a significant road block inthe development of millimeter-wave systems.

We have addressed this issue by developing a yieldassessment methodology that is based on a statisticalstudy of DC figures of merit obtained in actual transis-tors. We measured the threshold voltage, maximumdrain current and transconductance, on- and off-statebreakdown voltages, and other figures of merit thatstrongly impact millimeter-wave performance of InP

HEMTs. We characterized 50 power 0.1 m double-heterostructure InAlAs/InGaAs HEMTs on InP on anexperimental 3-inch wafer from Sanders LockheedMartin.

A Principal Component Analysis (PCA) was carried outin an attempt to uncover the physics underlying thecorrelation between these figures of merit. PCA performsa coordinate transformation from the original space of

electrical measurements to the space of uncorrelatedprincipal components. These are ordered according tothe total variance that they account for in the originaldata: first the variance explained by P1 is maximized;then the second component, P2, is selected to maximizethe variance of the residual after P1 is removed, and soon. In a first pass, all figures of merit were weightedequally. Customer demands can be taken into account byintroducing appropriate weights.

PCA showed that the main source of variability, princi-pal component P1, accounts for 51% of the total varianceof the process. Correct identification of this component,

followed by appropriate corrective action, can signifi-cantly improve the manufacturing yield. The second andthe third components account for 21% and 13% of thetotal variance respectively.

Fig. 16: (Left) schematic diagram of a typical HEMT device showing the physical interpretations of P1 and P2, the dominant sources ofmanufacturing variability. (Right): bar chart showing the impact of each principal variance component on the measured figures of merit.

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The physical origin of P1 and P2 was identified byexamining details of their correlation with the DC figuresof merit. P1 has been linked to the concentration of Sidopants in the delta-doping layers of the device that is

produced during the molecular-beam epitaxial growth ofthe heterostructure. This identification was indepen-dently verified through measurements on gateless teststructures. P2 was related to gate-source distancevariations that are introduced in the electron-beamfabrication process of the gate.

The methodology that we have developed can be easilyimplemented in a manufacturing environment forcontinuous process yield diagnostics and improvement.The most important sources of manufacturing variationsare found using the Principal Component Analysis, withall the necessary statistical data obtained from simple DC

measurements on actual transistors no specialized teststructures were required. t

continued Arrays of Nanomagnets for HighDensity Information Storage

PersonnelM. Farhoud, J. M. Carter, J. M. Bae, and M. Hwang(C. Ross, H. I. Smith, and K. Youcef-Toumi)

Sponsorship3M Corporation

For several years, the areal density of informationstorage in thin-film hard disks has been increasingrapidly through improvements in magnetic materials,head design, signal processing, and mechanical design;

while prices have fallen with equal rapidity. This trendclearly cannot continue forever, and in fact will soonslow down unless a new paradigm for magnetic infor-mation storage is invoked. Following earlier work byS. Y. Chou, R. L. White, and others we have initiated aprogram to develop fabrication technologies for ultra-high-density information storage based on discretepillars of ferromagnetic materials, as illustrated in Figure17. In order to exceed the extrapolated informationdensity of conventional hard discs, the pillars must havediameters less than 100 nm and a spatial period less than200 nm (aerial density of 2.5 x 109 /cm2). In fact, our

100 nm

Fig. 17: Schematic of high density magnetic information storagebased on discrete sub-100 nm sized magnetic pillars.


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continued

continued

goal is to achieve aerial densities of 4 x 1010 /cm2,corresponding to a spatial period of 50 nm in the array ofmagnetic pillars. An important focus of our research is torealize such densities via techniques that are compatible

with low-cost manufacturing. The lithography candi-dates are therefore restricted to interferometric lithogra-phy, X-ray lithography, achromatic-interferometric

lithography stack

Si

ARC (400 nm)

plating base

SiO2(45 nm)

photoresist(200 nm)

351.1 nm radiation

holes in photoresist

electroplate Ni or Co

holesin ARC

RIE holes into ARC

lithography, and nanoimprint lithography. At presentour work is confined to the first, using a process illus-trated in Figure 18. The magnetic materials of choice atpresent are nickel and cobalt, both of which are electro-

plated into the holes produced in an AntiReflectionCoating (ARC) by the process illustrated in Figure 18.Figure 19 shows some results of electroplating cobalt.

Fig. 18: Schematic of the process currently used to fabricate 100 nm-scale magnetic pillars. Photoresist exposure is by interferometriclithography using the 351 nm line of the Ar ion laser. The antireflection coating (ARC) prevents backreflection from the substrate frominterfering with the lithography. Circular holes in the SiO2 and ARC are created by reactive-ion etching in CHF3 and O2, respectively.


17/2087

continued

Reading and writing of the information stored in themagnetic pillars appears to be the most formidableproblem of the proposed new paradigm. Because themagnetization is vertical, a scheme akin to the magnetic-

force microscope with multiple reading heads willpresumably be required. Interferometric lithographycannot produce nanopillar arrays in a cylindrically-symmetric configuration compatible with rotating discreading and writing; it can provide only a Cartesiangeometrical arrangement. Accordingly, if interferometricis the lithography of choice, entirely new apparatus forreading and writing must be developed, presumablyutilizing micromechanical schemes, such as electrostaticmotors that move exclusively in X and Y. If, on the otherhand, a rotating scheme is desired, x-ray nanolitho-graphy or nanoimprint lithography will be used toproduce the nanomagnet arrays. Both of these schemes

are compatible with 25 - 50 nm pillar dimensions. Boththe x-ray mask and the nanoimprint master would haveto be made by scanning electron beam lithography.

200 nm

ARC Cobalt

An important focus of our research will be the basicstudy of how discrete nanoscale magnets switch direc-tion of magnetization. It has been predicted theoreticallythat below a certain size, which depends on the magnetic

properties of the material, the magnetization will switchcoherently. This as well as other mechanisms of switch-ing will be studied. t

Fig. 19: Scanning-electron micrograph of cobalt pillars electroplatedto a height of 200 nm still embedded in ARC. The spatial period is200 nm.


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Integrated Si-MOSFET/FEA

PersonnelC.-Y. Hong(A. I. Akinwande)

SponsorshipDARPA

The Field Emission Display (FED) is essentially a thin flatCRT. Unlike a CRT which uses a raster scanned singleelectron source to generate images on a phosphor screen,the FED generates images by using a two dimensional

array of matrix addressed micro-electron sources whichare row-scanned and proximity-focused on a phosphorscreen. Field emitter arrays operate on the basis ofelectron tunneling into vacuum when a high electric fieldis applied to the field emitter tip. The device perfor-mance (current density, operating voltage, beam spread,temporal and spatial uniformity) are essentially deter-mined by the characteristics of the energy barrier formedbetween the emitter (metal or semiconductor) andvacuum. Silicon FEAs have recently been fabricated inour laboratory (see report by Dr. Han Kim) using metalor poly-Si gates. Si FEAs have good emission character-istics and reliability similar to Mo micro-tips. In addi-

tion, they are easy to fabricate using silicon micro-fabrication technology. However, Si FEAs also havetemporal and spatial current uniformity problems just

like their Mo-tip counterparts. The problems stem fromthe inherent nature of the electron emission processelectron tunneling through a barrier. Electrons tunnelout of the emitter when the barrier is made narrow by

the application of a gate voltage and the enhancement ofthe tip electric field by using a very sharp tip. Theemission current varies exponentially with the appliedvoltage. Spatial and temporal non-uniformity in theemission current result when small changes occur in thebarrier height or width occurs. Traditionally, currentnon-uniformity and stability have been addressed byadding a series resistor to determine the operating pointof the device. At a fixed current, the operating voltagebecomes more uniform as the value of the series resistoris increased. In the limit, the best series element forcurrent stabilization is a current source. An effectiveway to control the field emission current is to add an n-

channel MOSFET in series with the FEA. This is rela-tively easy if the FEA is fabricated on a Si substrate.

Fig. 20: The integrated MOSFET / FEA device structure.

continued


19/2089

Other important benefits of integrating Si FEAs with Si n-MOSFET is the ability to (I) drive displays using inte-grated MOSFET, (ii) implement current drive schemesusing the Si-MOSFET and (iii) explore new display

architectures through the addition of sophisticated signalprocessing circuits to the display.

The objective of this project is to demonstrate the integra-tion of Si-MOSFET technology with S-FEAs. The deviceswe are fabricating have a relatively simple structure inwhich the n-Si FEA tip is also the drain of the n-MOSFET.The MOSFET has very light doping at the drain toimprove its breakdown voltage. This is necessarybecause the MOSFET must be able to withstand the gatevoltage of a field emitter. The proposed Si MOSFETstructure is shown in Figure 20. t

Low-Power Row and Column Driversfor Field Emission Displays

PersonnelA. Ranadive(A. I. Akinwande)

SponsorshipDARPA and NSF Career Award

The Field Emission Display (FED) is being widely studiedas a viable alternative to existing flat panel technologies.The FED is an emissive display that has inherent advan-tages over the existing flat panel displays, higher lumi-

nous efficiency, wide viewing angle, low volume andhigh performance. One aspect of field emission displaysthat has not received very much attention is the displayelectronics. Field emission displays, like most otherdisplays, are composed of a matrix of pixels. The displayelectronics are responsible for addressing and controllingthese pixels based upon the data that needs to be dis-played. To perform this crucial addressing function,modern flat panel display electronics can consume up toone-third of the power dissipation in the display. Sincethe trend with portable flat panel displays is to minimizethe power consumption, the power dissipation in thedisplay electronics is therefore an important aspect to

investigate.

The objective of this research project is to design low-power row and column display drivers based upon thespecific requirements of the FED. There were severaldesign requirements for the FED row and columndrivers. Functionality requirements included the abilityto accommodate eight-bit gray scale (256 gray levels), theability to introduce column data for a monochrome VGA(640 x 480 resolution) display with 75 Hz refresh rate, andthe ability to scan rows and assert data upon the appro-priate columns simultaneously. The area requirementwas to conform to a pixel pitch size of approximately 200m. The row and column drivers are intended to drive ahighly capacitive electrode at high voltages. Finally, allof the design must be done with the intention of minimizing the power consumption of the device.

Several approaches were considered to implement thegray scale requirements of the FED, including amplitudemodulation and pulse width modulation. Althoughsimple amplitude modulation would have reduced theoverall power consumption the best, the performance of

continue

continued


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continued

the FED would suffer at low voltage values due to lack ofuniformity. Thus, the decision to use pulse widthmodulation to achieve gray scale voltages was made.The challenge was then to use low-power techniques to

reduce the amount of power consumption with pulsewidth modulation.

One major technique employed to reduce the powerconsumption of the row and column drivers was half-power point switching. Pulse width modulation man-dates that a consistent voltage level is applied for aportion of the maximum possible time corresponding tothe data value desired. For example, for the eight-bit(256) gray scale requirement, the row time is multiplexedinto 256 intervals. If we wanted to assert gray level 128,

then we would apply a consistent voltage to the outputfor half of the row time. If we wanted to assert gray level64, then we would apply a voltage to the output for one-fourth of the row time. Half-power point switching

shifts the active period of every odd row time to elimi-nate one transition every two cycles. Thus the number oftransitions is reduced by 50%, and so is the dynamicpower dissipation. The essence of half-power pointswitching is shown in Figure 21.

A second technique being considered to reduce powerconsumption involves charge conservation, or energyrecovery. We will utilize a large storage capacitor thatnaturally maintains a DC bias point that is locatedmidway between the low and high voltage transitions.At the beginning of a transition, the output of the row (orcolumn) driver is momentarily isolated from the elec-

trode and is connected to the large storage capacitor.The driver output quickly decays to the potential of thestorage capacitor node, which is the half-voltage swingbias point. After this brief configuration, the driveroutput is again connected to the pixel electrode and thendriven to its final voltage value. The benefit of thischarge-sharing configuration is that the effective voltageswing is reduced by 50%. The dynamic power dissipa-tion is therefore also reduced by 50% sincePdyn = Pt (CLVswingVDDfclk). In the preceding equation,pt is the probability that a power-consuming transitionoccurs (the activity factor),CL is the loading capacitance,Vswing

is the voltage swing between high and low, VDD

isthe power supply voltage, andfclk is the clock frequency.We will conduct a feasibility study to determine what thecosts and benefits of this charge conservation method

would be. t

Fig. 21: Half Power Point Switching

electronic devices in mtl annual report 1998

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