electronic devices and circuits 2-1 n-d-12

7/29/2019 Electronic Devices and Circuits 2-1 N-D-12

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QP.8 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

B.Tech. II-Year I-Sem. ( JNTU-Hyderabad )

The low frequency model for CE amplifier with coupling capacitor is as shown in figure (1).

Vi hfeIb

CC

BIb

+

+VS

RS

E

RiR1||R2RL

C

Vo

+

Vi hfeIb

CC

BIb

+

+VS

RS

E

RiR1||R2RL

C

Vo

+

Figure (1): Low Frequency Model for CE Amplifier with Coupling Capacitor

For large values ofCE, the low frequency gain experiences no reduction in its value.The lower 3-dB frequency is given as,

fL

=CiS CRR )(2

1

+... (1)

Where,

CC

= Coupling capacitor

R'i=R

1||R

2||R

1

Ri=

++ .consideredisresistanceseriesscapacitor'when;)1(capacitorbypassemitteridealfor;

CEfeie

ie

Rhh

h

Therefore, to achieve good low frequency response the value ofCC

must be large.

Effect of Bypass Capacitor on Low Frequency Response

CE

is the emitter bypass capacitor which causes frequency response of an amplifier to break at a cut-off frequency,

fc

and prevents the reduction of A.C gain by passing A.C signal current through it.

IfCE

would not have been there, A.C signal current would flow intoRE

making A.C signal gainless.

The gain falls at low frequency region because of coupling capacitorsC1, C

2,C

3... and emitter bypass capacitor C

E1,

CE2

, CE3

, CE

.

~

Ro

CE~

Ro

CE

f

Am

Am

0.707

f

Am

Am

0.707

Figure (2): Frequency Response


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QP.11Electronic Devices and Circuits (Nov./Dec.-2012, R09) JNTU-Hyderabad

( JNTU-Hyderabad ) B.Tech. II-Year I-Sem.

(b) Explain the procedure to obtain the small-signal equivalent circuit of a field effect transistorwith necessary equations. Also draw the small-signal model.

Answer : Nov./Dec.-12, (R09), Q6(b)

The circuit diagram of N-channel JFET is shown in figure (1).

VDS

+ID

IS

VDD

+

D

+

VGS

VGG

+

IG

G

S

VDS

+ID

IS

VDD

+

D

+

VGS

VGG

+

IG

G

S

Figure (1): Circuit Diagram of N-channel JFET

Small signal equivalent circuit of FET can be drawn in two models. The two models are current source and voltage

source. These models are analysed in common source configuration, as shown in figure (2) and figure (3) respectively.

Vds

rd

+

G

Vgs

S

gm

Vgs

id D

+

Vds

rd

+

G

Vgs

S

gm

Vgs

id D

+

Figure (2): Small Signal Current Source Model of FET

Vds

rd

+

G

Vgs

S

Vgs

id D

+

+

V

ds

rd

+

G

Vgs

S

Vgs

id D

+

+

Figure (3): Small Signal Voltage Source Model of FET


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The drain current (id) of FET is a function of gate to source voltage (

gs) and drain to source voltage (

ds).

Considering varying currents and voltages for FET, id

is given as,

iD

=f(gs

,ds

) ... (1)

The drain current (id) is dependent on drain and gate voltages. Any changes in drain and gate voltages also changes

drain current. The corresponding change in drain current due to variations in gate and drain voltages is obtained by

expanding equation (1) using Taylors series.

id=

dsVgs

di

gs

+

gsVds

di

ds

... (2)

In the small signal notation, the incremental values are A.C quantities.

So,

id

= id,

gs=

gsand

ds=

ds

The equation (2) can be re-written as,

id

= gm

gs

+dr

1

ds... (3)

Where,

gm

= Mutual conductance or transconductance

rd

= Drain to source resistance.

The mutual conductance of FET is defined as,

gm

=

dsVgs

di

dsV

gs

di

=

dsVgs

di

dsV

gs

dm

ig

=

The drain to source (output) resistance of FET can be defined as,

rd

=

gsVd

ds

i

gsV

d

ds

i

=

gsVd

ds

i

gsV

d

dsd

ir

=

Amplification factor of FET can be defined as,

=DI

gs

ds

DI

gs

ds

=

0=

digs

ds

0=

=di

gs

ds


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A relation between , rd

and gm

can be established

by making the drain current id

= 0 in equation (3).

id = gmgs +dr1 ds

0 = gm

gs

+dr

1

ds

gm

gs=

dr

1

ds

gs

ds

= gm

rd

dmrg=

=

=0digs

dsQ

Q7. (a) What are the requirements of FETbiasing? Verify these requirements insource self-bias circuit.

Answer : Nov./Dec.-12, (R09), Q7(a)

Requirements of FET Biasing

The process of obtaining desired Q-point by giving

proper supply voltages and resistances is known as biasing.

The set of D.C voltage VCEQ and currentICQ are established

by properly choosing supply voltages and resistances,

which are responsible to produce distortion-free output by

operating transistor in active region.

Transistors have to be properly biased in order to

function as amplification stage. A transistor is biased by

setting the amount of D.C current that flows in the tube

when there is no signal present at the transistor base. This

D.C bias current can be set in a number of ways. The bias

point determines several things about a transistor

amplification stage. It determines the power output, amount

of distortion, the size of input signal that can be applied

before the output signal clips (head room), efficiency of thestage, gain of the stage, noise of the stage and class of

operation (class A, AB etc.,). The proper bias point is a

trade-off between all of these factors and selecting the

optimum bias point can sometimes be difficult, and it will

vary depending on the amplification stage requirements.

Source Self Bias (Self bias)

The self-bias scheme is a biasing technique mostly

used in FETS. This configuration provides more assistance

in stabilizing the operating point even for the changes in

FET parameters.

The self-bias configuration of N-channel JFET is

shown in figure (1).

A.C input

signalCi

RG RS

CC

A.C output

signal

RD

VDD

A.C input

signalCi

RG RS

CC

A.C output

signal

RD

VDD

Figure (1)

Analysis of the Self-bias Circuit

The D.C equivalent of the self-bias circuit is shown

in figure (2).

+

+

RS IS = IDRGIG = 0

VGS

VDS

RD ID

VDD

+

+

RS IS = IDRGIG = 0

VGS

VDS

RD ID

VDD

Figure (2)

Applying Kirchoffs voltage law at the input side of

the circuit, we get,

VGSI

DR

SR

GIG= 0

VGS

= IDR

S(QIG = 0) ... (1)

Voltage at the source terminal is given by,

VS

= VG

VGS

... (2)

VS

= VGS

(QVG = 0)

VS

= VGS

=IDR

S... (3)

(Q From equation (1))


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Then, the expression for drain current (ID

) of a JFET

is given by,

ID

=IDSS

2

1

P

GS

V

V

From equation (1), we get,

ID

=IDSS

2

1

+

P

SD

V

RI... (4)

By applying Kirchoffs voltage law at the output side

of the circuit shown in figure (2), we get,

VDD

IDR

D V

DSI

SR

S= 0

VDS

= VDD

ID

(RD

+RS) [QIS=ID] ... (5)

The graphical analysis can be obtained as shown in

figure (3).

VGS

(V) 2

RI SDSS VGSQ

IDQ

2

IDSS

ID(mA)

VGS

(V) 2

RI SDSS VGSQ

IDQ

2

IDSS

ID(mA)

Figure (3)

The operating point can be determined by drawing a

straight-line corresponds to equation (3) (i.e., VGS

= IDR

S)

on the transfer characteristics curve of JFET.

(b) A common source FET amplifier circuit

shown in figure with unbypassed Rs has

the following circuit parameters:

Rd = 15 k, RS = 2.5 k, Rg = 1 M, rd = 100 k,

IDSS = 10 mA, VP = 5 V and VDD = 20 V.

Calculate gm and AV.

Rg Rs

Rd

VDD

V0

+

Vi Rg Rs

Rd

VDD

V0

+

Vi

Figure

Nov./Dec.-12, (R09), Q7(b)

Answer :

Given that,

For a common source FET amplifier,R

d= 15 k

Rs= 2.5 k

Rg= 1M

rd

= 100 k

IDSS

= 10 mA

Vp

= 5 V

VDD

= 20 V

gm

= ?

Av= ?

Then, the expression for transconductance of acommon source FET amplifier is given by,

gm

= DSSDp

IIV ||

2... (1)

Where,

ID

=d

DD

R

V

ID

= 31015

20

ID

= 1.333 103

On substituting the value of ID

in equation (1), we

get,

gm

= )1010)(10333.1(5

2 33

= )10651.3(5

2 3

= 1.46 103

mho1046.1 3= mg

And the expression for the voltage gain is given by,

dd

dv

rR

RA

+

= ... (2)

Where,

= rd.g

m

= 100 103 1.46 103

= 146


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On substituting the value of in equation (2), weget,

Av=

)10100()1015(1015146

33

3

+

= 115000

2190000

= 19.043

19.043vA =

Q8. (a) Draw the structure and two-transistormodel of SCR, explain various methodsof triggering an SCR.

Answer : Nov./Dec.-12, (R09), Q8(a)

For answer refer Unit-VIII, Q5.

The triggering of SCR mainly classified into five

methods, they are,

1. Thermal triggering

2. Radiation triggering

3. Voltage triggering

4. dv/dt triggering

5. Gate triggering.

1. Thermal Triggering

In this triggering method, when the input voltagelevel is very close to the breakdown voltage level, the SCR

gets turned ON with increase in temperature.

2. Radiation Triggering

The triggering method in which SCR is triggered by

the bombarding of photons, which forms an electron-hole

pair is referred as Radiation triggering.

The SCR which is turned ON by this triggering

method is referred as Light Activated SCR (LASCR).

3. Voltage Triggering

In this triggering method, the increase in forward

biased voltage level results in accumulation of electronsand holes at the reversed biased junction which in turn

causes increase in blocking current. Therefore, SCR is turned

ON.

4. dv/dt Triggering

In this triggering method, SCR is turned ON when

the rate of rise of voltage increases above the critical rate of

rise of voltage.

5. Gate Triggering

This is one of the most easiest, simplest and useful

triggering technique of SCR.

The following are the important points to be

considered during the design of gate control circuit.

(a) An appropriate gate signal should be applied

to trigger SCR, when it is in forward biased

condition.

(b) Once the SCR is turned ON, gate signal should

be removed for reducing losses and higher

junction temperatures.

(c) During the reverse biased condition of SCR,

gate signal should not be applied.

(d) The characteristics of SCR can be improved by

applying negative voltage between gate and

cathode during OFF state of SCR.

There are three methods of triggering SCR by usinggate control, they are,

By D.C gate signal

By A.C gate signal

By pulsed gate signal.

By D.C Gate Signal

In this technique, SCR is triggered by applying D.C

gate signal of appropriate polarity and magnitude

between the gate and cathode.

By A.C Gate Signal

In this technique, SCR is triggered by applying A.C

gate signal between gate and cathode.

By Pulsed Gate Signal

By applying pulsed gate signal between the gate and

cathode SCR is triggered.

This technique has less losses when compare to other

techniques.

(b) With neat sketches, explain the principleof operation of Schottky barrier diode.

Answer :Nov./Dec.-12, (R09), Q8(b)

For answer refer Unit-VIII, Q3.

electronic devices and circuits 2-1 n-d-12

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