electromigration simulation flow for chip-scale parametric ......© 2010 mentor graphics corp....

Electromigration Simulation Flow For Chip-Scale Parametric Failure Analysis

Valeriy Sukharev1, Jun-Ho Choy1, Armen Kteyan2, and Xin Huang3

1Mentor Graphics, Fremont, CA, USA

2Mentor Graphics, Armenia

3UCR, Riverside, CA, USA

© 2010 Mentor Graphics Corp.

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Outline

• Introduction and motivations

• A role of residual stress and temperature in EM-induced degradation

• Methodology of across-interconnect residual stress assessment

• Methodology of across-interconnect temperature assessment

• Voiding-induced IR-drop degradation – parametric failure

• Characterization techniques for models/methodology validation

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Electromigration Material depletion and accumulation occurring at the sites of atomic flux

divergence results the localized tensile and compressive stresses.

Resulting stress gradient creates a backflow atomic flux.

Immortality: the interconnect segment will be immortal, if the electron-wind and back-stress forces balance each other before the critical stresses needed for void nucleation or metal extrusion are developed.

je

3


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General Physical Model

dxxx

W

H x

y

z

ejJa(x)

Ja(x+dx)

If atom flux diverges somewhere inside metal line then accumulation or depletion of atoms is happening there:

0

A

A Jt

N

Fast diffusion

Slow diffusion Slow diffusion

x

jeZ

xt

HydHyd

Evolution of the hydrostatic stress (a) along the metal line loaded with DC current, and at the cathode end of line, (b) j = 5x109A/m2, T = 400K.

je

Anode area

je

Cathode area

crit

crit

nuct

Solution of Korhonen’s equation: Condition for growing void formation: Nucleation time for stable, growing void:

0222 exp

21cos4,

n nn

nres

Ltmm

LxmLx

jeZtx

0222 exp

21cos4

n nucnn

nrescrit

Ltmm

LxmLx

jeZ

critres

Tk

jLeZEE

Bnuc jLeZ

jLeZ

eB

Tk

D

Lt B

TVDV

2

2ln2

2

0

2*

4


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Black’s equation based MTTF

jaccel

jaccel

EM accelerated test: Taccel and jaccel • TTF averaged with the accepted distribution function provides mean time to failure (MTTF).

• A set of calculated MTTF obtained for different Taccel and jaccel is used for extraction of the current density exponent n and apparent activation energy E used in the Black’s equation:

• Assuming an “universal” character of the extracted n and E, the MTTF at the used conditions is:

kT

E

j

AMTTF

nexp

acceluse

n

useaccelacceluseTTk

EjjMTTFMTTF

11exp

Experiments demonstrates that n and E by themselves are the functions of both j and T

M. Hauschildt, C. Hennesthal, G. Talut, et al. (GF & Fraunhofer), 2C.1.1, IRPS 2013

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EM Assessment – PROBLEM!

• Stress and temperature dependency of the current density exponent, • Current density and temperature dependency of the activation energy • Across-interconnect temperature and residual stress variation ALL THESE FACTORS MAKE QUESTIONABLE USING BLACK EQUATION and BLECH LIMIT (CRITICAL PRODUCT) FOR ACCURATE EM ASSESSMENT!

kT

TjE

j

rAt

Tn

resnuc

,exp

),(

eZ

TrLj resEM

crit

,

resid

crit

Hydro

static

stre

ss

EM

Interconnect line, arc-length

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EM Assessment requires

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• Current density assessment • Temperature assessment • Residual stress assessment


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STRESS ASSESSMENT

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3D TSS (Through Si Stacking) Technology

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~20 um

~100 um

~20 um

DIE 1 : Si Substrate

Backside Insulator

TS

VTS

V

Device

M1

M2

Mn

FC Bump

uBump

ILD

DIE 2 Substrate

DIE 1 BEOL

Device

DIE 2 BEOL

~5

0 u

m

~1

00

um

~5 um

TSV BRDL F2B F2B

Die 1

Die 2

uBump

9

Die Integration Technology

— using Through Si Vias

— electrical connection from

front to back (on die or

interposer)

Value Proposition

— Small form factor (in X-Y &Z)

— Improved Performance

— Heterogeneous Integration

Typical Implementation — e.g. WIO Memory-on-Logic

– stacking orientation: F2B – TSV via diameter ~ 5u – wafer thickness ~ 50

— e.g. Die on (Active) Interposer – stacking orientation: F2F – TSV via diameter ~ 10u – wafer thickness ~ 100u


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Multiscale methodology for calculation of device-to-device variation of stress: Stress Exchange Format

Package-scale simulation (FEA) Input: geometry; material properties; smeared mechanical properties for RDLs, Silicon/TSV bulk, interconnect.

Output: field of displacement components on the die faces.

Die-scale simulation (FEA) Input: geometry; field of displacements on the die faces; coordinate-dependent mechanical properties for RDLs, Silicon/TSV bulk, interconnect.

Output: Distribution of the strain components across device layer.

Layout-scale with feature-scale resolution : Input: GDS. Output: distribution of the stress components across interconnect metal layer.

Package scale

Die scale

Feature scale

Package simulations

(FEA)

TSV induced stress

(compact model)

Bump effect

(compact model)

Design (GDSII, OASIS);

Design tech file

Composite interconnect

layers (compact model)

Transistors layout effect

(compact model)

CPI stress/strain

(FEA)

Stress and strain

components (per transistor);

mobility shift

Package tech file

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Effective mechanical properties of BEoL, BRDL interconnects and Si/TSV bulk layer

Theory of the mechanical properties of anisotropic composites is employed.

Required input: (a) Thermo-mechanical properties of each material – metal, dielectric: CTE, Young’s moduli, Poisson factors; (b) fraction of dispersed phase; (c) routing direction of the metal layer.

For each bin of each layer of interconnect, depending on routing direction: for example the Young’s modulus:

ji

MD

ji

MM

ji EEE ,,,

|| 1

ji

MM

ji

MD

DMji

EE

EEE

,,

,

1

bin {i,j} layer l

z

x

y

Young’s modulus components for M1 layer

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Supported Compact Models

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Stress component distributions obtained with: “smeared” (dashed line) and non-uniform (solid line) interconnects.

1. Package-scale: Warpage-Induced Stress

2. Compact Model for Bump-Induced Displacements

3. Effect of Non-Uniform Interconnect

4. Compact Model for TSV-Induced Stress: Based on: S. Ryu, K. Lu, X., et Al., , “Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects”, IEEE TDMR, VOL. 11, NO. 1, (2011) pp. 35-43

D

uEEP

W

yx

ubyx

)(

)( ~

T

H

uEP ub

W

zbz ~

Tier2 die edges


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Residual stress in on-chip interconnect

TREE 41

TREE 37

0 30 60 90

120 150 180

0 50 100 150 200

MP

a

M1 tree=37 VDD

TREE 1

296

0 30 60 90

120 150 180

0 50 100 150 200

MP

a

M3 tree=1296 VDD

Interconnect tree is a elemental EM reliability unit representing a continuously connected, highly conductive metal (Cu) lines within one layer of metallization, terminated by diffusion barriers.

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TEMPERATURE ASSESSMENT

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Major components

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kx

M

ky

kz

Effective thermal properties of a die

MGC’s effective thermal properties extractor. - Each interconnect layer is considered as a composite: a mixture of metal fibers

included in a dielectric matrix. - Calculates the effective thermal conductivity (ki, i=x,y,z), specific heat of each interconnect layer as a function of local metal density (M).

• Lateral components Kx,y inside each metal layer are determined by a routing direction:

- Parallel to the routing direction:

- Normal to the routing direction:

- A vertical component:

Thermal Netlist Builder. - A die is represented by a 3D array of cuboidal thermal cells. Each cell contains a

thermal node, and is characterized by local effective thermal properties(Rth, Cth). - The array transforms into a thermal netlist.

SPICE simulator. - Calculates transistor power consumption.

- Solves for temperature for each thermal node.

ILDMMMII kkk 1

2/1/1

MILDMILD

MILD

kkkkk

ILDMMMZ kkk 1


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From effective thermal props to thermal netlist

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Construct an array of cuboidal cells of dimension, LxLxt : “L” is user-supplied binSize.

For each cell, MGC’s engine uses Calibre to extract local metal density, and calculates effective thermal properties.

Thermal netlist builder transforms effective thermal properties into Rth and Cth.

The array transforms into a thermal netlist.

Consideration on boundaries - Fixed T with V source & R=0; Insulation with large R.

Cth

L

L tM6

tV5

tM5

.

.

.

.

.

.

Cell i: Mi, kxi,kyi,kzi,Si

x // east

y // north z // top

6,

6,

,/

6,

,/2

6

,

./

2/1;

2/1;

2/1

Miicell

Mix

iwesteast

Miy

isouthnorthM

iz

ibottomtop

tLLSC

Lt

L

kR

Lt

L

kR

L

t

kR

Design Power map Temperature across M1


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Flow

STEP1: Obtain thermal properties of each bin • Run mPower to obtain power dissipation map. • Run MGC thermal properties extractor to obtain per layer effective thermal properties of each layer. • Run a script to obtain per bin thermal properties.

STEP2: Generate thermal netlist • Input :

• Thermal properties of each bin (rawBin.txt) - Location - Thermal conductance in 6 directions - Power consumption - Boundary condition - etc.

• Chip size, bin size, #layers

• Output: • Thermal netlist (.spef) • Control file (Tamb (V), Power Sources (Is))

STEP3: PERC calcd solver (static analysis): Obtain temperature distribution • Input:

• Thermal netlist, control file

• Output: • temperature distribution -> Used in EM analysis

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INTERCONNECT SCALE EM MODELING

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Chip-scale EM assessment

Interconnect functionality

• interconnectivity for signal propagation -bidirectional pulsed currents

• voltage delivery -unidirectional current - power grids, more susceptible to EM effect

Traditional segment-based EM assessment

• single segment based stress analysis - assume individual segment is confined by diffusion barriers - however, in power grids, atoms can diffuse in the interconnect tree, stress redistribution

• EM induced failure rate of the individual segment

EM induced degradation in power grids • high level of redundancy • Failure: loss of performance, parametric failure

- cannot deliver needed voltage to any point of the circuitry

New methodology for EM assessment: • IR drop based assessment • physics based models for void initiation and evolution

Interconnect tree

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Follow Carl Thompson we consider interconnect trees, which are the continuously connected conductor metals within one layer of metallization confined by the diffusion barrier liners, as segments where EM assessment should be done.

Interconnect tree; sidewalls and bottoms of the lines and exit vias are covered by metal diffusion liners (Ta/TaN).

Dielectric (SiN) diffusion barrier layers covering tops of the metal lines.

Electron flow inlets. Electron flow exits.

Interconnect tree

20 C.V. Thompson, 11th International workshop on stress-induced phenomena in metallization, AIP, 2005


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Interconnect segment vs. wire

Current density Hydrostatic stress

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Closed-form analytical solution for stress evolution in the multi-branched interconnect tree

j1 j2

j3

T-shaped interconnect tree with shown directions of the electron flows.

Evolution of the stress distribution along the segment of the shown T-shaped tree; (a) line 1, (b) line 2, and (c) line 3.

(a) (b) (c)

If we disassemble these brunches a standard stress evolution will take place in each of them:

22

V. Sukharev, X. Huang, H.-B. Chen, and S. X.-D. Tan, Proc. ACCAD, October 2014.


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Voiding

When void is nucleated the stress at the void surface is zero. The solution of the stress kinetics equation with the zero-flux condition at the downstream (anode) end of the line is [J. He and Z. Suo, AIP Conf. Proceedings, vol. 741, 2004]:

tn

L

xn

nL

xjLeZtx

n

n 2

022 2

12exp

2

12sin

12

18, Here,

DB

TkLL B

22

Once void is nucleated and the stress field is solved, the void volume is calculated from the volume of atoms drifted into the line:

tn

nB

AjLeZdx

BAdxN

BAdxNAV

n

nLL

A

L

PL

2

023

2

0002

12exp

12

1321

2

There are two limiting cases for volume void: 1. Short time; stress in the line is small, so

jeZTk

Dr

B

and

Tk

jDAteZAtV

B

2. Steady state was reached; the atomic flux vanishes, void volume is saturated:

jxeZ

x

and B

AjLeZdx

BAV

L

sat

2

2

0

nuctt

Void Atoms from area occupied by void

Je electron flow

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Void

Atoms from area occupied by void Je electron flow

h H

W

Cu

Ta

HWWHh

tV

WHhtt

HWWHhtttR

HW

ttR

hW

ttR

hH

ttR

RRRR

RRR

TavoidTa

nuc

CuTa

nuc

nuc

Ta

Void

Cu

nuc

Ta

bottomvoid

Ta

nuc

Ta

wallvoid

Ta

bottomvoid

Ta

wallvoid

Ta

wallvoid

Ta

Void

Ta

Void

Cu

Void

Ta

222

;;

1111

__

___

Once V(t) is known the kinetics of line resistance can be easily calculated. For a void volume at an instance in time t we have: Or, when current density depends on time:

kT

jDeZ HWtttV nucvoid

For the corresponding change in the line resistance we can write:

t

t

void

nuc

dttjkT

DeZHWtV

Void growth-induced line resistance change

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• Assume (just for a moment) that the void less steady state was achieved in the tree.

• Consider the redistribution of the atoms between sub-segments due to unblocked sub-segment ends:

For the steady state:

7

1

023i

ij

ijijkT

E

iTi L

LjeZe

RBZS

V

If , this sub-segment is suspicious to EM failure.

Example of an interconnect tree

jmn is the density of electron flow

(opposite to the current direction).

criti

Distribution of the steady state hydrostatic stress along the considered tree

• Previously, we use uniform temperature distribution:

The shortest void nucleation time is characterized by the biggest steady state stress ,

j23

j34

j54

j46

j68

j76

j13

1

3

2

5

4

7

6

8

• With temperature variation: Void nucleation time is

affected by both T and hydrostatic stress. Consider both factors to find the first nucleated void (min{tnuc

i})

Steady state distribution of the hydrostatic stress inside interconnect tree in void-less regime

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t1

- Nucleated void - Growing void

t2 t3 t4

- Saturated void

EM-induced supply voltage degradation

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EM effect is sensitive to temperature

- TTF exponentially relates to temperature

(the same as Black’s equation)

Reducing chip temperature/ temperature gradient could extend TTF

EM Assessment Results in IBM Benchmarks

12 14 16 18 20 22 24 26 281.62

1.625

1.63

1.635

1.64

1.645

1.65

1.655

Simulation Time (yrs)

Nod

e V

oltag

e (

V)

Reaches minimum nucleationtime, begin to degradate

Reaches thresholdvoltage, TTF

TABLE: COMPARISON OF POWER GRID MTTF USING BLACK’S EQUATION AND PROPOSED MODEL

Both Black’s equation based series and Mesh models lead to pessimistic predictions

Voltage at the first failed node over time

In this work, the first failure is most likely to happen at the nodes where the initial hydrostatic stress is large

(b)

360 364 368 372 376 380

20

40

60

80

100

Temperature (K)

Tim

e to

Failu

re (

yrs

)

360 370 3802

4

6

Temperature (K)

ln(T

TF

,(ye

ar)

)

(a) Voltage drop (V) distribution and (b) Initial steady state hydrostatic stress (Pa)distribution predicted by initial current density in IBMPG2.

(a)

27

2

4

6

8

10

12

14

250 350 450 550

thermal stress(MPa)

Tim

e t

o F

ailu

re (

yrs

)

X. Huang, T. Yu, V. Sukharev, and S. X.-D. Tan, Proc. IEEE/ACM Design Automation Conference (DAC'14), San Francisco, June, 2014.


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EXAMPLE OF IR-DROP EM ASSESSMENT

CHIP-SCALE EM ASSESSMENT CONSIDERING THE IMPACT OF TEMPERATURE AND CPI STRESS VARIATIONS

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Layout

Design: 7-metal layer 32nm Dimension:184um ×184um

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power net

Initial current density and initial IR-drop -power net, M1 layer

power net

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suspicious to EM failure

σcrit = 500Mpa

Initial hydrostatic stress -power net, M1 layer

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Temperature distribution

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16300

320

340

360

380

400

420temperature variation

layer number

tem

pra

ture

(K)

average T of the layer

max T in the layer

min T in the layer

bottom top

1 2

Metal 1 layer

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EM induced IR drop change - power net

Initial IR drop distribution

Final IR drop distribution (at lifetimeth)

Significant IR drop changes in M1 layer

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Voids mainly locate in M1 layer, some voids locate in M3 layer

Branches with voids - power net


Chip fails when the maximum IR drop > threshold level

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CALIBRATION/VALIDATION

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How to calibrate/validate verification tools?

• Both types of tools predicting the effect of CPI on chip performance and chip reliability need as inputs: Measured foundry and process dependent thermal-mechanical properties of

the involved materials. Calibrated compact models employed for calculation of the stresses and

temperature across a device layer and across the whole chip. Calibrated models for calculating effective thermal-mechanical properties of all

composite layers (BEoL and RDL interconnects, underfill with C4 and u-bumps, silicon bulk with TSVs, etc.).

• Both types of tools need to be validated by a direct comparison between the predicted characteristics and measured: Comparing the measured characteristics of individual transistors and predicted

by verification tools is a validation of the CPI effect on chip performance. What kind of test-structures should be used to validate the effect of

CPI on chip reliability (EM as an example)?

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Proof Electrical vs. Mechanical

U2U Glacier Project 37

H-Bar –TEM Lamella

Distance to TSV

After FIB processing Before FIB processing Strain distribution in lamella ( after FIB, before FIB)

Reconstructive FEA simulation

TEM CBED measurement of strain

MECHANICAL DOMAIN

A

C B

ELECTRICAL DOMAIN

0

1

2

3

4

5

6

7

8

0 2 4 6

de

lta

_Id

, %

Distance to TSV, um

Measured

Simulated

SPICE

z

I

zy

I

yx

I

x

simul II

2cos

421 2

2

r

DE TSV

Si

thSiyx

Calibrating th :

Good fit between simulated and measured electrical characteristics of transistors located at different distances from TSV allows to calibrate the developed tool with relatively easy accessible electrical data.


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Validation with the Foundry calibrated Model

Test-chip segment

y = 0.9504x + 0.1289 R² = 0.9492

-2

0

2

4

6

8

10

-5 0 5 10

Pre

dic

tio

n

Fab data

n-ch Id_lin

y = 0.8711x + 0.2115 R² = 0.8514

-5

0

5

10

15

-5 0 5 10 15

Pre

dic

tio

n

Fab data

p-ch Id_lin

y = 0.941x - 0.0011 R² = 0.9235 -0.08

-0.06

-0.04

-0.02

0

0.02

-0.08 -0.06 -0.04 -0.02 0 0.02

Pre

dic

tio

n

Fab data

n-ch Vt

y = 0.9001x - 0.0036 R² = 0.8881

-0.07

-0.06

-0.05

-0.04

-0.03

-0.02

-0.01

0

-0.08 -0.06 -0.04 -0.02 0

Pre

dic

tio

n

Fab data

p-ch Vt

Calibration was performed on ~100 gates Prediction was made for all (~4000) gates

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Die Corner Array: Test-chip 28nm node

39 39

Die corner

1

1

1

1

FC bumps

Device #i Device #j

Schematics of the test structures used for model calibration: die corner


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Conclusions

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• A novel methodology was developed for full-chip power/ground nets redundancy-aware EM assessment based on IR-drop analysis.

• Physics-based model was developed and implemented in

the flow, for temperature- and residual stress-aware void nucleation and growth.

• A developed technique for calculating hydrostatic stress

distribution inside a multi branch interconnect tree allows to avoid over optimistic prediction of the time to failure made with the Blech-Black analysis of individual branches of interconnect segment.


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THANK YOU

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electromigration simulation flow for chip-scale parametric ......© 2010 mentor graphics corp....

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