ekt 221/4 digital electronics ii registers, micro-operations and implementations - part2
TRANSCRIPT
EKT 221/4 DIGITAL
ELECTRONICS II
Registers, Micro-operations and
Implementations -Part2
HIGH LEVEL LANGUAGEExample : C+, VB, JAVA
ASSEMBLY LANGUAGEExample : uP and uC
OPCODE
MICROCODE
Mircocode (Micro-operations):Operations executed on data stored in registers, performed in one clock cycle
Register Transfer Level (RTL):Symbolic notation used to describe micro-operations
Register Transfer Level (RTL)
RTL an algebraic notation used to define machine level
operations it is not executed by a computer used to explain how the computer works.
Example: In 68000 assembly language instruction
ADD#3, D2 is define in RTL as
[D2] [D2] + 3
Register Transfer Level (RTL)
Types of Registers
AR (Address Registers) DR (Data Registers) PC (Program Counters) IR (Instruction Registers) Rn (n indicates the Register
number, eg R2)
Block Diagram of Registers
R
PC(H)
Register
16 bit Register
78 bit Register
6 5 4 3 2 1 0
Bit 7 Bit 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit 16 Bit 0
PC(L)
8 bit = 1 byte
H = High order byte L = Low order byte
PC(H) = PC(15:8)
PC(L) = PC(7:0)
Basic Symbols
R followed by a number is referring to a register:
R2 = second register/register no 2
R2
M refers to Memory with addresses in square braces:
Direct Addressing :
M[10] = contents of memory address 10
In this example, M[10] refers to 10111011
100000001011101111111111
91011
Address Content
MEMORY
Basic Symbols
M refers to Memory with addresses in square braces
In-direct Addressing :
M[R3] = content of the memory address in R3
100000001011101111111111
151617
Address Content
MEMORY
100000000000011000001111
123
Address Content
REGISTER
00001111= 15
Ans : M[R3] refers to 10000000
Basic Symbols
Arrow pointing to the right shows transfer of data :
R4 R3 = Stores the value of R3 to R4
* The word transfer is misleading, since it implies that data is moved from one location to another. In fact, the data is copied from one location to another since it also still resides in register R3
Basic Symbols
A comma represents simultaneous transfer:
R1 R2, R6 R7 = Stores R2 into R1 and at the same time stores R7 into R6.
Basic Symbols
Parenthesis indicates part of the register.
R8(1) = bit 1of R8
R8
7 6 5 34 2 1 0
1 0 1 11 0 0 0
Bit Position
Content
MSB LSB
LSB : Least Significant BitMSB : Most Significant Bit
Basic Symbols
Parenthesis indicates part of the register.
R3(7:0) = the least significant byte of R3
Note : 1 byte = 8 bit
R3
7 6 5 34 2 1 0
1 0 1 11 0 0 0
14..915 8
10..1
Basic Symbols
Mathematical and Logical Symbols
Addition is indicated by the + sign:
R1 R2+R3
Add R2 and R3, stores in R1
R2 R4+R1
Add R4 and R1, stores in R2
Example 1 :
Example 2 :
Subtraction is handled not with the minus sign but with complementing.
1’s complement :
2’s complement :
R5 R3+R4
R5 R3+R4+1
R3 minus R4 in 1’s complement
R3 minus R4 in 2’s complement
Mathematical and Logical Symbols
EXERCISE:
Minus R2 from R1 and stores the answer in R8 (use 2’s comp method)
RTL : R8 R1+R2+1
What is the value of R8 if R1 = 01000100 and
R2 = 00100011.
Mathematical and Logical Symbols
Summary
Symbol Description Example
Square brackets Specifies an address for memory
M[R2]
Letters Denotes a register AR, IR, PC, R2
Parentheses Denotes part of a register
R2(1), R2(7:0), PC(L)
Arrow Denotes Transfer of data R1 R2
Comma Separates simultaneous transfers
R1 R2, R3 R2
Arithmetic Operations
+ Addition
- Subtraction
* Multiplication
/ Division
Example: R2 R1+R2
Example: R2 R1+R2+1
Example: R2 R1*R2
Example: R2 R1/R2
Conditional Register Transfer
Conditional Statement Using control signal to control the transfer Can be symbolised by if-then statement
If (K1 = 1) then (R2 R1)
In RTL we can write it as:
K1 : R2 R1
A subscripted letter followed by a colon is a conditional
Conditional Register Transfer
R2R1
K1
CLK
n
K1
CLK
Transfer occurs here
n = no of lines = no of bits
Transfer occurs in parallel
K1 : R2 R1
Conditional Register Transfer
Content of R2 will be stored in R5 when condition K1 occurs:
R5
R2
K
K1 :R5 R2Example:
Summary
Note : Any register may be specified for source 1, source 2, or destination.
Logical Operations v OR (SETS Bits)
^ AND (CLEARS Bits)
+ EXOR (Complement Bits, 2 Sources)
NOT (Complement Bits, 1 Source)
Example: R3 R4 v R6
Example: R2 DR ^ R1
Example: PC PC + DR
Example: R6 R1
Logical Operations
Example: Let R1 =
10101010 and R2 = 11110000
After the operations, R0 becomes:
Shift Operations
To Shift left and shift right operations:
Shift Operations
Example 1: Let R2 = 11001001 After the Shift operation, R1 becomes:
Note: These shifts "zero fill". Sometimes a separate flip-flop is used to provide the data shifted in, or to “catch” the data shifted out
Shift Operations Example 2 : shift left operation
P : R1 sl R1
If R1 = 1001, then sl R1 = 0010 sr R1 = 0100
R13 R12 R11 R10 0
P
Zero Fill
Assignment#1
Given the 16-bit operand 0010 0111 1011 1010,
what operation must be performed and what operand must be used:
a)to clear all even bit positions to 0? (Assume bit positions are 15 through 0
from left to right)b) to set the leftmost 4 bits to 1?c) to complement the centre 8 bits?
Thank you